From patchwork Mon Dec 7 14:25:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 339242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71347C4361B for ; Mon, 7 Dec 2020 14:26:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 43E6220784 for ; Mon, 7 Dec 2020 14:26:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726042AbgLGO06 (ORCPT ); Mon, 7 Dec 2020 09:26:58 -0500 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:59333 "EHLO out5-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725803AbgLGO06 (ORCPT ); Mon, 7 Dec 2020 09:26:58 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2C5115C00F9; Mon, 7 Dec 2020 09:26:12 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Mon, 07 Dec 2020 09:26:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=SBALsPNYnP1HF pXf5N2yZ6Vi3FshNtci6dnwoaQoJw8=; b=GKnED2dDKK4vPgHovpWSCRWDNRj1a D0GLqDZlfRA4nLfZYgDJ3eYrDVGLO9+n/SQp9mMZQ4XmM0kTj4XvX/WBoqxmk5r6 DdgAvLNmQSpjaJrtNy1zQZ8wAXSO42uxPAIwr2ezPRVk8Yy9jEmNS2VB5pDzoZEG fewPeFRqzjQANUkxO2u1LBpn2Gnc5/ndFv12RPn5UWvN6rFVs59XKLFyWGe7zBlc MMql0nUOMzU+rltiF/ztd3vzzA88/OBYzwNdBMQK2ZMabPtdjS7+bj4D6UJJISpv mn20I9t4fuEK5LUOV9omppOyAWXPCBHoqf51mixkFPiPPbUoeNRzyK3Kw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=SBALsPNYnP1HFpXf5N2yZ6Vi3FshNtci6dnwoaQoJw8=; b=ibGRSqgy KhOHX5qRkRueYHjQVdkJzVNBa8THZr31TM1O4lgwCOGkR6N0Vh+Z5Yas696uZaze 0ASV+8INlRAu3VgDsiQssWsweNzvxecBOoNBr1G4uZcmhZnxEnj09MJxuviU/f98 LW3MUkIGGQYN5rCt0l5XVl2CUT27JNPgc1lYmRQfQXQFDbz1xWTOXjawS8w3vm/u SsS85XAIP07bfdsAkZl5Pt06YQ2MrTTpuE9pcSmWFjk1Tbr4GRe5D2pT7chxcbmQ essZmSCdoh17qL27ppmklrV9UBiGH47Tum+allqypcFF9D4JYvag1iH15EzlRN3M Qq6pQDrS9LqV9Q== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedrudejgedgieefucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomheptehnughrvgifucflvghffhgvrhihuceorghnughrvgifsegr jhdrihgurdgruheqnecuggftrfgrthhtvghrnhepjefgvdevheetkeevgeegleelgfelte etjeffleffvdduudevieffgeetleevhfetnecukfhppedvtdefrdehjedrvddtkedrudeg ieenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpegrnh gurhgvfiesrghjrdhiugdrrghu X-ME-Proxy: Received: from localhost.localdomain (203-57-208-146.dyn.iinet.net.au [203.57.208.146]) by mail.messagingengine.com (Postfix) with ESMTPA id BD0931080059; Mon, 7 Dec 2020 09:26:08 -0500 (EST) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Cc: ulf.hansson@linaro.org, robh+dt@kernel.org, joel@jms.id.au, adrian.hunter@intel.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, ryan_chen@aspeedtech.com Subject: [PATCH v4 1/6] mmc: core: Add helper for parsing clock phase properties Date: Tue, 8 Dec 2020 00:55:51 +1030 Message-Id: <20201207142556.2045481-2-andrew@aj.id.au> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201207142556.2045481-1-andrew@aj.id.au> References: <20201207142556.2045481-1-andrew@aj.id.au> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Drivers for MMC hosts that accept phase corrections can take advantage of the helper by embedding a mmc_clk_phase_map_t object in their private data and invoking mmc_of_parse_clk_phase() to extract phase parameters. It is the responsibility of the host driver to translate and apply the extracted values to hardware as required. Signed-off-by: Andrew Jeffery --- drivers/mmc/core/host.c | 43 ++++++++++++++++++++++++++++++++++++++++ include/linux/mmc/host.h | 17 ++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 96b2ca1f1b06..d03518f2e654 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -163,6 +163,49 @@ static void mmc_retune_timer(struct timer_list *t) mmc_retune_needed(host); } +static void mmc_of_parse_timing_phase(struct device *dev, const char *prop, + struct mmc_clk_phase *phase) +{ + int degrees[2] = {0}; + int rc; + + rc = device_property_read_u32_array(dev, prop, degrees, 2); + phase->valid = !rc; + if (phase->valid) { + phase->in_deg = degrees[0]; + phase->out_deg = degrees[1]; + } +} + +void +mmc_of_parse_clk_phase(struct mmc_host *host, mmc_clk_phase_map_t map) +{ + struct device *dev = host->parent; + + mmc_of_parse_timing_phase(dev, "clk-phase-legacy", + &map[MMC_TIMING_LEGACY]); + mmc_of_parse_timing_phase(dev, "clk-phase-mmc-hs", + &map[MMC_TIMING_MMC_HS]); + mmc_of_parse_timing_phase(dev, "clk-phase-sd-hs", + &map[MMC_TIMING_SD_HS]); + mmc_of_parse_timing_phase(dev, "clk-phase-uhs-sdr12", + &map[MMC_TIMING_UHS_SDR12]); + mmc_of_parse_timing_phase(dev, "clk-phase-uhs-sdr25", + &map[MMC_TIMING_UHS_SDR25]); + mmc_of_parse_timing_phase(dev, "clk-phase-uhs-sdr50", + &map[MMC_TIMING_UHS_SDR50]); + mmc_of_parse_timing_phase(dev, "clk-phase-uhs-sdr104", + &map[MMC_TIMING_UHS_SDR104]); + mmc_of_parse_timing_phase(dev, "clk-phase-uhs-ddr50", + &map[MMC_TIMING_UHS_DDR50]); + mmc_of_parse_timing_phase(dev, "clk-phase-mmc-ddr52", + &map[MMC_TIMING_MMC_DDR52]); + mmc_of_parse_timing_phase(dev, "clk-phase-mmc-hs200", + &map[MMC_TIMING_MMC_HS200]); + mmc_of_parse_timing_phase(dev, "clk-phase-mmc-hs400", + &map[MMC_TIMING_MMC_HS400]); +} + /** * mmc_of_parse() - parse host's device-tree node * @host: host whose node should be parsed. diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 01bba36545c5..bc4731c9738f 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -79,6 +79,22 @@ struct mmc_ios { bool enhanced_strobe; /* hs400es selection */ }; +struct mmc_clk_phase { + bool valid; + u16 in_deg; + u16 out_deg; +}; + +/* + * Define a type to map between bus timings and phase correction values. To + * avoid bloat in struct mmc_host we leave it to the host driver to define the + * phase map object in its private data if it supports phase correction. + * However, mmc_of_parse_clk_phase() is provided by the mmc core and needs the + * provided array to be correctly sized, so typedef an appropriately sized + * array to minimise the chance that the wrong size object is passed. + */ +typedef struct mmc_clk_phase mmc_clk_phase_map_t[MMC_TIMING_MMC_HS400 + 1]; + struct mmc_host; struct mmc_host_ops { @@ -490,6 +506,7 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *); int mmc_add_host(struct mmc_host *); void mmc_remove_host(struct mmc_host *); void mmc_free_host(struct mmc_host *); +void mmc_of_parse_clk_phase(struct mmc_host *host, mmc_clk_phase_map_t map); int mmc_of_parse(struct mmc_host *host); int mmc_of_parse_voltage(struct device_node *np, u32 *mask); From patchwork Mon Dec 7 14:25:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 339240 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9637FC2BB3F for ; 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Mon, 7 Dec 2020 09:26:12 -0500 (EST) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Cc: ulf.hansson@linaro.org, robh+dt@kernel.org, joel@jms.id.au, adrian.hunter@intel.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, ryan_chen@aspeedtech.com Subject: [PATCH v4 2/6] mmc: sdhci-of-aspeed: Expose clock phase controls Date: Tue, 8 Dec 2020 00:55:52 +1030 Message-Id: <20201207142556.2045481-3-andrew@aj.id.au> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201207142556.2045481-1-andrew@aj.id.au> References: <20201207142556.2045481-1-andrew@aj.id.au> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Aspeed SD/eMMC controllers expose configurable clock phase correction by inserting delays of up to 15 logic elements in length into the bus clock path. The hardware supports independent configuration for both bus directions on a per-slot basis. The timing delay per element encoded in the driver was experimentally determined by scope measurements. The phase controls for both slots are grouped together in a single register of the global register block of the SD/MMC controller(s), which drives the use of a locking scheme between the SDHCIs and the global register set. Signed-off-by: Andrew Jeffery --- drivers/mmc/host/sdhci-of-aspeed.c | 216 +++++++++++++++++++++++++++-- 1 file changed, 208 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c index 4f008ba3280e..788ec7728227 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -16,9 +17,19 @@ #include "sdhci-pltfm.h" -#define ASPEED_SDC_INFO 0x00 -#define ASPEED_SDC_S1MMC8 BIT(25) -#define ASPEED_SDC_S0MMC8 BIT(24) +#define ASPEED_SDC_INFO 0x00 +#define ASPEED_SDC_S1_MMC8 BIT(25) +#define ASPEED_SDC_S0_MMC8 BIT(24) +#define ASPEED_SDC_PHASE 0xf4 +#define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21) +#define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16) +#define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11) +#define ASPEED_SDC_S1_PHASE_IN_EN BIT(10) +#define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8) +#define ASPEED_SDC_S0_PHASE_OUT GENMASK(7, 3) +#define ASPEED_SDC_S0_PHASE_IN_EN BIT(2) +#define ASPEED_SDC_S0_PHASE_OUT_EN GENMASK(1, 0) +#define ASPEED_SDC_PHASE_MAX 31 struct aspeed_sdc { struct clk *clk; @@ -28,9 +39,36 @@ struct aspeed_sdc { void __iomem *regs; }; +struct aspeed_sdhci_tap_param { + bool valid; + +#define ASPEED_SDHCI_TAP_PARAM_INVERT_CLK BIT(4) + u8 in; + u8 out; +}; + +struct aspeed_sdhci_tap_desc { + u32 tap_mask; + u32 enable_mask; + u8 enable_value; +}; + +struct aspeed_sdhci_phase_desc { + struct aspeed_sdhci_tap_desc in; + struct aspeed_sdhci_tap_desc out; +}; + +struct aspeed_sdhci_pdata { + const struct aspeed_sdhci_phase_desc *phase_desc; + size_t nr_phase_descs; +}; + struct aspeed_sdhci { + const struct aspeed_sdhci_pdata *pdata; struct aspeed_sdc *parent; u32 width_mask; + mmc_clk_phase_map_t phase_map; + const struct aspeed_sdhci_phase_desc *phase_desc; }; static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc, @@ -50,10 +88,118 @@ static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc, spin_unlock(&sdc->lock); } +static u32 +aspeed_sdc_set_phase_tap(const struct aspeed_sdhci_tap_desc *desc, + u8 tap, bool enable, u32 reg) +{ + reg &= ~(desc->enable_mask | desc->tap_mask); + if (enable) { + reg |= tap << __ffs(desc->tap_mask); + reg |= desc->enable_value << __ffs(desc->enable_mask); + } + + return reg; +} + +static void +aspeed_sdc_set_phase_taps(struct aspeed_sdc *sdc, + const struct aspeed_sdhci_phase_desc *desc, + const struct aspeed_sdhci_tap_param *taps) +{ + u32 reg; + + spin_lock(&sdc->lock); + reg = readl(sdc->regs + ASPEED_SDC_PHASE); + + reg = aspeed_sdc_set_phase_tap(&desc->in, taps->in, taps->valid, reg); + reg = aspeed_sdc_set_phase_tap(&desc->out, taps->out, taps->valid, reg); + + writel(reg, sdc->regs + ASPEED_SDC_PHASE); + spin_unlock(&sdc->lock); +} + +#define PICOSECONDS_PER_SECOND 1000000000000ULL +#define ASPEED_SDHCI_NR_TAPS 15 +/* Measured value with *handwave* environmentals and static loading */ +#define ASPEED_SDHCI_MAX_TAP_DELAY_PS 1253 +static int aspeed_sdhci_phase_to_tap(struct device *dev, unsigned long rate_hz, + int phase_deg) +{ + u64 phase_period_ps; + u64 prop_delay_ps; + u64 clk_period_ps; + unsigned int tap; + u8 inverted; + + phase_deg %= 360; + + if (phase_deg >= 180) { + inverted = ASPEED_SDHCI_TAP_PARAM_INVERT_CLK; + phase_deg -= 180; + dev_dbg(dev, + "Inverting clock to reduce phase correction from %d to %d degrees\n", + phase_deg + 180, phase_deg); + } else { + inverted = 0; + } + + prop_delay_ps = ASPEED_SDHCI_MAX_TAP_DELAY_PS / ASPEED_SDHCI_NR_TAPS; + clk_period_ps = div_u64(PICOSECONDS_PER_SECOND, (u64)rate_hz); + phase_period_ps = div_u64((u64)phase_deg * clk_period_ps, 360ULL); + + tap = div_u64(phase_period_ps, prop_delay_ps); + if (tap > ASPEED_SDHCI_NR_TAPS) { + dev_warn(dev, + "Requested out of range phase tap %d for %d degrees of phase compensation at %luHz, clamping to tap %d\n", + tap, phase_deg, rate_hz, ASPEED_SDHCI_NR_TAPS); + tap = ASPEED_SDHCI_NR_TAPS; + } + + return inverted | tap; +} + +static void +aspeed_sdhci_phases_to_taps(struct device *dev, unsigned long rate, + const struct mmc_clk_phase *phases, + struct aspeed_sdhci_tap_param *taps) +{ + taps->valid = phases->valid; + + if (!phases->valid) + return; + + taps->in = aspeed_sdhci_phase_to_tap(dev, rate, phases->in_deg); + taps->out = aspeed_sdhci_phase_to_tap(dev, rate, phases->out_deg); +} + +static void +aspeed_sdhci_configure_phase(struct sdhci_host *host, unsigned long rate) +{ + struct aspeed_sdhci_tap_param _taps = {0}, *taps = &_taps; + struct mmc_clk_phase *params; + struct aspeed_sdhci *sdhci; + struct device *dev; + + dev = host->mmc->parent; + sdhci = sdhci_pltfm_priv(sdhci_priv(host)); + + if (!sdhci->phase_desc) + return; + + params = &sdhci->phase_map[host->timing]; + aspeed_sdhci_phases_to_taps(dev, rate, params, taps); + aspeed_sdc_set_phase_taps(sdhci->parent, sdhci->phase_desc, taps); + dev_dbg(dev, + "Using taps [%d, %d] for [%d, %d] degrees of phase correction at %luHz (%d)\n", + taps->in & ASPEED_SDHCI_NR_TAPS, + taps->out & ASPEED_SDHCI_NR_TAPS, + params->in_deg, params->out_deg, rate, host->timing); +} + static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host; - unsigned long parent; + unsigned long parent, bus; int div; u16 clk; @@ -69,13 +215,17 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) clock = host->max_clk; for (div = 2; div < 256; div *= 2) { - if ((parent / div) <= clock) + bus = parent / div; + if (bus <= clock) break; } + div >>= 1; clk = div << SDHCI_DIVIDER_SHIFT; + aspeed_sdhci_configure_phase(host, bus); + sdhci_enable_clk(host, clk); } @@ -157,6 +307,7 @@ static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev, static int aspeed_sdhci_probe(struct platform_device *pdev) { + const struct aspeed_sdhci_pdata *aspeed_pdata; struct sdhci_pltfm_host *pltfm_host; struct aspeed_sdhci *dev; struct sdhci_host *host; @@ -164,12 +315,15 @@ static int aspeed_sdhci_probe(struct platform_device *pdev) int slot; int ret; + aspeed_pdata = of_device_get_match_data(&pdev->dev); + host = sdhci_pltfm_init(pdev, &aspeed_sdhci_pdata, sizeof(*dev)); if (IS_ERR(host)) return PTR_ERR(host); pltfm_host = sdhci_priv(host); dev = sdhci_pltfm_priv(pltfm_host); + dev->pdata = aspeed_pdata; dev->parent = dev_get_drvdata(pdev->dev.parent); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -180,8 +334,17 @@ static int aspeed_sdhci_probe(struct platform_device *pdev) else if (slot >= 2) return -EINVAL; - dev_info(&pdev->dev, "Configuring for slot %d\n", slot); - dev->width_mask = !slot ? ASPEED_SDC_S0MMC8 : ASPEED_SDC_S1MMC8; + if (dev->pdata && slot < dev->pdata->nr_phase_descs) { + dev->phase_desc = &dev->pdata->phase_desc[slot]; + } else { + dev_info(&pdev->dev, + "Phase control not supported for slot %d\n", slot); + dev->phase_desc = NULL; + } + + dev->width_mask = !slot ? ASPEED_SDC_S0_MMC8 : ASPEED_SDC_S1_MMC8; + + dev_info(&pdev->dev, "Configured for slot %d\n", slot); sdhci_get_of_property(pdev); @@ -199,6 +362,9 @@ static int aspeed_sdhci_probe(struct platform_device *pdev) if (ret) goto err_sdhci_add; + if (dev->phase_desc) + mmc_of_parse_clk_phase(host->mmc, dev->phase_map); + ret = sdhci_add_host(host); if (ret) goto err_sdhci_add; @@ -230,10 +396,44 @@ static int aspeed_sdhci_remove(struct platform_device *pdev) return 0; } +static const struct aspeed_sdhci_phase_desc ast2600_sdhci_phase[] = { + /* SDHCI/Slot 0 */ + [0] = { + .in = { + .tap_mask = ASPEED_SDC_S0_PHASE_IN, + .enable_mask = ASPEED_SDC_S0_PHASE_IN_EN, + .enable_value = 1, + }, + .out = { + .tap_mask = ASPEED_SDC_S0_PHASE_OUT, + .enable_mask = ASPEED_SDC_S0_PHASE_OUT_EN, + .enable_value = 3, + }, + }, + /* SDHCI/Slot 1 */ + [1] = { + .in = { + .tap_mask = ASPEED_SDC_S1_PHASE_IN, + .enable_mask = ASPEED_SDC_S1_PHASE_IN_EN, + .enable_value = 1, + }, + .out = { + .tap_mask = ASPEED_SDC_S1_PHASE_OUT, + .enable_mask = ASPEED_SDC_S1_PHASE_OUT_EN, + .enable_value = 3, + }, + }, +}; + +static const struct aspeed_sdhci_pdata ast2600_sdhci_pdata = { + .phase_desc = ast2600_sdhci_phase, + .nr_phase_descs = ARRAY_SIZE(ast2600_sdhci_phase), +}; + static const struct of_device_id aspeed_sdhci_of_match[] = { { .compatible = "aspeed,ast2400-sdhci", }, { .compatible = "aspeed,ast2500-sdhci", }, - { .compatible = "aspeed,ast2600-sdhci", }, + { .compatible = "aspeed,ast2600-sdhci", .data = &ast2600_sdhci_pdata, }, { } }; From patchwork Mon Dec 7 14:25:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 339940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E20B2C2BB40 for ; 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Mon, 7 Dec 2020 09:26:16 -0500 (EST) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Cc: ulf.hansson@linaro.org, robh+dt@kernel.org, joel@jms.id.au, adrian.hunter@intel.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, ryan_chen@aspeedtech.com Subject: [PATCH v4 3/6] mmc: sdhci-of-aspeed: Add AST2600 bus clock support Date: Tue, 8 Dec 2020 00:55:53 +1030 Message-Id: <20201207142556.2045481-4-andrew@aj.id.au> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201207142556.2045481-1-andrew@aj.id.au> References: <20201207142556.2045481-1-andrew@aj.id.au> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AST2600 can achieve HS200 speeds with a change to the bus clock divisor behaviour. The divisor can also be more accurate with respect to the requested clock rate, but keep the one-hot behaviour for backwards compatibility with the AST2400 and AST2500. Signed-off-by: Andrew Jeffery --- drivers/mmc/host/sdhci-of-aspeed.c | 37 ++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c index 788ec7728227..0a181b104752 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -59,6 +59,7 @@ struct aspeed_sdhci_phase_desc { }; struct aspeed_sdhci_pdata { + unsigned int clk_div_start; const struct aspeed_sdhci_phase_desc *phase_desc; size_t nr_phase_descs; }; @@ -200,10 +201,13 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host; unsigned long parent, bus; + struct aspeed_sdhci *sdhci; int div; u16 clk; pltfm_host = sdhci_priv(host); + sdhci = sdhci_pltfm_priv(pltfm_host); + parent = clk_get_rate(pltfm_host->clk); sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); @@ -214,7 +218,23 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) if (WARN_ON(clock > host->max_clk)) clock = host->max_clk; - for (div = 2; div < 256; div *= 2) { + /* + * Regarding the AST2600: + * + * If (EMMC12C[7:6], EMMC12C[15:8] == 0) then + * period of SDCLK = period of SDMCLK. + * + * If (EMMC12C[7:6], EMMC12C[15:8] != 0) then + * period of SDCLK = period of SDMCLK * 2 * (EMMC12C[7:6], EMMC[15:8]) + * + * If you keep EMMC12C[7:6] = 0 and EMMC12C[15:8] as one-hot, + * 0x1/0x2/0x4/etc, you will find it is compatible to AST2400 or AST2500 + * + * Keep the one-hot behaviour for backwards compatibility except for + * supporting the value 0 in (EMMC12C[7:6], EMMC12C[15:8]), and capture + * the 0-value capability in clk_div_start. + */ + for (div = sdhci->pdata->clk_div_start; div < 256; div *= 2) { bus = parent / div; if (bus <= clock) break; @@ -316,6 +336,10 @@ static int aspeed_sdhci_probe(struct platform_device *pdev) int ret; aspeed_pdata = of_device_get_match_data(&pdev->dev); + if (!aspeed_pdata) { + dev_err(&pdev->dev, "Missing platform configuration data\n"); + return -EINVAL; + } host = sdhci_pltfm_init(pdev, &aspeed_sdhci_pdata, sizeof(*dev)); if (IS_ERR(host)) @@ -334,7 +358,7 @@ static int aspeed_sdhci_probe(struct platform_device *pdev) else if (slot >= 2) return -EINVAL; - if (dev->pdata && slot < dev->pdata->nr_phase_descs) { + if (slot < dev->pdata->nr_phase_descs) { dev->phase_desc = &dev->pdata->phase_desc[slot]; } else { dev_info(&pdev->dev, @@ -396,6 +420,10 @@ static int aspeed_sdhci_remove(struct platform_device *pdev) return 0; } +static const struct aspeed_sdhci_pdata ast2400_sdhci_pdata = { + .clk_div_start = 2, +}; + static const struct aspeed_sdhci_phase_desc ast2600_sdhci_phase[] = { /* SDHCI/Slot 0 */ [0] = { @@ -426,13 +454,14 @@ static const struct aspeed_sdhci_phase_desc ast2600_sdhci_phase[] = { }; static const struct aspeed_sdhci_pdata ast2600_sdhci_pdata = { + .clk_div_start = 1, .phase_desc = ast2600_sdhci_phase, .nr_phase_descs = ARRAY_SIZE(ast2600_sdhci_phase), }; static const struct of_device_id aspeed_sdhci_of_match[] = { - { .compatible = "aspeed,ast2400-sdhci", }, - { .compatible = "aspeed,ast2500-sdhci", }, + { .compatible = "aspeed,ast2400-sdhci", .data = &ast2400_sdhci_pdata, }, + { .compatible = "aspeed,ast2500-sdhci", .data = &ast2400_sdhci_pdata, }, { .compatible = "aspeed,ast2600-sdhci", .data = &ast2600_sdhci_pdata, }, { } }; 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Mon, 7 Dec 2020 09:26:20 -0500 (EST) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Cc: ulf.hansson@linaro.org, robh+dt@kernel.org, joel@jms.id.au, adrian.hunter@intel.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, ryan_chen@aspeedtech.com Subject: [PATCH v4 4/6] mmc: sdhci-of-aspeed: Add KUnit tests for phase calculations Date: Tue, 8 Dec 2020 00:55:54 +1030 Message-Id: <20201207142556.2045481-5-andrew@aj.id.au> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201207142556.2045481-1-andrew@aj.id.au> References: <20201207142556.2045481-1-andrew@aj.id.au> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Converting degrees of phase to logic delays is irritating to test on hardware, so lets exercise the function using KUnit. Signed-off-by: Andrew Jeffery --- drivers/mmc/host/Kconfig | 14 ++++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-of-aspeed-test.c | 100 ++++++++++++++++++++++++ 3 files changed, 115 insertions(+) create mode 100644 drivers/mmc/host/sdhci-of-aspeed-test.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 596f32637315..9f910655d6ea 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -168,6 +168,20 @@ config MMC_SDHCI_OF_ASPEED If unsure, say N. +config MMC_SDHCI_OF_ASPEED_TEST + bool "Test for the ASPEED SDHCI controller" + depends on MMC_SDHCI_OF_ASPEED && KUNIT + help + Enable KUnit tests for the ASPEED SDHCI driver. Select this + option only if you will boot the kernel for the purpose of running + unit tests (e.g. under UML or qemu). + + The KUnit tests generally exercise parts of the driver that do not + directly touch the hardware, for example, the phase correction + calculations. + + If unsure, say N. + config MMC_SDHCI_OF_AT91 tristate "SDHCI OF support for the Atmel SDMMC controller" depends on MMC_SDHCI_PLTFM diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 451c25fc2c69..3ee59d5802cf 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -90,6 +90,7 @@ obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o obj-$(CONFIG_MMC_SDHCI_OF_ARASAN) += sdhci-of-arasan.o obj-$(CONFIG_MMC_SDHCI_OF_ASPEED) += sdhci-of-aspeed.o +obj-$(CONFIG_MMC_SDHCI_OF_ASPEED_TEST) += sdhci-of-aspeed-test.o obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o diff --git a/drivers/mmc/host/sdhci-of-aspeed-test.c b/drivers/mmc/host/sdhci-of-aspeed-test.c new file mode 100644 index 000000000000..fb79b278fb81 --- /dev/null +++ b/drivers/mmc/host/sdhci-of-aspeed-test.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2020 IBM Corp. */ + +#include + +#include "sdhci-of-aspeed.c" + +static void aspeed_sdhci_phase_ddr52(struct kunit *test) +{ + int rate = 52000000; + + KUNIT_EXPECT_EQ(test, 0, + aspeed_sdhci_phase_to_tap(NULL, rate, 0)); + KUNIT_EXPECT_EQ(test, 0, + aspeed_sdhci_phase_to_tap(NULL, rate, 1)); + KUNIT_EXPECT_EQ(test, 1, + aspeed_sdhci_phase_to_tap(NULL, rate, 2)); + KUNIT_EXPECT_EQ(test, 1, + aspeed_sdhci_phase_to_tap(NULL, rate, 3)); + KUNIT_EXPECT_EQ(test, 2, + aspeed_sdhci_phase_to_tap(NULL, rate, 4)); + KUNIT_EXPECT_EQ(test, 3, + aspeed_sdhci_phase_to_tap(NULL, rate, 5)); + KUNIT_EXPECT_EQ(test, 14, + aspeed_sdhci_phase_to_tap(NULL, rate, 23)); + KUNIT_EXPECT_EQ(test, 15, + aspeed_sdhci_phase_to_tap(NULL, rate, 24)); + KUNIT_EXPECT_EQ(test, 15, + aspeed_sdhci_phase_to_tap(NULL, rate, 25)); + + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 0, + aspeed_sdhci_phase_to_tap(NULL, rate, 180)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 0, + aspeed_sdhci_phase_to_tap(NULL, rate, 181)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 1, + aspeed_sdhci_phase_to_tap(NULL, rate, 182)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 1, + aspeed_sdhci_phase_to_tap(NULL, rate, 183)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 2, + aspeed_sdhci_phase_to_tap(NULL, rate, 184)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 3, + aspeed_sdhci_phase_to_tap(NULL, rate, 185)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 14, + aspeed_sdhci_phase_to_tap(NULL, rate, 203)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 15, + aspeed_sdhci_phase_to_tap(NULL, rate, 204)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 15, + aspeed_sdhci_phase_to_tap(NULL, rate, 205)); +} + +static void aspeed_sdhci_phase_hs200(struct kunit *test) +{ + int rate = 200000000; + + KUNIT_EXPECT_EQ(test, 0, + aspeed_sdhci_phase_to_tap(NULL, rate, 0)); + KUNIT_EXPECT_EQ(test, 0, + aspeed_sdhci_phase_to_tap(NULL, rate, 5)); + KUNIT_EXPECT_EQ(test, 1, + aspeed_sdhci_phase_to_tap(NULL, rate, 6)); + KUNIT_EXPECT_EQ(test, 1, + aspeed_sdhci_phase_to_tap(NULL, rate, 7)); + KUNIT_EXPECT_EQ(test, 14, + aspeed_sdhci_phase_to_tap(NULL, rate, 89)); + KUNIT_EXPECT_EQ(test, 15, + aspeed_sdhci_phase_to_tap(NULL, rate, 90)); + KUNIT_EXPECT_EQ(test, 15, + aspeed_sdhci_phase_to_tap(NULL, rate, 91)); + KUNIT_EXPECT_EQ(test, 15, + aspeed_sdhci_phase_to_tap(NULL, rate, 96)); + + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK, + aspeed_sdhci_phase_to_tap(NULL, rate, 180)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK, + aspeed_sdhci_phase_to_tap(NULL, rate, 185)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 1, + aspeed_sdhci_phase_to_tap(NULL, rate, 186)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 1, + aspeed_sdhci_phase_to_tap(NULL, rate, 187)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 14, + aspeed_sdhci_phase_to_tap(NULL, rate, 269)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 15, + aspeed_sdhci_phase_to_tap(NULL, rate, 270)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 15, + aspeed_sdhci_phase_to_tap(NULL, rate, 271)); + KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 15, + aspeed_sdhci_phase_to_tap(NULL, rate, 276)); +} + +static struct kunit_case aspeed_sdhci_test_cases[] = { + KUNIT_CASE(aspeed_sdhci_phase_ddr52), + KUNIT_CASE(aspeed_sdhci_phase_hs200), + {} +}; + +static struct kunit_suite aspeed_sdhci_test_suite = { + .name = "sdhci-of-aspeed", + .test_cases = aspeed_sdhci_test_cases, +}; +kunit_test_suite(aspeed_sdhci_test_suite); From patchwork Mon Dec 7 14:25:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 339939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B01EC433FE for ; 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Mon, 7 Dec 2020 09:26:24 -0500 (EST) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Cc: ulf.hansson@linaro.org, robh+dt@kernel.org, joel@jms.id.au, adrian.hunter@intel.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, ryan_chen@aspeedtech.com Subject: [PATCH v4 5/6] MAINTAINERS: Add entry for the ASPEED SD/MMC driver Date: Tue, 8 Dec 2020 00:55:55 +1030 Message-Id: <20201207142556.2045481-6-andrew@aj.id.au> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201207142556.2045481-1-andrew@aj.id.au> References: <20201207142556.2045481-1-andrew@aj.id.au> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add myself as the maintainer. Signed-off-by: Andrew Jeffery --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e451dcce054f..eae4322aae67 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2826,6 +2826,15 @@ F: Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic. F: drivers/irqchip/irq-aspeed-scu-ic.c F: include/dt-bindings/interrupt-controller/aspeed-scu-ic.h +ASPEED SD/MMC DRIVER +M: Andrew Jeffery +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) +L: openbmc@lists.ozlabs.org (moderated for non-subscribers) +L: linux-mmc@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml +F: drivers/mmc/host/sdhci-of-aspeed* + ASPEED VIDEO ENGINE DRIVER M: Eddie James L: linux-media@vger.kernel.org From patchwork Mon Dec 7 14:25:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 339239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F8B2C2BB48 for ; Mon, 7 Dec 2020 14:28:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EDA0820784 for ; Mon, 7 Dec 2020 14:28:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727243AbgLGO2F (ORCPT ); Mon, 7 Dec 2020 09:28:05 -0500 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:47485 "EHLO out5-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727162AbgLGO2F (ORCPT ); Mon, 7 Dec 2020 09:28:05 -0500 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id 8BF085C016D; Mon, 7 Dec 2020 09:26:32 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Mon, 07 Dec 2020 09:26:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=R9UFuHjtAK1qQ YI8cmha4Thpo1402hfejrmvtlGfR4Y=; b=QEkimx7HDJZ+IdrzB2b+g1CaF61st 5NUPY0JxfA2xDmdNhq/XdQn1gUt70WSuqyvJA7p/IUrPZJwz711GERDm1bZdTt0T VX3rDZsypDoZBBheimOIwcetdhHJOtm/ug7kMHco/Iiu76vrVndza7hDpLC3Msxc DqO9nK4ZRJ/RbkTGvilDlANONIJ3IyBdYaZMnaRAkIQ/NPdpwxkvHR0jPOobCKvC fW4oyYC65zXUzGxFIoyfnn1SKbpoPtbhRx90+9X09RJTll7bnZ2l6O3GLZarvHYm paR2pEjKqMnNt3Jae/QaTodaHaGTftCgqMjbDudwdAGVF6snXZrzWh20w== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=R9UFuHjtAK1qQYI8cmha4Thpo1402hfejrmvtlGfR4Y=; b=F2eQNWp3 pxSaft5+Elh4+p6w4zEHfDw6Cxh1Zt+HxWJyLefzP+sfoma64UvUiHUVBmFNSt/Q ysdQqwN761NxDaP4H9OwX81EPbRVTPdpJ/taEjkdzLA9H0y2CrR15df4iemeZtLJ ilS9NWWm5ppna+qxlyzUjEV+3dEarJ0KCNWqpc2jYN/kG25TBv+nLoO8cNvicqvY gY59M4wZXeZQ0uiTaBRzPuJRc2r65W/e9uoXeBUS6Cbsn0x0kbIohbbvmcNsnNvp HGRX3rI/s9+FzzxCc3T6SetUy/y6V2IKK76J4fQ+YISGOBLXJIViN+29iEF6RQCS u86w6PO5z59/OA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedrudejgedgieegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomheptehnughrvgifucflvghffhgvrhihuceorghnughrvgifsegr jhdrihgurdgruheqnecuggftrfgrthhtvghrnhepjefgvdevheetkeevgeegleelgfelte etjeffleffvdduudevieffgeetleevhfetnecukfhppedvtdefrdehjedrvddtkedrudeg ieenucevlhhushhtvghrufhiiigvpedvnecurfgrrhgrmhepmhgrihhlfhhrohhmpegrnh gurhgvfiesrghjrdhiugdrrghu X-ME-Proxy: Received: from localhost.localdomain (203-57-208-146.dyn.iinet.net.au [203.57.208.146]) by mail.messagingengine.com (Postfix) with ESMTPA id 217CE1080063; Mon, 7 Dec 2020 09:26:28 -0500 (EST) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Cc: ulf.hansson@linaro.org, robh+dt@kernel.org, joel@jms.id.au, adrian.hunter@intel.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, ryan_chen@aspeedtech.com Subject: [PATCH v4 6/6] ARM: dts: rainier: Add eMMC clock phase compensation Date: Tue, 8 Dec 2020 00:55:56 +1030 Message-Id: <20201207142556.2045481-7-andrew@aj.id.au> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201207142556.2045481-1-andrew@aj.id.au> References: <20201207142556.2045481-1-andrew@aj.id.au> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Determined by scope measurements at speed. Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 21ae880c7530..ab8d37d49f30 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -186,6 +186,7 @@ &pinctrl_emmc_default { &emmc { status = "okay"; + clk-phase-mmc-hs200 = <180>, <180>; }; &fsim0 {