From patchwork Fri Dec 4 08:58:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 338513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B349C4361A for ; Fri, 4 Dec 2020 09:00:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 241FF222B6 for ; Fri, 4 Dec 2020 09:00:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728854AbgLDJA0 (ORCPT ); Fri, 4 Dec 2020 04:00:26 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:41893 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726860AbgLDJA0 (ORCPT ); Fri, 4 Dec 2020 04:00:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1607072425; x=1638608425; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hd8ZmjId7vBbXQM1jz5+4Nu+51CF6i4iXNW7aRPTEWM=; b=ZBWg4gq+2MNB5vaNSMIdkwxm1fOporNa83h+/unjzyc3XvZU6nNQnNDI vKx0+0glU6A0rLu4jO7N1I6qiDBWoKxoHcpZKbYtc5cWZik3Tl9X0xee1 lXbDVY4UCewQEq3vaH14BD+Gg3kqX2C6abBWRuARwn/qv4NyLZK14Er74 smEtrX8gcmoQBsU3ygUgoMn3H3TdOtzp0JDDVQqIi7ule88M6uiL/UlD4 10tAtzx+myVyQN3YNv6S6BogY60RoBVuCGzYTayG2oUqo47CfNDd31Ffz 1yMiotWJIgN8yy78hqdAC0yt8ASYlYi914V9keiLhU3mCSWz9h/+sa+CH A==; IronPort-SDR: cY9dAJSm1SPbcoIh62NBx3SMW8TAEpLeV+NGOGs959m+u2coiyp1ZO/m7lokcQcJ7Vd9pvWNAz d08vzzPo3ab8epw+scgrLomoxG3n7IVcnH1g1GGkli/9kuxw8ABSRdZ5Ou0jQTJ5ZXOW9gzbNp RZEd6hme4SJYwfHaDgPMN9DzT9I5tzDM5dThEgb3VMH/TnHA/uM34yoHz91n51iw3avuohVtwy pYtXAZLcns3I6FXoInz6fU5eNWa61W6tQUeug5qLdODjv/KxBpOI+btLs8TkBVWYW2IVEflR4G RKM= X-IronPort-AV: E=Sophos;i="5.78,392,1599494400"; d="scan'208";a="258129844" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 04 Dec 2020 17:18:03 +0800 IronPort-SDR: AIGhHAeu70aBtnDXVT9Rh4Vl8v9v5OVXufL+qT0Zv25kAezq9qrObmELGZ/mFeemAMF8Q2ORAE NXaPK77ZBHFYV2VJ8/zcRio3zn6ti1naU= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 00:44:11 -0800 IronPort-SDR: YOD2hDxJzF7vnxvNHifPyI2Oz/45hnF4x7vnKsbiL5xlYmiL7JrCkysKlgtj+4NhYzIIZq7lHn cAyt4lJHnBqg== WDCIronportException: Internal Received: from cnf010505.ad.shared (HELO jedi-01.hgst.com) ([10.86.61.200]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Dec 2020 00:58:39 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Bin Meng , Anup Patel , Albert Ou , Alistair Francis , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring , Ivan.Griffin@microchip.com, Cyril.Jean@microchip.com, Daire McNamara , Conor.Dooley@microchip.com Subject: [PATCH v3 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Date: Fri, 4 Dec 2020 00:58:31 -0800 Message-Id: <20201204085835.2406541-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204085835.2406541-1-atish.patra@wdc.com> References: <20201204085835.2406541-1-atish.patra@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Microchip PolarFire kconfig option which selects SoC specific and common drivers that is required for this SoC. Signed-off-by: Atish Patra Reviewed-by: Bin Meng Reviewed-by: Anup Patel --- arch/riscv/Kconfig.socs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 8a55f6156661..148ab095966b 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,12 @@ menu "SoC selection" +config SOC_MICROCHIP_POLARFIRE + bool "Microchip PolarFire SoCs" + select MCHP_CLK_PFSOC + select SIFIVE_PLIC + help + This enables support for Microchip PolarFire SoC platforms. + config SOC_SIFIVE bool "SiFive SoCs" select SERIAL_SIFIVE if TTY From patchwork Fri Dec 4 08:58:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 337898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A567AC4361A for ; Fri, 4 Dec 2020 09:00:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 50F50222B6 for ; Fri, 4 Dec 2020 09:00:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728004AbgLDJAv (ORCPT ); Fri, 4 Dec 2020 04:00:51 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:41999 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727875AbgLDJAv (ORCPT ); Fri, 4 Dec 2020 04:00:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1607072463; x=1638608463; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=juXAMaoC0LaiudGimn3JVw/cJS6l1iw8NO9uF2NFJUs=; b=cT2sSk7YVYMALUY2/g81jw0W7uDDuM6rQVutcX4ZvZNMx9ShCVwOEeRj QpZGNPSoeqfaw8fwS4KTz5+Bu81JEwKbYlg+rZfMrj8qzguouSL2/otIm YnrdyOSAF1tnrJBGBrnefCpw+EZqqq+OhFL3AvQWYGijbaO4Ts/IlPX44 yi9IDhBKIV9sMInDry7vW3pT6jQPc+tFI57YqPzZzD4aizEb9WkOPAbHX Z0Tw+3XwqqTa4nojiYzwgUlWo2g++mjIHOxop3I+w3S8mdHYszLDGXMd5 XjB4RlFqZH/cMaJyvjwog686c+VWHUJIY796J4wNpLjcMQzq6tgKfzmme Q==; IronPort-SDR: vyvcLQU0v2j+psJS2jevqIh/gyTFW3yayo2l97RIycAg5TcHB5tefEwAe8r+leyJRLGaWC0biv 4ME7/vBTCIc7Pzt8WXH2qzEJcGfWlLruHOcFm62/O6QWw/TLzymPXlhdqfvniAdgLMd7TeK9wy AEt31ZkMbUHzqRaTWKoi9HaGQnDlSfY/YnECapIbXmI4Mr07bWpTDbpXWB7pgQ/SMKEqHx/jqI 3XtPP6PpwTiRGs0Y1z19i9Hgf5ZDF1BBKhQYtTf84xP86pmArePFXSiBoBQ354x/975uzNJOSu fis= X-IronPort-AV: E=Sophos;i="5.78,392,1599494400"; d="scan'208";a="258129846" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 04 Dec 2020 17:18:04 +0800 IronPort-SDR: v7W+SoRZdUz7FyfFqyYKmPMJk7j7xAz13mRerbhkdS2gn0APiO8dBU+a6o9dRHeVuEoS0n54Og +pWZzCgLUWaf7Fl/JNO9cArjjzq6U6d5A= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 00:44:12 -0800 IronPort-SDR: 8+0WEGg+RGWJLmk6pntYWJW4OHU6PJa0AI68Dwjs2t23s7srBgV2EXcnLi5wtAGR+N5j6xBtoK o8yaK7wQpvFA== WDCIronportException: Internal Received: from cnf010505.ad.shared (HELO jedi-01.hgst.com) ([10.86.61.200]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Dec 2020 00:58:39 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alistair Francis , Anup Patel , Bin Meng , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring , Ivan.Griffin@microchip.com, Cyril.Jean@microchip.com, Daire McNamara , Conor.Dooley@microchip.com Subject: [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Date: Fri, 4 Dec 2020 00:58:32 -0800 Message-Id: <20201204085835.2406541-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204085835.2406541-1-atish.patra@wdc.com> References: <20201204085835.2406541-1-atish.patra@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add YAML DT binding documentation for the Microchip PolarFire SoC. It is documented at: https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide Signed-off-by: Atish Patra --- .../devicetree/bindings/riscv/microchip.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml new file mode 100644 index 000000000000..66e63c2bf359 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0 OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/microchip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC-based boards device tree bindings + +maintainers: + - Cyril Jean + - Lewis Hanly + +description: + Microchip PolarFire SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - microchip,mpfs-icicle-kit + - const: microchip,polarfire-soc + - const: microchip,mpfs + +additionalProperties: true + +... From patchwork Fri Dec 4 08:58:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 338512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7790C433FE for ; Fri, 4 Dec 2020 09:01:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E5CF22838 for ; Fri, 4 Dec 2020 09:01:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729318AbgLDJBH (ORCPT ); Fri, 4 Dec 2020 04:01:07 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:41893 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727875AbgLDJBH (ORCPT ); Fri, 4 Dec 2020 04:01:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1607072487; x=1638608487; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p4/4WU7zlPSDBX1K6cVlPpse+7pKzY0b1sUIIwj/gkY=; b=jUx1NlUR3mxlrFfkg+RqSZDBKXlke2PR0YHFFXFAuzKKvTQZ1bGVU1lj ZtxXyBlnC2xoEnhr8/Ww41qGilbeXltk/ZnAh61hQiTJDkvtnowqCidlD 2h4toUgUnxAnHDYsfXGWnr0GxIF0kw8VW8CGYTMefEIu55EVNqpUd++rF 1SpGrcgiOZR4YU6p3i8GqbGjNj9L6vEztMJXyBjYMX2Me+iPpncrvjsXM 6LV72KhoMS5k3m9wXxaWlqC0uvrFuucUokYltNzQ8LD9lzfGvfWH9kM65 pThrEDgP62hua8qApI4H4EJFRSVK8pKdrpVF7MKnYpiO2AHNJ9IsTsMI4 A==; IronPort-SDR: SpyeJRCHPu0N6Vicm9x5Hn3oPuJP8jr84L1SLYqmE9g2UFKVdoa5pcML3+3wtSvob8RVd9R0gu Hk1JcRCJ8gznCt4WRnY49DSkTl+TbvLOitweDW/Wiyg4WXnm620xBXpC8r77FqfXGW5CE4OJbd nxZLY9ZiN2NuGHsMZsPDOwkwl+KKs0v/jwdZZzc1ja2pHJgHDYJm9pL66rPR8PZqj5cuOPh3xC J65cIly+3x4OozpsT4H9TreiWUhiGbZ0shFxhDZBdUW5s2ULYdS53TpQ/iTvJ6iNRTx0+9Pgte huA= X-IronPort-AV: E=Sophos;i="5.78,392,1599494400"; d="scan'208";a="258129848" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 04 Dec 2020 17:18:05 +0800 IronPort-SDR: 70NPrZ+Ni2D2WOEDQlhol0GpFcKiu3rGW/2MDYnrTjB5GCBh2EGPS2xtg7yQ9KEc2JgJ3v7mSy Vk01dlvnPZg0Af8vb/5ww+kBYQWBEf0wo= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 00:44:13 -0800 IronPort-SDR: hpevyYajMil9qiaJwKklLYkGvROq1vk+1zqb4ra4g+6Ym17E03bjTNWlPFHpWcaGkKYMa08w2Q zNnQvxF7VH/g== WDCIronportException: Internal Received: from cnf010505.ad.shared (HELO jedi-01.hgst.com) ([10.86.61.200]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Dec 2020 00:58:40 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alistair Francis , Anup Patel , Bin Meng , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring , Ivan.Griffin@microchip.com, Cyril.Jean@microchip.com, Daire McNamara , Conor.Dooley@microchip.com Subject: [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board Date: Fri, 4 Dec 2020 00:58:33 -0800 Message-Id: <20201204085835.2406541-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204085835.2406541-1-atish.patra@wdc.com> References: <20201204085835.2406541-1-atish.patra@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial DTS for Microchip ICICLE board having only essential devices (clocks, sdhci, ethernet, serial, etc). The device tree is based on the U-Boot patch. https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ Signed-off-by: Atish Patra --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/microchip/Makefile | 2 + .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ .../boot/dts/microchip/microchip-mpfs.dtsi | 331 ++++++++++++++++++ 4 files changed, 406 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/Makefile create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ca1f8cbd78c0..3ea94ea0a18a 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += sifive subdir-y += kendryte +subdir-y += microchip obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile new file mode 100644 index 000000000000..622b12771fd3 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts new file mode 100644 index 000000000000..5b51dad13c72 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020 Microchip Technology Inc */ + +/dts-v1/; + +#include "microchip-mpfs.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PolarFire-SoC Icicle Kit"; + compatible = "microchip,mpfs-icicle-kit", "microchip,polarfire-soc"; + + chosen { + stdout-path = &serial0; + }; + + cpus { + timebase-frequency = ; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + clocks = <&clkcfg 26>; + }; + + soc { + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&sdcard { + status = "okay"; +}; + +&emac0 { + phy-mode = "sgmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@8 { + reg = <8>; + ti,fifo-depth = <0x01>; + }; +}; + +&emac1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@9 { + reg = <9>; + ti,fifo-depth = <0x01>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi new file mode 100644 index 000000000000..7a076aa4c78d --- /dev/null +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020 Microchip Technology Inc */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PolarFire-SoC"; + compatible = "microchip,polarfire-soc"; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@1 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@2 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@3 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@4 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + + clint@2000000 { + compatible = "riscv,clint0"; + reg = <0x0 0x2000000 0x0 0xC000>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; + }; + + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <186>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11 + &cpu1_intc 11 &cpu1_intc 9 + &cpu2_intc 11 &cpu2_intc 9 + &cpu3_intc 11 &cpu3_intc 9 + &cpu4_intc 11 &cpu4_intc 9>; + }; + + dma@3000000 { + compatible = "sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = <23 24 25 26 27 28 29 30>; + #dma-cells = <1>; + }; + + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + clock-output-names = "msspllclk"; + }; + + clkcfg: clkcfg@20002000 { + compatible = "microchip,pfsoc-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>; + reg-names = "mss_sysreg"; + clocks = <&refclk>; + #clock-cells = <1>; + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ + "mac0", "mac1", "mmc", "timer", /* 4-7 */ + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ + "i2c1", "can0", "can1", "usb", /* 16-19 */ + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ + }; + + serial0: serial@20000000 { + compatible = "ns16550a"; + reg = <0x0 0x20000000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <90>; + current-speed = <115200>; + clocks = <&clkcfg 8>; + status = "disabled"; + }; + + serial1: serial@20100000 { + compatible = "ns16550a"; + reg = <0x0 0x20100000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <91>; + current-speed = <115200>; + clocks = <&clkcfg 9>; + status = "disabled"; + }; + + serial2: serial@20102000 { + compatible = "ns16550a"; + reg = <0x0 0x20102000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <92>; + current-speed = <115200>; + clocks = <&clkcfg 10>; + status = "disabled"; + }; + + serial3: serial@20104000 { + compatible = "ns16550a"; + reg = <0x0 0x20104000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <93>; + current-speed = <115200>; + clocks = <&clkcfg 11>; + status = "disabled"; + }; + + emmc: mmc@20008000 { + compatible = "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88 89>; + pinctrl-names = "default"; + clocks = <&clkcfg 6>; + bus-width = <4>; + cap-mmc-highspeed; + mmc-ddr-3_3v; + max-frequency = <200000000>; + non-removable; + no-sd; + no-sdio; + voltage-ranges = <3300 3300>; + status = "disabled"; + }; + + sdcard: sdhc@20008000 { + compatible = "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88>; + pinctrl-names = "default"; + clocks = <&clkcfg 6>; + bus-width = <4>; + disable-wp; + no-1-8-v; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <200000000>; + status = "disabled"; + }; + + emac0: ethernet@20110000 { + compatible = "cdns,macb"; + reg = <0x0 0x20110000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <64 65 66 67>; + local-mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg 5>, <&clkcfg 2>; + clock-names = "pclk", "hclk"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac1: ethernet@20112000 { + compatible = "cdns,macb"; + reg = <0x0 0x20112000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <70 71 72 73>; + mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg 5>, <&clkcfg 2>; + status = "disabled"; + clock-names = "pclk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + }; +}; From patchwork Fri Dec 4 08:58:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 338511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5E3DC4167B for ; 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04 Dec 2020 00:58:41 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Bin Meng , Albert Ou , Alistair Francis , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring , Ivan.Griffin@microchip.com, Cyril.Jean@microchip.com, Daire McNamara , Conor.Dooley@microchip.com Subject: [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC Date: Fri, 4 Dec 2020 00:58:34 -0800 Message-Id: <20201204085835.2406541-5-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204085835.2406541-1-atish.patra@wdc.com> References: <20201204085835.2406541-1-atish.patra@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable Microchip PolarFire ICICLE soc config in defconfig. It allows the default upstream kernel to boot on PolarFire ICICLE board. Signed-off-by: Atish Patra Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- arch/riscv/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d222d353d86d..2660fa05451e 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -16,6 +16,7 @@ CONFIG_EXPERT=y CONFIG_BPF_SYSCALL=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y +CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_SMP=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y @@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_STORAGE=y CONFIG_USB_UAS=y +CONFIG_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC=y CONFIG_MMC_SPI=y CONFIG_RTC_CLASS=y From patchwork Fri Dec 4 08:58:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 337897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49884C4361A for ; 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04 Dec 2020 00:58:41 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Conor Dooley , Albert Ou , Alistair Francis , Anup Patel , Atish Patra , Bin Meng , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring , Ivan.Griffin@microchip.com, Cyril.Jean@microchip.com, Daire McNamara , Conor.Dooley@microchip.com Subject: [PATCH v3 5/5] MAINTAINERS: add microchip polarfire soc support Date: Fri, 4 Dec 2020 00:58:35 -0800 Message-Id: <20201204085835.2406541-6-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204085835.2406541-1-atish.patra@wdc.com> References: <20201204085835.2406541-1-atish.patra@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC directory Signed-off-by: Conor Dooley Reviewed-by: Bin Meng --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2daa6ee673f7..cccb7d6c58aa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14989,6 +14989,14 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT +M: Lewis Hanly +M: Cyril Jean +L: linux-riscv@lists.infradead.org +S: Supported +F: drivers/soc/microchip/ +F: include/soc/microchip/mpfs.h + RNBD BLOCK DRIVERS M: Danil Kipnis M: Jack Wang