From patchwork Thu Dec 3 14:05:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 337472 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91FBDC433C1 for ; Thu, 3 Dec 2020 14:01:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A6A920709 for ; Thu, 3 Dec 2020 14:01:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388029AbgLCOBh (ORCPT ); Thu, 3 Dec 2020 09:01:37 -0500 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:31004 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726111AbgLCOBh (ORCPT ); Thu, 3 Dec 2020 09:01:37 -0500 Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B3E0l2n016424; Thu, 3 Dec 2020 09:00:55 -0500 Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com with ESMTP id 355vj5ntg3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 03 Dec 2020 09:00:55 -0500 Received: from SCSQMBX10.ad.analog.com (SCSQMBX10.ad.analog.com [10.77.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 0B3E0p0n059075 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL); Thu, 3 Dec 2020 09:00:52 -0500 Received: from SCSQMBX11.ad.analog.com (10.77.17.10) by SCSQMBX10.ad.analog.com (10.77.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 3 Dec 2020 06:00:51 -0800 Received: from zeus.spd.analog.com (10.66.68.11) by SCSQMBX11.ad.analog.com (10.77.17.10) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Thu, 3 Dec 2020 06:00:50 -0800 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 0B3E0mE8012864; Thu, 3 Dec 2020 09:00:49 -0500 From: Alexandru Ardelean To: , , CC: , , , , Alexandru Ardelean Subject: [PATCH v4 1/3] spi: uapi: unify SPI modes into a single spi.h header Date: Thu, 3 Dec 2020 16:05:29 +0200 Message-ID: <20201203140531.74470-1-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-03_07:2020-12-03,2020-12-03 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 clxscore=1015 malwarescore=0 suspectscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 phishscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2012030085 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This change moves all the SPI mode bits into a separate 'spi.h' header in uAPI. This is meant to re-use these definitions inside the kernel as well as export them to userspace (via uAPI). The SPI mode definitions have usually been duplicated between between 'include/linux/spi/spi.h' and 'include/uapi/linux/spi/spidev.h', so whenever adding a new entry, this would need to be put in both headers. They've been moved from 'include/linux/spi/spi.h', since that seems a bit more complete; the bits have descriptions and there is the SPI_MODE_X_MASK. This change also does a conversion of these bitfields to _BITUL() macro. Signed-off-by: Alexandru Ardelean --- Changelog v3 -> v4: * https://lore.kernel.org/linux-spi/20201127130834.136348-1-alexandru.ardelean@analog.com/ * uapi -> uAPI in comment * removed extra license text in 'uapi/linux/spi/spi.h' * using _BITUL() macro include/linux/spi/spi.h | 23 ++--------------------- include/uapi/linux/spi/spi.h | 31 +++++++++++++++++++++++++++++++ include/uapi/linux/spi/spidev.h | 30 +----------------------------- 3 files changed, 34 insertions(+), 50 deletions(-) create mode 100644 include/uapi/linux/spi/spi.h diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index aa09fdc8042d..a08c3f37e202 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -15,6 +15,8 @@ #include #include +#include + struct dma_chan; struct property_entry; struct spi_controller; @@ -165,27 +167,6 @@ struct spi_device { u8 bits_per_word; bool rt; u32 mode; -#define SPI_CPHA 0x01 /* clock phase */ -#define SPI_CPOL 0x02 /* clock polarity */ -#define SPI_MODE_0 (0|0) /* (original MicroWire) */ -#define SPI_MODE_1 (0|SPI_CPHA) -#define SPI_MODE_2 (SPI_CPOL|0) -#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) -#define SPI_MODE_X_MASK (SPI_CPOL|SPI_CPHA) -#define SPI_CS_HIGH 0x04 /* chipselect active high? */ -#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ -#define SPI_3WIRE 0x10 /* SI/SO signals shared */ -#define SPI_LOOP 0x20 /* loopback mode */ -#define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */ -#define SPI_READY 0x80 /* slave pulls low to pause */ -#define SPI_TX_DUAL 0x100 /* transmit with 2 wires */ -#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ -#define SPI_RX_DUAL 0x400 /* receive with 2 wires */ -#define SPI_RX_QUAD 0x800 /* receive with 4 wires */ -#define SPI_CS_WORD 0x1000 /* toggle cs after each word */ -#define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */ -#define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */ -#define SPI_3WIRE_HIZ 0x8000 /* high impedance turnaround */ int irq; void *controller_state; void *controller_data; diff --git a/include/uapi/linux/spi/spi.h b/include/uapi/linux/spi/spi.h new file mode 100644 index 000000000000..703b586f35df --- /dev/null +++ b/include/uapi/linux/spi/spi.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ +#ifndef _UAPI_SPI_H +#define _UAPI_SPI_H + +#include + +#define SPI_CPHA _BITUL(0) /* clock phase */ +#define SPI_CPOL _BITUL(1) /* clock polarity */ + +#define SPI_MODE_0 (0|0) /* (original MicroWire) */ +#define SPI_MODE_1 (0|SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL|0) +#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define SPI_MODE_X_MASK (SPI_CPOL|SPI_CPHA) + +#define SPI_CS_HIGH _BITUL(2) /* chipselect active high? */ +#define SPI_LSB_FIRST _BITUL(3) /* per-word bits-on-wire */ +#define SPI_3WIRE _BITUL(4) /* SI/SO signals shared */ +#define SPI_LOOP _BITUL(5) /* loopback mode */ +#define SPI_NO_CS _BITUL(6) /* 1 dev/bus, no chipselect */ +#define SPI_READY _BITUL(7) /* slave pulls low to pause */ +#define SPI_TX_DUAL _BITUL(8) /* transmit with 2 wires */ +#define SPI_TX_QUAD _BITUL(9) /* transmit with 4 wires */ +#define SPI_RX_DUAL _BITUL(10) /* receive with 2 wires */ +#define SPI_RX_QUAD _BITUL(11) /* receive with 4 wires */ +#define SPI_CS_WORD _BITUL(12) /* toggle cs after each word */ +#define SPI_TX_OCTAL _BITUL(13) /* transmit with 8 wires */ +#define SPI_RX_OCTAL _BITUL(14) /* receive with 8 wires */ +#define SPI_3WIRE_HIZ _BITUL(15) /* high impedance turnaround */ + +#endif /* _UAPI_SPI_H */ diff --git a/include/uapi/linux/spi/spidev.h b/include/uapi/linux/spi/spidev.h index d56427c0b3e0..0c3da08f2aff 100644 --- a/include/uapi/linux/spi/spidev.h +++ b/include/uapi/linux/spi/spidev.h @@ -25,35 +25,7 @@ #include #include - -/* User space versions of kernel symbols for SPI clocking modes, - * matching - */ - -#define SPI_CPHA 0x01 -#define SPI_CPOL 0x02 - -#define SPI_MODE_0 (0|0) -#define SPI_MODE_1 (0|SPI_CPHA) -#define SPI_MODE_2 (SPI_CPOL|0) -#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) - -#define SPI_CS_HIGH 0x04 -#define SPI_LSB_FIRST 0x08 -#define SPI_3WIRE 0x10 -#define SPI_LOOP 0x20 -#define SPI_NO_CS 0x40 -#define SPI_READY 0x80 -#define SPI_TX_DUAL 0x100 -#define SPI_TX_QUAD 0x200 -#define SPI_RX_DUAL 0x400 -#define SPI_RX_QUAD 0x800 -#define SPI_CS_WORD 0x1000 -#define SPI_TX_OCTAL 0x2000 -#define SPI_RX_OCTAL 0x4000 -#define SPI_3WIRE_HIZ 0x8000 - -/*---------------------------------------------------------------------------*/ +#include /* IOCTL commands */ From patchwork Thu Dec 3 14:05:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 338203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEB2AC433C1 for ; Thu, 3 Dec 2020 14:02:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 66442206F6 for ; Thu, 3 Dec 2020 14:02:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388521AbgLCOBi (ORCPT ); Thu, 3 Dec 2020 09:01:38 -0500 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:31302 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729909AbgLCOBh (ORCPT ); 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Thu, 3 Dec 2020 09:00:52 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Thu, 3 Dec 2020 09:00:52 -0500 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 0B3E0mE9012864; Thu, 3 Dec 2020 09:00:50 -0500 From: Alexandru Ardelean To: , , CC: , , , , Alexandru Ardelean Subject: [PATCH v4 2/3] spi: Add SPI_NO_TX/RX support Date: Thu, 3 Dec 2020 16:05:30 +0200 Message-ID: <20201203140531.74470-2-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201203140531.74470-1-alexandru.ardelean@analog.com> References: <20201203140531.74470-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-03_07:2020-12-03,2020-12-03 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 clxscore=1015 malwarescore=0 suspectscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 phishscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2012030085 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Dragos Bogdan Transmit/receive only is a valid SPI mode. For example, the MOSI/TX line might be missing from an ADC while for a DAC the MISO/RX line may be optional. This patch adds these two new modes: SPI_NO_TX and SPI_NO_RX. This way, the drivers will be able to identify if any of these two lines is missing and to adjust the transfers accordingly. Signed-off-by: Dragos Bogdan Signed-off-by: Alexandru Ardelean --- Changelog v3 -> v4: * https://lore.kernel.org/linux-spi/20201127130834.136348-2-alexandru.ardelean@analog.com/ * moved SPI_NO_TX + SPI_NO_RX to internal spi.h header * added SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK + BUILD_BUG_ON() check drivers/spi/spi.c | 28 +++++++++++++++++++++++----- include/linux/spi/spi.h | 4 ++++ include/uapi/linux/spi/spi.h | 6 ++++++ 3 files changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index cd3c395b4e90..8668626c4a46 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1941,6 +1941,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, /* Device DUAL/QUAD mode */ if (!of_property_read_u32(nc, "spi-tx-bus-width", &value)) { switch (value) { + case 0: + spi->mode |= SPI_NO_TX; + break; case 1: break; case 2: @@ -1962,6 +1965,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, if (!of_property_read_u32(nc, "spi-rx-bus-width", &value)) { switch (value) { + case 0: + spi->mode |= SPI_NO_RX; + break; case 1: break; case 2: @@ -3329,12 +3335,17 @@ int spi_setup(struct spi_device *spi) unsigned bad_bits, ugly_bits; int status; - /* check mode to prevent that DUAL and QUAD set at the same time + /* + * check mode to prevent that any two of DUAL, QUAD and NO_MOSI/MISO + * are set at the same time */ - if (((spi->mode & SPI_TX_DUAL) && (spi->mode & SPI_TX_QUAD)) || - ((spi->mode & SPI_RX_DUAL) && (spi->mode & SPI_RX_QUAD))) { + if ((hweight_long(spi->mode & + (SPI_TX_DUAL | SPI_TX_QUAD | SPI_NO_TX)) > 1) || + (hweight_long(spi->mode & + (SPI_RX_DUAL | SPI_RX_QUAD | SPI_NO_RX)) > 1)) { dev_err(&spi->dev, - "setup: can not select dual and quad at the same time\n"); + "setup: can not select any two of dual, quad and no-rx/tx " + "at the same time\n"); return -EINVAL; } /* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden @@ -3348,7 +3359,8 @@ int spi_setup(struct spi_device *spi) * SPI_CS_WORD has a fallback software implementation, * so it is ignored here. */ - bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD); + bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD | + SPI_NO_TX | SPI_NO_RX); /* nothing prevents from working with active-high CS in case if it * is driven by GPIO. */ @@ -3609,6 +3621,8 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) * 2. check tx/rx_nbits match the mode in spi_device */ if (xfer->tx_buf) { + if (spi->mode & SPI_NO_TX) + return -EINVAL; if (xfer->tx_nbits != SPI_NBITS_SINGLE && xfer->tx_nbits != SPI_NBITS_DUAL && xfer->tx_nbits != SPI_NBITS_QUAD) @@ -3622,6 +3636,8 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) } /* check transfer rx_nbits */ if (xfer->rx_buf) { + if (spi->mode & SPI_NO_RX) + return -EINVAL; if (xfer->rx_nbits != SPI_NBITS_SINGLE && xfer->rx_nbits != SPI_NBITS_DUAL && xfer->rx_nbits != SPI_NBITS_QUAD) @@ -4190,6 +4206,8 @@ static int __init spi_init(void) { int status; + BUILD_BUG_ON(SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK); + buf = kmalloc(SPI_BUFSIZ, GFP_KERNEL); if (!buf) { status = -ENOMEM; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index a08c3f37e202..6f1905f729c4 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -6,6 +6,7 @@ #ifndef __LINUX_SPI_H #define __LINUX_SPI_H +#include #include #include #include @@ -166,6 +167,9 @@ struct spi_device { u8 chip_select; u8 bits_per_word; bool rt; +#define SPI_NO_TX BIT(31) /* no transmit wire */ +#define SPI_NO_RX BIT(30) /* no receive wire */ +#define SPI_MODE_KERNEL_MASK (SPI_NO_TX | SPI_NO_RX) u32 mode; int irq; void *controller_state; diff --git a/include/uapi/linux/spi/spi.h b/include/uapi/linux/spi/spi.h index 703b586f35df..e5c58748422e 100644 --- a/include/uapi/linux/spi/spi.h +++ b/include/uapi/linux/spi/spi.h @@ -28,4 +28,10 @@ #define SPI_RX_OCTAL _BITUL(14) /* receive with 8 wires */ #define SPI_3WIRE_HIZ _BITUL(15) /* high impedance turnaround */ +#define SPI_MODE_USER_MASK \ + (SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | \ + SPI_3WIRE | SPI_LOOP | SPI_NO_CS | SPI_READY | \ + SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD | \ + SPI_CS_WORD | SPI_TX_OCTAL | SPI_RX_OCTAL | SPI_3WIRE_HIZ) + #endif /* _UAPI_SPI_H */ From patchwork Thu Dec 3 14:05:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 337471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D08EC001B2 for ; Thu, 3 Dec 2020 14:02:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 07B59206D8 for ; Thu, 3 Dec 2020 14:02:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389081AbgLCOBj (ORCPT ); Thu, 3 Dec 2020 09:01:39 -0500 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:35346 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389070AbgLCOBj (ORCPT ); Thu, 3 Dec 2020 09:01:39 -0500 Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B3E0cSx022951; Thu, 3 Dec 2020 09:00:56 -0500 Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com with ESMTP id 355vjenuxy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 03 Dec 2020 09:00:55 -0500 Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 0B3E0s6a025117 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL); Thu, 3 Dec 2020 09:00:54 -0500 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Thu, 3 Dec 2020 09:00:53 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Thu, 3 Dec 2020 09:00:53 -0500 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 0B3E0mEA012864; Thu, 3 Dec 2020 09:00:52 -0500 From: Alexandru Ardelean To: , , CC: , , , , Alexandru Ardelean Subject: [PATCH v4 3/3] spi: dt-bindings: document zero value for spi-{rx, tx}-bus-width properties Date: Thu, 3 Dec 2020 16:05:31 +0200 Message-ID: <20201203140531.74470-3-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201203140531.74470-1-alexandru.ardelean@analog.com> References: <20201203140531.74470-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-03_07:2020-12-03,2020-12-03 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 phishscore=0 clxscore=1015 mlxscore=0 mlxlogscore=739 malwarescore=0 adultscore=0 impostorscore=0 priorityscore=1501 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2012030085 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Following a change to the SPI framework, providing a value of zero for 'spi-rx-bus-width' and 'spi-tx-bus-width' is now possible and will essentially mean that no RX or TX is allowed. Signed-off-by: Alexandru Ardelean Reviewed-by: Rob Herring --- Changelog v3 -> v4: * https://lore.kernel.org/linux-spi/20201127130834.136348-3-alexandru.ardelean@analog.com/ * fix typos Documentation/devicetree/bindings/spi/spi-controller.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml index 1b56d5e40f1f..cf663e4a4afe 100644 --- a/Documentation/devicetree/bindings/spi/spi-controller.yaml +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml @@ -125,8 +125,9 @@ patternProperties: spi-rx-bus-width: description: Bus width to the SPI bus used for read transfers. + If 0 is provided, then no RX will be possible on this device. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2, 4, 8] + enum: [0, 1, 2, 4, 8] default: 1 spi-rx-delay-us: @@ -136,8 +137,9 @@ patternProperties: spi-tx-bus-width: description: Bus width to the SPI bus used for write transfers. + If 0 is provided, then no TX will be possible on this device. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2, 4, 8] + enum: [0, 1, 2, 4, 8] default: 1 spi-tx-delay-us: