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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 302 ++++++++++++++++++++++++++- 1 file changed, 295 insertions(+), 7 deletions(-) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 65acd1f381eb..f4cae2b82e2a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4,10 +4,12 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -1254,14 +1256,8 @@ tcsr_mutex: hwlock@1f40000 { }; gpu: gpu@3d00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ compatible = "qcom,adreno-650.2", - "qcom,adreno", - "amd,imageon"; + "qcom,adreno"; #stream-id-cells = <16>; reg = <0 0x03d00000 0 0x40000>; @@ -1803,6 +1799,298 @@ usb_2_dwc3: dwc3@a800000 { }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>, + <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "notused", "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <460000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: mdp-opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8250-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk", + "dptx2_phy_pll_link_clk", + "dptx2_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8250-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; From patchwork Thu Dec 3 14:21:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 336936 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp332715ilb; Thu, 3 Dec 2020 06:23:21 -0800 (PST) X-Google-Smtp-Source: ABdhPJyoJLa+GUlNw/BQvM6LbslhpcNAtr4Z2D5jP5LBeyhxBUCJ7roQ1BWkVBz3kYwGRFv2AQqQ X-Received: by 2002:a17:906:2582:: with SMTP id m2mr2668532ejb.271.1607005401345; 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Thu, 03 Dec 2020 06:21:12 -0800 (PST) Received: from eriador.lumag.spb.ru ([188.162.64.117]) by smtp.gmail.com with ESMTPSA id k185sm575716lfd.294.2020.12.03.06.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Dec 2020 06:21:11 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/7] arm64: dts: qrb5165-rb5: add mdss/mdp/dsi nodes Date: Thu, 3 Dec 2020 17:21:00 +0300 Message-Id: <20201203142105.841666-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> References: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index ce22d4fa383e..ce9d98e2d856 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -406,6 +406,30 @@ vreg_s8c_1p3: smps8 { }; }; +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l9a_1p2>; + +#if 0 + qcom,dual-dsi-mode; + qcom,master-dsi; +#endif + + ports { + port@1 { + endpoint { + //remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l5a_0p88>; +}; + /* LS-I2C0 */ &i2c4 { status = "okay"; @@ -420,6 +444,14 @@ &i2c15 { status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &pm8150_gpios { gpio-reserved-ranges = <1 1>, <3 2>, <7 1>; gpio-line-names = From patchwork Thu Dec 3 14:21:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 337004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F9C5C00130 for ; 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Thu, 03 Dec 2020 06:21:13 -0800 (PST) Received: from eriador.lumag.spb.ru ([188.162.64.117]) by smtp.gmail.com with ESMTPSA id k185sm575716lfd.294.2020.12.03.06.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Dec 2020 06:21:13 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/7] arm64: dts: qcom: qrb5165-rb5: add gpu/zap-shader node Date: Thu, 3 Dec 2020 17:21:01 +0300 Message-Id: <20201203142105.841666-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> References: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add firmware configuration for Adreno zap shader on qrb5165-rb5. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index ce9d98e2d856..22c1953f4e63 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -430,6 +430,13 @@ &dsi0_phy { vdds-supply = <&vreg_l5a_0p88>; }; +&gpu { + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sm8250/a650_zap.mbn"; + }; +}; + /* LS-I2C0 */ &i2c4 { status = "okay"; From patchwork Thu Dec 3 14:21:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 336940 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp332825ilb; Thu, 3 Dec 2020 06:23:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJyfbcRxZABTego4yCggh781MvZKfxHCc7eQs/PnYN3dbb0oG2MtGx0aRkZUt+w/o65lH95D X-Received: by 2002:a17:907:2506:: with SMTP id y6mr2738974ejl.53.1607005408164; Thu, 03 Dec 2020 06:23:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607005408; cv=none; d=google.com; s=arc-20160816; b=aCSxUwSkaWu2Oj8KoyBl8w4cCZxe21AyM8LpxkD9QjztLxUpPziXAaHdNgM1KW5bpV Rk1cpLDphUi5EBIU4SHAzZt9dO7RKmCiXfO0BkSrX0EJrrolZV8pEhQx7WlJPoTI0qhK dD2kpnOQwj8rBRtbLLMGBk0QDdRAEAKnccGhwnGwoa7RASVeas0fqOO/LdhV/aX0sNYg THLP1ALHNH17EDXQG0d6vlhgq+Mm2KQuq53jiqcWv5CW7kOYwtIH0A8ltSGc0tlWmQ24 1krvTHcmV1kh9uMdiRgEJbkw2qHcsuoWmRto9sqTwTyx0oB0J7mEGvf2VNwcpV6xGkps CUnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Uko9b3BV55av2QkaenkzJqpvAkDFgYkHQm5vc8/OXNA=; b=gHDntuEbegEvjt/DhXGbLZBgb7ue8nYzMdHfA7uElc1JgCDVVvoYKqNzy8Du+YtINy iRcglOGKJydRBZyeJu93Taoqt2Hmadj1po61VIkTVUS/Qu4OikovSjh+Zlt6Nkvzhlgg kF9+qYpxv4t2Cs+cp1lR+SnietnwdbiKjxoJTFoNJ6UhYA7SCHJEwpuC+bED/bsMZaJz VXjZDptxuATpCbBIi9h2m7o/2vS6Oqapelko/kyHv22EO7QWt+MYBhVSp4BXIsgf2M3p 16fyu3f4iSmKoZGkroBVJnW62E6FD6VfNetIE09LPt6mvjEWT5GmX0cuLi5M7ynzj09+ yQLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qJrt4aoa; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 22c1953f4e63..94d95dff48c4 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -87,7 +87,7 @@ vbat_som: vbat-som-regulator { vdc_3v3: vdc-3v3-regulator { compatible = "regulator-fixed"; regulator-name = "VDC_3V3"; - vin-supply = <&dc12v>; + vin-supply = <&vreg_l11c_3p3>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; From patchwork Thu Dec 3 14:21:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 337003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A18EFC433C1 for ; Thu, 3 Dec 2020 14:22:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4F8CD20793 for ; Thu, 3 Dec 2020 14:22:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730711AbgLCOWk (ORCPT ); Thu, 3 Dec 2020 09:22:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727822AbgLCOWk (ORCPT ); Thu, 3 Dec 2020 09:22:40 -0500 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56C9FC08E861 for ; Thu, 3 Dec 2020 06:21:19 -0800 (PST) Received: by mail-lf1-x144.google.com with SMTP id u18so2931499lfd.9 for ; Thu, 03 Dec 2020 06:21:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KcRu/X3xJaaLM+ngoS1QVEM2mbS7z453C1cW9cVO+24=; b=jxALDj5S1uasxL4Wa21OAPLGRojIzp1++DhlKZo1tjxUfDKARgB6LaDMzfKm8RJqxJ 1g76RY9AvwXMzJLD9peur1eJGxi086RRDTlcmJ7IwFx5h0jBcUwLeHSMBILa9IFiH3Hr 8dQUb+hXxoBn6uld5cdwmWrLHh7/spKKHAv1MrrJV9UyfwSRiHI/O7AHpx6170PFUsV6 7xXc/eg8i/uKVT78tLqq1Nz3LVsLc+Pw3MiMXPu4eTbbaxRPXYTfgpra4JtpHPtn1a+E MrVoOUnPocPJN1IH0g4MhloFIvD+a4R25zmuLJl2/hCPDWw/pEJY8T2fk+sVMz4MoZ90 hbVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KcRu/X3xJaaLM+ngoS1QVEM2mbS7z453C1cW9cVO+24=; b=eEoRDQH0y1zqUtMguDaXuO30J+MEgz6ijBj6t1hJh63S+1qK53G2gp4PMBzO1TBbpG TGs52eCuWYWHRvDuuem7bvR7CVZ4UARu/3Prm3Ah9GJok2J63f3jz/BwI2aE1O30PZwz M3qywj0ma6Srg8hMtCKYFwWlzrUxzB5uFr1scTEwYal+wyCFq+MSjoEloUyp36IjLsFo cOF6KhORe2I53ZP/t3nLRZV+IlRQFnjxvSMEsR7UsjHKtLkbhoT7LrE8N68WXYBO8eBn jDXkBgmq8YTl2enUJBQs69rIiyBSPQVLopTJSwW2URYxTcipz9SVeiZnYeczlCkeA8Uv PhVg== X-Gm-Message-State: AOAM5339D25JVuVvcCCPUDpgKQvsvozQqPnOFrDgnmK4FN0nv9JEaoOX Np28WPOPhUN5aAryRkJK5+cDlg== X-Google-Smtp-Source: ABdhPJxMyzirZqfdZOxK5o3S2qn5MzfcDs3ikYYLY17umY4BSyxw+yNj3Y2g9j2XdgIabgoc6JdS+A== X-Received: by 2002:a19:c815:: with SMTP id y21mr1372057lff.589.1607005277861; Thu, 03 Dec 2020 06:21:17 -0800 (PST) Received: from eriador.lumag.spb.ru ([188.162.64.117]) by smtp.gmail.com with ESMTPSA id k185sm575716lfd.294.2020.12.03.06.21.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Dec 2020 06:21:17 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 6/7] arm64: dts: qcom: qrb5165-rb5: add lt9611 HDMI bridge Date: Thu, 3 Dec 2020 17:21:04 +0300 Message-Id: <20201203142105.841666-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> References: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree node for the lontium lt9611ux DSI-HDMI bridge. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 97 +++++++++++++++++++++++- 1 file changed, 96 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 94d95dff48c4..1ade62d98f98 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -40,6 +40,17 @@ dc12v: dc12v-regulator { regulator-always-on; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -66,6 +77,26 @@ bt { }; + lt9611_1v2: lt9611-vdd12-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + vin-supply = <&vdc_3v3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + lt9611_3v3: lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vdc_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vbat: vbat-regulator { compatible = "regulator-fixed"; regulator-name = "VBAT"; @@ -418,7 +449,7 @@ &dsi0 { ports { port@1 { endpoint { - //remote-endpoint = <<9611_a>; + remote-endpoint = <<9611_a>; data-lanes = <0 1 2 3>; }; }; @@ -444,6 +475,55 @@ &i2c4 { &i2c5 { status = "okay"; + clock-frequency = <400000>; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + #sound-dai-cells = <1>; + + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&pm8150l_gpios 5 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + +#if 0 + port@1 { + reg = <1>; + + lt9611_b: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; +#endif + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + + }; + }; }; /* LS-I2C1 */ @@ -504,6 +584,15 @@ &pm8150l_gpios { "PM_GPIO-B", "NC", "PM3003A_MODE"; + + lt9611_rst_pin: lt9611-rst-pin { + pins = "gpio5"; + function = "normal"; + + output-high; + input-disable; + power-source = <0>; + }; }; &pm8150_rtc { @@ -735,6 +824,12 @@ &tlmm { "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; + lt9611_irq_pin: lt9611-irq { + pins = "gpio63"; + function = "gpio"; + bias-disable; + }; + sdc2_default_state: sdc2-default { clk { pins = "sdc2_clk"; From patchwork Thu Dec 3 14:21:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 337002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1514CC433C1 for ; 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Thu, 03 Dec 2020 06:21:19 -0800 (PST) Received: from eriador.lumag.spb.ru ([188.162.64.117]) by smtp.gmail.com with ESMTPSA id k185sm575716lfd.294.2020.12.03.06.21.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Dec 2020 06:21:18 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 7/7] arm64: dts: qcom: sm8250: power up dispcc on sm8250 by MMCX regulator Date: Thu, 3 Dec 2020 17:21:05 +0300 Message-Id: <20201203142105.841666-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> References: <20201203142105.841666-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add regulator controlling MMCX power domain to be used by display clock controller on SM8250. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f4cae2b82e2a..0c7986bf60d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -216,6 +216,13 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + mmcx_reg: mmcx-reg { + compatible = "regulator-fixed-domain"; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + regulator-name = "MMCX"; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -2058,6 +2065,7 @@ opp-358000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x20000>; + mmcx-supply = <&mmcx_reg>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, <&dsi0_phy 1>,