From patchwork Wed Jan 24 05:47:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 125627 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp201949ljf; Tue, 23 Jan 2018 21:48:12 -0800 (PST) X-Google-Smtp-Source: AH8x2247ssYtvrVjR9SBRD0VSAsbDBpsuqNBMAvb/DGx41gYzs0Qp3D9NllIu1fXYM+gjSv8tykV X-Received: by 10.98.58.194 with SMTP id v63mr12039844pfj.36.1516772892409; Tue, 23 Jan 2018 21:48:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516772892; cv=none; d=google.com; s=arc-20160816; b=z2KslPRzxqR+aG3Vj43cXsnqeUiDzzUCYy8Kx7hnX8wL1sU3Q7KqxrbzKj0VH7U3jD vlHZZUvqM1RmLB9o04ZHOk2Z29qkqwB1qaB8ZpV4eK9FAPR7P8vJD7FYzc5HY3FUlRGQ lL2jMy7cKLWfaCMrgaF2+lsPY5BD6jqPyIi4hygrSCNssL8VSDKgF/o7aoi16WMA8j+b tFnjRRqtomX86utuaI6vLTK7SdFWMTkDH3azYFou+Ge4KZJV31e1YNhC4/l8As7jqJoE bKmt6k8g/O9d/sA8BY8SD2l/CB46yN8NoJj7JWsOum/+M4g2AD7I3dnNpEgeCUqWQxT3 wk2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=rFIYNPs+VraWddhdwLhfEUHZ9ZrjVAspfjGkB/TOv/0=; b=ubr5hxpn8qOnFz3RoDqck8BOt5sRFpnt2WvKHbQ6nXobtujMMpRjTB5f0FRbdFwPgd 8GGFN6cEMIvgcCQdWV9jqf6evVWidU6uzcihsudHx7m5OIODUMD5ziEgvxl/1mfPj4/f sHsB2AwCsjISjySiqE+9h4FEnYHgDH4ZBXwcafzD6iG88GzRqkDJdI3h+AQOx37L8I7S NF3PSjqjUeri28rjv4IzdZbdRh3zNS+P1jqVGqRgnCfPZXgIIqI92tXjVod17YstCgy6 JsbEE4BzS0InijIAcWG1Kf4r0c4UmLeh8P2lw9gpsc0Z/GKnBdu1B+QIGw8OXBXI2CHg Ho5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Op0r4TQ9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m17-v6si5630216pls.212.2018.01.23.21.48.12; Tue, 23 Jan 2018 21:48:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Op0r4TQ9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752524AbeAXFsK (ORCPT + 28 others); Wed, 24 Jan 2018 00:48:10 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:45518 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752371AbeAXFsG (ORCPT ); Wed, 24 Jan 2018 00:48:06 -0500 Received: by mail-pf0-f195.google.com with SMTP id a88so2253690pfe.12 for ; Tue, 23 Jan 2018 21:48:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rFIYNPs+VraWddhdwLhfEUHZ9ZrjVAspfjGkB/TOv/0=; b=Op0r4TQ9MSewlU/UoV2Nl3cJBIZJ+DUIayOQimyRQ1B1JruBv4i+jdDG7KYZDzuJ/j VUxM08OtM0j1PKKwWaNF6dLSXfJ6PdfXjjUPySnRcaE+Qnkk2l4Q2yN5e89dYUhOjq2D e96bq0jxeR5vSQ6VHRUjeskY0ixrXCDCyLBQ4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rFIYNPs+VraWddhdwLhfEUHZ9ZrjVAspfjGkB/TOv/0=; b=l1Lq2tthjuD/1qKDsog3mXoppyPwx+eTcvHCDq4qlgmQ1YSj961KDhRkknBKaM8JKn YPkJPNJhUMAmzA8vl7uz+gXNObHqLwyTBG0832wankEEn8xyjzvi7xrhwEMl3FiwGA7C iKbwkVRNBZgXbyxhJxSSMGbSRGFnVppzywTRENZ+pNJSA6dbRCKhUgmQwH0S5mIAEacC OACSLQN2Z2y9WkTeIty2FEl708Xqt6kFqmVTFoiLfzd/WnRz5F9wgiBMGNObnOvDsy+P j7azY8kzWiJepBSnWyHoh7hFEBT9bvRhnf9tpAkqmsGn2QKu0sYHoHRO3vWLDCrvsOyw UeOQ== X-Gm-Message-State: AKwxytdN1lpOfQSYbZnkz+mBrFScEtDBe8AVNZEsXWH6U6OIAI4GskHC j1wf8FSrzRH4IncdY9IvKzX4ZQ== X-Received: by 10.99.96.199 with SMTP id u190mr9942910pgb.290.1516772886312; Tue, 23 Jan 2018 21:48:06 -0800 (PST) Received: from localhost.localdomain ([45.56.152.94]) by smtp.gmail.com with ESMTPSA id f188sm8524519pfc.22.2018.01.23.21.48.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Jan 2018 21:48:05 -0800 (PST) From: Shawn Guo To: Kishon Vijay Abraham I Cc: Rob Herring , Jianguo Sun , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, project-aspen-dev@linaro.org, Shawn Guo Subject: [PATCH v5 RESEND 1/3] dt-bindings: hisilicon: add doc for Hi3798CV200 peripheral controller Date: Wed, 24 Jan 2018 13:47:35 +0800 Message-Id: <1516772857-3580-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516772857-3580-1-git-send-email-shawn.guo@linaro.org> References: <1516772857-3580-1-git-send-email-shawn.guo@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It adds bindings doc for Hi3798CV200 peripheral controller. Signed-off-by: Shawn Guo --- .../bindings/arm/hisilicon/hisilicon.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 7111fbc82a4e..199cd36fe1ba 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -75,6 +75,29 @@ Example: }; ----------------------------------------------------------------------- +Hisilicon Hi3798CV200 Peripheral Controller + +The Hi3798CV200 Peripheral Controller controls peripherals, queries +their status, and configures some functions of peripherals. + +Required properties: +- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" + and "simple-mfd". +- reg: Register address and size of Peripheral Controller. +- #address-cells: Should be 1. +- #size-cells: Should be 1. + +Examples: + + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + +----------------------------------------------------------------------- Hisilicon Hi6220 system controller Required properties: From patchwork Wed Jan 24 05:47:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 125628 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp201967ljf; Tue, 23 Jan 2018 21:48:15 -0800 (PST) X-Google-Smtp-Source: AH8x227v+9l9nTdTqjwSX4ScrfBaDJ3QM9lTh6tOFSdo/gchvEDa9LBU1vEfU63c8Yn1jGg8xfL1 X-Received: by 2002:a17:902:481:: with SMTP id e1-v6mr5167056ple.228.1516772894876; Tue, 23 Jan 2018 21:48:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516772894; cv=none; d=google.com; s=arc-20160816; b=uZto8vov1rz05S6zlhHYWpfa96XmPOTThGJv9CSAoKkKWaTFrZksxOSdClZLk3PdwD kYzkft5Lp08zI/m4X4k5l+MoQXAgZYglcKj0E+lfQQEZDgJ+bKG/+Sd+5dF0OiBOoJPF QEZb9+N1aelOfOV8HWO+e9TpsgqS7MtNFSuGGq1Lnxk7X9FzlVuwU+hudsxfNsez+ceo 3cmSxkseZTZabcCvXfS58hnJxUe/oqBWEwztGOt8b0/d77kWoc0sydYsW/QwKjxYnLJ5 /SA/YVjE+Kv9ZlQYiCLi7gQBV7vlEXLQIGw/dYftHXWEdJ7hRJllFdifEFnrfCb1Cnci EEXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=3rbNW3xDNb/+Hjv6vdIBgT3G0o9MU79RUdkKmHfcaVc=; b=Dbh9N2YH+rRdqcJamIzheUG82Qki6coG5c1bWlA2SgZ0uvbQIeTVLhXv+MQthjNAAS h15iHHfBbY8qruLJ9QKu90tLwTalS7l65TYVqEk3RvCwvjVzaFoSIcSXU+JlvRZEZEuC AGYggGBiCKyZZOcgaDAjQjEtguP+0v8rjIYJbHIRMLSI5QYTeKwhFtuExcxOTJ+2Tn6l rDCV8tzz6qIZC1k1cGAdAf8mX0O/0XqC/wrKWTYkeVJPvC7uJ+aqlI5obFivOzNC5gbA 5ETQwNHWr5/mvefXm6P4Zjw1y94shIKWYCJ4SgDOgPZsrcd1OzGY0xI92ZA6kOqWdO1W 1HAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I4E6uvum; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Jianguo Sun Signed-off-by: Shawn Guo Acked-by: Rob Herring --- .../bindings/phy/phy-hi3798cv200-combphy.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt new file mode 100644 index 000000000000..17b0c761370a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt @@ -0,0 +1,59 @@ +HiSilicon STB PCIE/SATA/USB3 PHY + +Required properties: +- compatible: Should be "hisilicon,hi3798cv200-combphy" +- reg: Should be the address space for COMBPHY configuration and state + registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and + PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC. +- #phy-cells: Should be 1. The cell number is used to select the phy mode + as defined in . +- clocks: The phandle to clock provider and clock specifier pair. +- resets: The phandle to reset controller and reset specifier pair. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties. + +Optional properties: +- hisilicon,fixed-mode: If the phy device doesn't support mode select + but a fixed mode setting, the property should be present to specify + the particular mode. +- hisilicon,mode-select-bits: If the phy device support mode select, + this property should be present to specify the register bits in + peripheral controller, as a 3 integers tuple: + . + +Notes: +- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only + one of them should be present. +- The device node should be a child of peripheral controller that contains + COMBPHY configuration/state and PERI_CTRL register used to select PHY mode. + Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller + bindings. + +Examples: + +perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + combphy0: phy@850 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x850 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY0_CLK>; + resets = <&crg 0x188 4>; + hisilicon,fixed-mode = ; + }; + + combphy1: phy@858 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x858 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY1_CLK>; + resets = <&crg 0x188 12>; + hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; + }; +}; From patchwork Wed Jan 24 05:47:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 125629 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp202007ljf; Tue, 23 Jan 2018 21:48:19 -0800 (PST) X-Google-Smtp-Source: AH8x226QPuJZ0BP4gahYFlA2jkhbjRA5Th11LrnAxQezLWrMLg3w9rCtzlTbgXqZ2FxZIVusP4Cr X-Received: by 10.98.196.75 with SMTP id y72mr12033839pff.73.1516772899671; Tue, 23 Jan 2018 21:48:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516772899; cv=none; d=google.com; s=arc-20160816; b=oh2In8eXJKWWLPYr4OxLhhfQz07b2Mwy7M9Ozmr71AwKbHyl7+YBfUsgPdP4r7iAUs z8MdSYi+pCPKkimMpgmjecnjimj8P3Gzu5+3q8aNac6jGb0AXXag1C1eli9oFVNHSzfP Wwv5T2SjR/PehJzrB/eMSuen2ckM6Qw7k06mhEA9B2rUBNq3IK0cEhYy2pZNM3LacJZC 7RSD6Ds2YKZmxyLGbrQxCQqnKO+9jZdVURqhxy26P/fGx0vZf8N8VbZZOEN1brmcei/r GlHfQMTTasUD6bn16ctIND0sVpdubPdHlfzIxLZkWmLOzPLrkOYIGEc4ixCtB0QGwOd6 1WUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=FzHwP+iazyZ3l1k9p8jgNh/Yn/xzBh42pTYjCcqA2og=; b=lt0bsTSn3pB4470wISQ6kZualpXyeCJGwGiDui3B3m+aw8rYal2xPzdYdNj37S2uzo Tx+H9QEMmEggNuZ+ovHucYYICzqnGrF9epLgftH4T5qiJyK4+uOOAwhYNGqTqL0hxNJp l+zjsZYv41MX/sTdy85oJoq7Fy0wzSnK4UqAtdW3o6wWo52NJ583zEXYWsItScBlansv H9znJ+m5lzvNSj5fTsMqXO6196O/V0Mn+1VsiuEaNl+ifCvhU803r+pMfB1OSR5bq/E/ A7EHsXcJrL4z9BzPfUM9m1UkVdZwlc4pP6gVTlHmn2XV4vamLJY+iAJJXd5hqs6hEkXO gQqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ayt46keY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This phy can be used as pcie-phy, sata-phy or usb-phy. Changes for v5: - Add bindings doc for Hi3798CV200 peripheral controller, and refer to the bindings of this parent node in combphy bindings doc. Changes for v4: - Instead of relying on device id, add a new property hisilicon,fixed-mode for combphy device that doesn't support mode select but a fixed phy mode. - Move combphy mode select register bits definition to device tree, as it may vary from one device to another. Changes for v3: - Make combphy device be child of peripheral controller and use 'reg' property for mapping combphy configuration registers. - Kill "hisilicon,peripheral-syscon" property, since parent node is just the syscon controller now. - Check combphy id to handle the quirk that combphy0 can not configure mode but always works in USB3 mode. - Unify phy .init and .exit hooks for different combphy instances and work modes, as the only quirk we need to handle is that combphy0 can only work in USB3 mode. - Better naming for clock and reset, 'ref' to 'ref_clk', 'por' to 'por_rst'. Changes for v2: - Move DT bindings into a separate patch. - Drop the spurious newline from drivers/phy/Makefile. - Use the phy type defines in dt-bindings/phy/phy.h. - Use PTR_ERR_OR_ZERO() for checking return from devm_of_phy_provider_register(). - Add USB3 phy support. Signed-off-by: Jianguo Sun Signed-off-by: Shawn Guo --- drivers/phy/hisilicon/Kconfig | 9 + drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-histb-combphy.c | 289 ++++++++++++++++++++++++++++++ 3 files changed, 299 insertions(+) create mode 100644 drivers/phy/hisilicon/phy-histb-combphy.c -- 1.9.1 diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig index 6164c4cd0f65..d9afe2b12827 100644 --- a/drivers/phy/hisilicon/Kconfig +++ b/drivers/phy/hisilicon/Kconfig @@ -11,6 +11,15 @@ config PHY_HI6220_USB To compile this driver as a module, choose M here. +config PHY_HISTB_COMBPHY + tristate "HiSilicon STB SoCs COMBPHY support" + depends on (ARCH_HISI && ARM64) || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the HISILICON STB SoCs COMBPHY. + If unsure, say N. + config PHY_HIX5HD2_SATA tristate "HIX5HD2 SATA PHY Driver" depends on ARCH_HIX5HD2 && OF && HAS_IOMEM diff --git a/drivers/phy/hisilicon/Makefile b/drivers/phy/hisilicon/Makefile index 541b348187a8..5e8e2dfa8c37 100644 --- a/drivers/phy/hisilicon/Makefile +++ b/drivers/phy/hisilicon/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o +obj-$(CONFIG_PHY_HISTB_COMBPHY) += phy-histb-combphy.o obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o diff --git a/drivers/phy/hisilicon/phy-histb-combphy.c b/drivers/phy/hisilicon/phy-histb-combphy.c new file mode 100644 index 000000000000..5777b3120017 --- /dev/null +++ b/drivers/phy/hisilicon/phy-histb-combphy.c @@ -0,0 +1,289 @@ +/* + * COMBPHY driver for HiSilicon STB SoCs + * + * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com + * + * Authors: Jianguo Sun + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define COMBPHY_MODE_PCIE 0 +#define COMBPHY_MODE_USB3 1 +#define COMBPHY_MODE_SATA 2 + +#define COMBPHY_CFG_REG 0x0 +#define COMBPHY_BYPASS_CODEC BIT(31) +#define COMBPHY_TEST_WRITE BIT(24) +#define COMBPHY_TEST_DATA_SHIFT 20 +#define COMBPHY_TEST_DATA_MASK GENMASK(23, 20) +#define COMBPHY_TEST_ADDR_SHIFT 12 +#define COMBPHY_TEST_ADDR_MASK GENMASK(16, 12) +#define COMBPHY_CLKREF_OUT_OEN BIT(0) + +struct histb_combphy_mode { + int fixed; + int select; + u32 reg; + u32 shift; + u32 mask; +}; + +struct histb_combphy_priv { + void __iomem *mmio; + struct regmap *syscon; + struct reset_control *por_rst; + struct clk *ref_clk; + struct phy *phy; + struct histb_combphy_mode mode; +}; + +static void nano_register_write(struct histb_combphy_priv *priv, + u32 addr, u32 data) +{ + void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; + u32 val; + + /* Set up address and data for the write */ + val = readl(reg); + val &= ~COMBPHY_TEST_ADDR_MASK; + val |= addr << COMBPHY_TEST_ADDR_SHIFT; + val &= ~COMBPHY_TEST_DATA_MASK; + val |= data << COMBPHY_TEST_DATA_SHIFT; + writel(val, reg); + + /* Flip strobe control to trigger the write */ + val &= ~COMBPHY_TEST_WRITE; + writel(val, reg); + val |= COMBPHY_TEST_WRITE; + writel(val, reg); +} + +static int is_mode_fixed(struct histb_combphy_mode *mode) +{ + return (mode->fixed != PHY_NONE) ? true : false; +} + +static int histb_combphy_set_mode(struct histb_combphy_priv *priv) +{ + struct histb_combphy_mode *mode = &priv->mode; + struct regmap *syscon = priv->syscon; + u32 hw_sel; + + if (is_mode_fixed(mode)) + return 0; + + switch (mode->select) { + case PHY_TYPE_SATA: + hw_sel = COMBPHY_MODE_SATA; + break; + case PHY_TYPE_PCIE: + hw_sel = COMBPHY_MODE_PCIE; + break; + case PHY_TYPE_USB3: + hw_sel = COMBPHY_MODE_USB3; + break; + default: + return -EINVAL; + } + + return regmap_update_bits(syscon, mode->reg, mode->mask, + hw_sel << mode->shift); +} + +static int histb_combphy_init(struct phy *phy) +{ + struct histb_combphy_priv *priv = phy_get_drvdata(phy); + u32 val; + int ret; + + ret = histb_combphy_set_mode(priv); + if (ret) + return ret; + + /* Clear bypass bit to enable encoding/decoding */ + val = readl(priv->mmio + COMBPHY_CFG_REG); + val &= ~COMBPHY_BYPASS_CODEC; + writel(val, priv->mmio + COMBPHY_CFG_REG); + + ret = clk_prepare_enable(priv->ref_clk); + if (ret) + return ret; + + reset_control_deassert(priv->por_rst); + + /* Enable EP clock */ + val = readl(priv->mmio + COMBPHY_CFG_REG); + val |= COMBPHY_CLKREF_OUT_OEN; + writel(val, priv->mmio + COMBPHY_CFG_REG); + + /* Need to wait for EP clock stable */ + mdelay(5); + + /* Configure nano phy registers as suggested by vendor */ + nano_register_write(priv, 0x1, 0x8); + nano_register_write(priv, 0xc, 0x9); + nano_register_write(priv, 0x1a, 0x4); + + return 0; +} + +static int histb_combphy_exit(struct phy *phy) +{ + struct histb_combphy_priv *priv = phy_get_drvdata(phy); + u32 val; + + /* Disable EP clock */ + val = readl(priv->mmio + COMBPHY_CFG_REG); + val &= ~COMBPHY_CLKREF_OUT_OEN; + writel(val, priv->mmio + COMBPHY_CFG_REG); + + reset_control_assert(priv->por_rst); + clk_disable_unprepare(priv->ref_clk); + + return 0; +} + +static const struct phy_ops histb_combphy_ops = { + .init = histb_combphy_init, + .exit = histb_combphy_exit, + .owner = THIS_MODULE, +}; + +static struct phy *histb_combphy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct histb_combphy_priv *priv = dev_get_drvdata(dev); + struct histb_combphy_mode *mode = &priv->mode; + + if (args->args_count < 1) { + dev_err(dev, "invalid number of arguments\n"); + return ERR_PTR(-EINVAL); + } + + mode->select = args->args[0]; + + if (mode->select < PHY_TYPE_SATA || mode->select > PHY_TYPE_USB3) { + dev_err(dev, "invalid phy mode select argument\n"); + return ERR_PTR(-EINVAL); + } + + if (is_mode_fixed(mode) && mode->select != mode->fixed) { + dev_err(dev, "mode select %d mismatch fixed phy mode %d\n", + mode->select, mode->fixed); + return ERR_PTR(-EINVAL); + } + + return priv->phy; +} + +static int histb_combphy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct histb_combphy_priv *priv; + struct device_node *np = dev->of_node; + struct histb_combphy_mode *mode; + struct resource *res; + u32 vals[3]; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->mmio = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->mmio)) { + ret = PTR_ERR(priv->mmio); + return ret; + } + + priv->syscon = syscon_node_to_regmap(np->parent); + if (IS_ERR(priv->syscon)) { + dev_err(dev, "failed to find peri_ctrl syscon regmap\n"); + return PTR_ERR(priv->syscon); + } + + mode = &priv->mode; + mode->fixed = PHY_NONE; + + ret = of_property_read_u32(np, "hisilicon,fixed-mode", &mode->fixed); + if (ret == 0) + dev_dbg(dev, "found fixed phy mode %d\n", mode->fixed); + + ret = of_property_read_u32_array(np, "hisilicon,mode-select-bits", + vals, ARRAY_SIZE(vals)); + if (ret == 0) { + if (is_mode_fixed(mode)) { + dev_err(dev, "found select bits for fixed mode phy\n"); + return -EINVAL; + } + + mode->reg = vals[0]; + mode->shift = vals[1]; + mode->mask = vals[2]; + dev_dbg(dev, "found mode select bits\n"); + } else { + if (!is_mode_fixed(mode)) { + dev_err(dev, "no valid select bits found for non-fixed phy\n"); + return -ENODEV; + } + } + + priv->ref_clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->ref_clk)) { + dev_err(dev, "failed to find ref clock\n"); + return PTR_ERR(priv->ref_clk); + } + + priv->por_rst = devm_reset_control_get(dev, NULL); + if (IS_ERR(priv->por_rst)) { + dev_err(dev, "failed to get poweron reset\n"); + return PTR_ERR(priv->por_rst); + } + + priv->phy = devm_phy_create(dev, NULL, &histb_combphy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + + phy_provider = devm_of_phy_provider_register(dev, histb_combphy_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id histb_combphy_of_match[] = { + { .compatible = "hisilicon,hi3798cv200-combphy" }, + { }, +}; +MODULE_DEVICE_TABLE(of, histb_combphy_of_match); + +static struct platform_driver histb_combphy_driver = { + .probe = histb_combphy_probe, + .driver = { + .name = "combphy", + .of_match_table = histb_combphy_of_match, + }, +}; +module_platform_driver(histb_combphy_driver); + +MODULE_DESCRIPTION("HiSilicon STB COMBPHY driver"); +MODULE_LICENSE("GPL v2");