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[23.128.96.18]) by mx.google.com with ESMTP id k14si4968466edq.576.2020.11.27.01.56.28; Fri, 27 Nov 2020 01:56:29 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ySNIHPP7; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726014AbgK0Jzy (ORCPT + 6 others); Fri, 27 Nov 2020 04:55:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725865AbgK0Jzx (ORCPT ); Fri, 27 Nov 2020 04:55:53 -0500 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFE62C0613D4 for ; Fri, 27 Nov 2020 01:55:52 -0800 (PST) Received: by mail-lf1-x144.google.com with SMTP id d20so6189250lfe.11 for ; Fri, 27 Nov 2020 01:55:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/6wim9Ub2SwtjYj9niGLBRd7nsut6yLKYnhevmwWC/o=; b=ySNIHPP74f/+yuy94JV8xhuKq9bqxAVMhzHckdl4/Iw858Wiuh41JTTxQPs5gy86mS KfvCZc3fG/0svGhPIkt4oVC/1bYkXb7typTOOfQvp1RtjuHBELnQYv4hYIxkhMUxsH6B 8cGFozrqjVkph1BNfLuZHMoVEnckhVrwNN0mmAJ21vAUKXK/+R9E0VnlO4VO1DvjgLYg 3wLEUap9dlUgdcCRRVlrs9LEasopTMKou8IGvKuF0p8e67dknkV8oWd1haLCgb9weBmD JOJY4aM0D7hH6tnJUN/icSAXg4k8WczyTVLu/v/enB/iLCgujW8HucxSKFxZgKOnZehK GBcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/6wim9Ub2SwtjYj9niGLBRd7nsut6yLKYnhevmwWC/o=; b=Uzyf0IbEI3ufXzZb/X1TkYg49jYb4SmnQbNKe7f3GCIl1tqRMes8s4Z8oX5lRuj2sk cTV5ELmDKqagv9/wpXPDU+aALYIG7ANBES7t+u5/2CQb6uSrbW1urzx1kwV/9orCG5q/ /GkA/Xlye+HdUZKPibTgabpc1HD9hflTLREhCWbqQPchTEw/4uHwqPyVOnlE+C3rpAvz b+zBaNCZWNIIw+X4lkeu+/9wNF5f8RsE/OhwqeX1MkyIw/7twG6vwwsddpgIGVFl56W9 CMsELx/T1HtELIrBex5pp2gMLGdD7D0HxJyFrCF1ngr61TyLAxPdZLOVoBlVz3a29CHf C75A== X-Gm-Message-State: AOAM5334ei1wjKa/QeLsupRi6503e62X9HmTScLumCkHjH40Gdds4MdE bpKCygG2vWFHborRhCAOfGEOtg== X-Received: by 2002:ac2:548b:: with SMTP id t11mr2789640lfk.323.1606470951278; Fri, 27 Nov 2020 01:55:51 -0800 (PST) Received: from eriador.lumag.spb.ru ([188.162.64.79]) by smtp.gmail.com with ESMTPSA id x25sm628477lfn.99.2020.11.27.01.55.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Nov 2020 01:55:50 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/7] arm64: dts: qcom: sm8250.dtsi: add display system nodes Date: Fri, 27 Nov 2020 12:55:42 +0300 Message-Id: <20201127095548.128217-1-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree nodes for mdss, mdp, dsi0/1. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 302 ++++++++++++++++++++++++++- 1 file changed, 295 insertions(+), 7 deletions(-) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 65acd1f381eb..f4cae2b82e2a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4,10 +4,12 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -1254,14 +1256,8 @@ tcsr_mutex: hwlock@1f40000 { }; gpu: gpu@3d00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ compatible = "qcom,adreno-650.2", - "qcom,adreno", - "amd,imageon"; + "qcom,adreno"; #stream-id-cells = <16>; reg = <0 0x03d00000 0 0x40000>; @@ -1803,6 +1799,298 @@ usb_2_dwc3: dwc3@a800000 { }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>, + <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "notused", "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <460000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: mdp-opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8250-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk", + "dptx2_phy_pll_link_clk", + "dptx2_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8250-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; From patchwork Fri Nov 27 09:55:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 333745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3A4CC64E7C for ; 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Fri, 27 Nov 2020 01:55:52 -0800 (PST) Received: from eriador.lumag.spb.ru ([188.162.64.79]) by smtp.gmail.com with ESMTPSA id x25sm628477lfn.99.2020.11.27.01.55.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Nov 2020 01:55:52 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/7] arm64: dts: qrb5165-rb5: add mdss/mdp/dsi nodes Date: Fri, 27 Nov 2020 12:55:43 +0300 Message-Id: <20201127095548.128217-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201127095548.128217-1-dmitry.baryshkov@linaro.org> References: <20201127095548.128217-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index d9f52703ba2a..9c5135585ec9 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -399,6 +399,30 @@ vreg_s8c_1p3: smps8 { }; }; +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l9a_1p2>; + +#if 0 + qcom,dual-dsi-mode; + qcom,master-dsi; +#endif + + ports { + port@1 { + endpoint { + //remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l5a_0p88>; +}; + /* LS-I2C0 */ &i2c4 { status = "okay"; @@ -413,6 +437,14 @@ &i2c15 { status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &pm8150_gpios { gpio-reserved-ranges = <1 1>, <3 2>, <7 1>; gpio-line-names = From patchwork Fri Nov 27 09:55:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 333611 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp863958ejs; Fri, 27 Nov 2020 01:56:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJxPwsUyScjjDn0KVQK+SfreiofDa4VyANaYYOJf8aNsUuWLMugL0MnABg545DCoskSKnQAH X-Received: by 2002:a17:906:2a09:: with SMTP id j9mr6888665eje.355.1606470991435; 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 9c5135585ec9..d1f6cadca35a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -423,6 +423,13 @@ &dsi0_phy { vdds-supply = <&vreg_l5a_0p88>; }; +&gpu { + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/a650_zap.mdt"; + }; +}; + /* LS-I2C0 */ &i2c4 { status = "okay"; From patchwork Fri Nov 27 09:55:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 333612 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp863966ejs; Fri, 27 Nov 2020 01:56:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJwvzxl6ndLgNVHmZKS6Y8kaSnOjuzczQhvP2E8Lmul4JjTq+NKJ7niI0BbaIlQifT9fUYPC X-Received: by 2002:a17:906:af6b:: with SMTP id os11mr6875613ejb.270.1606470992203; Fri, 27 Nov 2020 01:56:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606470992; cv=none; d=google.com; s=arc-20160816; b=v5vjGfGTYLU1nzNIuzOMgvLSvi4OT0To/YZQWYBxnfG7GS3iYDbHpeY6Npw0nzW8ct 4j1hUP4DEoca+sYz8NJk8mjbQ99O7lKKA9aKjA4/5UO1vupbjlJTX0lVjDrR3vp0ZjPW 5UN3PaDbF0ksCKHC6VTjeU9xw1DTUn9N6qoYyc1x8mjKOs5eI1yC30N3WaleMW1gPnlt Sllruxo2CHNHZqDR5DK8Ojej3OQPIoAZa0m+zNfmKvuUeOFasMEeHIHYdI/sLFJdE31d aeXl+mGGXrjRh0tUH9dx3XYJDOYX6rFq0/rbuhXIKnFR1bsykh+wTmNkgBcfX+Ip3O1s z8rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aMtoWeMWHvc6/ZtjQjyHL53GwuZxoULh8/VicAMR0S4=; b=ErwZIl41r2UYfNts2b6DPbbLCf0tqyngX3dDWR1heMW5jvAHQmOvQ53NBuM++iHItu j1bPGOE0H54WuXj/DjpHN8Hn2KQOPZrZy5oGVefGLh4Bl6ekjGQ8Y5YVTuIlWQfWYFPg 7FLkTxGLOgMNApcoR8NKoqSRP0srly5MkJsEWLmkXtY7dtvFnbX+5Ib/TFVSWq8+kpUo Um0WUY3EKe/djBhFslzndMccMmPwwOBQvQwOZaUxDiuI8rt8rVTQ7fzx9tou3tl3Hivv tGBFAGKP265idsU8jxDKPsQC5UyfSRxN/WUn5EyWj7577YmPsvyWd2JW6hRmLxYe3xEC VlIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zBgYUoi+; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index dea00f19711d..b5a474ee008e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -358,6 +358,13 @@ &cdsp { firmware-name = "qcom/sm8250/cdsp.mbn"; }; +&gpu { + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/a650_zap.mdt"; + }; +}; + &i2c1 { status = "okay"; clock-frequency = <1000000>; From patchwork Fri Nov 27 09:55:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 333613 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp863980ejs; Fri, 27 Nov 2020 01:56:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJwRDw1LiFy4Bk5g0rb/K7cHIeWA24mLI8oxWm0kT6cgiIpFuKDObPI9VOhny4RFtZ8LaphK X-Received: by 2002:a17:906:ca0b:: with SMTP id jt11mr6644547ejb.538.1606470992992; Fri, 27 Nov 2020 01:56:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606470992; cv=none; d=google.com; s=arc-20160816; b=WSJ67BtqHw7+oZt+wXxX4YQixXqQqU9omLwNfHWBNErSfrw7dRf89Edu9D4eAamxKV 5nAxYFi2NFXIf8g+iGfPNXMyWcCXtqsVfHz+cuDx7SSIeqtd8EZMBvPfxD+tE5KmVFjs ruu3QVLNKhWb/GXZvr6l5fUqp3wXS8NW82NKuM8t+PsmWSykrDtQm0Nps/fa4F52I6Gw vbkdOVtpkqJwYocos2PPWdMLVjtQLe6mZnrNpWiHjvN834hIBoDpH+4BM43Zh6K5q8Yv AETWcinNkmkQUvMnx9lBdZaNXcihFkXQV98FBpckXE+Pjj6UZDRkG0HdjABoZ834dSlb JuyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CLNYIE3vndBOAusimV+1mCUTRKa8LpNqu793Pf61Gw4=; b=j5YeAXyRnitl+nl03C6zXfZygaetaKMdieqeV6pRvhtFnp5Hi5Bw8wdgsU1tZpHEfn j5FexnPui5Xb2Rm05WJgw+eM+Pgswpk+M/GJu8Cu5YDus3W/DfVL2/wI2WjmVsyv1JaT yJnSc0CxzZmxe8tcQ9Th44HJp2L3919S2BwDOBDLHsbb8k9qkGOB7+yyp2ne2DgN0Kt7 UUqwzvzQ5/xX2ZqL73v0KPTGlRYanwpczZw0IcpD31IdV5h5DdhDytDozVqknIzhMeFZ /y6dyZ+cS6ni7xVaCGg+ibrpJn/zh0ATRTGkCtadmNdVORlMJYV+JHEDmdo1LcUMDc4v OSOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZIhDHaGe; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index d1f6cadca35a..70e11705e9f6 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -80,7 +80,7 @@ vbat_som: vbat-som-regulator { vdc_3v3: vdc-3v3-regulator { compatible = "regulator-fixed"; regulator-name = "VDC_3V3"; - vin-supply = <&dc12v>; + vin-supply = <&vreg_l11c_3p3>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; From patchwork Fri Nov 27 09:55:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 333614 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp863993ejs; Fri, 27 Nov 2020 01:56:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJxUryQ2sIaAAMDqX0RkumJ1MpmfyLNsmNmOLr73e3NHfo6a5lbUpomBto1SBa+2O0yz6Zy/ X-Received: by 2002:a17:906:3ad5:: with SMTP id z21mr6697703ejd.35.1606470993801; Fri, 27 Nov 2020 01:56:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606470993; cv=none; d=google.com; s=arc-20160816; b=ETh4UDmewqM+8STT6zNHHkffuTUuw3jBqVlL6hsvvTMMvtbgHoceplh1LlrbKluUpb ydq/XZJrJiP1Jv4A/GqaviSd9/ozIxMA6+aUUrV0bFa9uyMufGJibT0+kifrGF6igYDz zhdNQHcMIFGaEVu/mdnAxyWcb4qLCSjRX5fpociobMayih+UIAAwlQs4kAwPUS1sn9/9 64Xr5xXTpTTR2zE8ykEJK7k2ZKyZsoPPU5D21vx9vWckr5jkdDTcs62eVKJLJ0A6REwp tYMU/ag4r1114A7SPhwbTWqpmPtRR8s3Qj8KxigtXEXBUrC/lt+mRdRv9YlZE/k8GJed 2WUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1tSZCM1rFRClI+8OSMPYPttqmqC9FZJKpAoW1UjVOOE=; b=ckm7TKW7G3JGOpu3VZxLDBJApeA6RqjRpNLkUN5/XOmQ8JAxBb5Gw7s2NCOnCZgb53 qDTCjieaUlAMONWnYBXe7/VJiQ2jvmo5gAVDh/L7lxWnrLHmWxkTm6dhM0RuBDjiytPz M1ijMardfEcLEbBfCmLEUqAJiNdj5DvPLzc7pHi/2NGYjqOu9Bl75ddlKbgC8qgg4uMh 0SP+b28PJqhyiV6FEtHsYyTkM6fS9ziqQbSau7b8MVKJJSgW655itqbdt0uFSGL8a2KS ecDb1T8wFjSVeYhrsRoA2senyTX/yhebjq3dmVYDSu1j9MlrCNAWSpHJvd6I1RPp8iXl UOLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MfT6/sb8"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 97 +++++++++++++++++++++++- 1 file changed, 96 insertions(+), 1 deletion(-) -- 2.29.2 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 70e11705e9f6..2c3eb3771ded 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -33,6 +33,17 @@ dc12v: dc12v-regulator { regulator-always-on; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -59,6 +70,26 @@ bt { }; + lt9611_1v2: lt9611-vdd12-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + vin-supply = <&vdc_3v3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + lt9611_3v3: lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vdc_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vbat: vbat-regulator { compatible = "regulator-fixed"; regulator-name = "VBAT"; @@ -411,7 +442,7 @@ &dsi0 { ports { port@1 { endpoint { - //remote-endpoint = <<9611_a>; + remote-endpoint = <<9611_a>; data-lanes = <0 1 2 3>; }; }; @@ -437,6 +468,55 @@ &i2c4 { &i2c5 { status = "okay"; + clock-frequency = <400000>; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + #sound-dai-cells = <1>; + + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&pm8150l_gpios 5 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + +#if 0 + port@1 { + reg = <1>; + + lt9611_b: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; +#endif + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + + }; + }; }; /* LS-I2C1 */ @@ -497,6 +577,15 @@ &pm8150l_gpios { "PM_GPIO-B", "NC", "PM3003A_MODE"; + + lt9611_rst_pin: lt9611-rst-pin { + pins = "gpio5"; + function = "normal"; + + output-high; + input-disable; + power-source = <0>; + }; }; &pm8150_rtc { @@ -718,6 +807,12 @@ &tlmm { "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; + lt9611_irq_pin: lt9611-irq { + pins = "gpio63"; + function = "gpio"; + bias-disable; + }; + sdc2_default_state: sdc2-default { clk { pins = "sdc2_clk"; From patchwork Fri Nov 27 09:55:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 334244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F1E4C8300E for ; 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Fri, 27 Nov 2020 01:55:59 -0800 (PST) Received: from eriador.lumag.spb.ru ([188.162.64.79]) by smtp.gmail.com with ESMTPSA id x25sm628477lfn.99.2020.11.27.01.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Nov 2020 01:55:59 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: qcom: sm8250: power up dispcc on sm8250 by MMCX regulator Date: Fri, 27 Nov 2020 12:55:48 +0300 Message-Id: <20201127095548.128217-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201127095548.128217-1-dmitry.baryshkov@linaro.org> References: <20201127095548.128217-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add regulator controlling MMCX power domain to be used by display clock controller on SM8250. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f4cae2b82e2a..0c7986bf60d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -216,6 +216,13 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + mmcx_reg: mmcx-reg { + compatible = "regulator-fixed-domain"; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + regulator-name = "MMCX"; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -2058,6 +2065,7 @@ opp-358000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x20000>; + mmcx-supply = <&mmcx_reg>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, <&dsi0_phy 1>,