From patchwork Mon Jan 22 10:35:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 125383 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1081138ljf; Mon, 22 Jan 2018 02:36:24 -0800 (PST) X-Google-Smtp-Source: AH8x225yyJart1NPk/LPXATVuDBDgmG66vsncnYA0b+IapALpkvuRwR1W9BtSXRFpUgF0LMpkxdY X-Received: by 10.99.96.151 with SMTP id u145mr6929139pgb.102.1516617384432; Mon, 22 Jan 2018 02:36:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516617384; cv=none; d=google.com; s=arc-20160816; b=s2Dl3TswxbL83/0fUJc77KRjQi0RwhCAY6rDsSrIOZLd7KxgMGTZPwfc4xG1zdZuxk kL4VONnFUHMwScbqAWgAD1fvPleMtGcpYa7cMHC7PRj3iB6Oxv/Xad0f3rudHAVFG2LD SxveImFdHqJM4Q+fJQTWpHzVZhOadFGN5b4gdB4Eh6df8CmgcXMM4wE8QK17D8I4r2PD +/TDQ3oh7J/5x0SbJVxzkS/EJWF9Vs9P+NLCkkQSyckhhse66J+tH/v2u4cxTUpMiVC6 pixhi9/pBrctZqF8eTzuHVFnVpszbENb+Srky0yE68hj9CReydMPGXwiGwd5sJrvNKxV o+Uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=gQUdQ+gr8TwzHoRwuT45m3zqHz/4QX+3rAa77ofAboY=; b=GqGkxfCcEhsKS7gb4yuFAGDQgXBBZsP480lhdne56NmUjeqrQskTn2MG6oAN+NgWGN Gebmy2plHESUpeRdD/ZklYKqvi3lIB3ipzs7eJvmUR7aUFHvoFElgS2hr9/MywIBrMUy dmPvQIFK8KL5uQAMwn44DQpQaeoPKpnUE2RvQA2jxIml+T/D9z07mv2wGFwY+G7KH2TY O2gtic9caMaJBUw87juggMIOqKtmzx1PKk0IH8RaaApgWaWk5QrI1H1BY88QY2cPp3LC w44OodJ2+FZbHjz8ph2kVWdFolj/fR0htHlHluabCPeey68nfPzidOXET3sDXo16EP6p GegQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w9-v6si3294687plp.93.2018.01.22.02.36.24; Mon, 22 Jan 2018 02:36:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751393AbeAVKgW (ORCPT + 28 others); Mon, 22 Jan 2018 05:36:22 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:46543 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750919AbeAVKgN (ORCPT ); Mon, 22 Jan 2018 05:36:13 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 022DE20721; Mon, 22 Jan 2018 11:36:12 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 2E5C020722; Mon, 22 Jan 2018 11:35:55 +0100 (CET) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , daniel.vetter@intel.com, jani.nikula@linux.intel.com, seanpaul@chromium.org Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas@vitsch.nl Subject: [PATCH v2 12/19] drm/sun4i: backend: Move the coord function in the shared part Date: Mon, 22 Jan 2018 11:35:41 +0100 Message-Id: <2cd57bcf13652109da7bd5bbe12fa1d29429f02f.1516617243.git-series.maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The function supposed to update a plane's coordinates is called in both branches of our function. Let's move it out the if statement. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_layer.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- git-series 0.9.1 Acked-by: Chen-Yu Tsai diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c index f03da16eb92a..c448cb6b9fa9 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.c +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c @@ -106,14 +106,13 @@ static void sun4i_backend_layer_atomic_update(struct drm_plane *plane, DRM_FORMAT_ARGB8888); sun4i_backend_update_layer_frontend(backend, layer->id, DRM_FORMAT_ARGB8888); - sun4i_backend_update_layer_coord(backend, layer->id, plane); sun4i_frontend_enable(frontend); } else { - sun4i_backend_update_layer_coord(backend, layer->id, plane); sun4i_backend_update_layer_formats(backend, layer->id, plane); sun4i_backend_update_layer_buffer(backend, layer->id, plane); } + sun4i_backend_update_layer_coord(backend, layer->id, plane); sun4i_backend_layer_enable(backend, layer->id, true); } From patchwork Mon Jan 22 10:35:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 125389 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1081304ljf; Mon, 22 Jan 2018 02:36:51 -0800 (PST) X-Google-Smtp-Source: AH8x224zo6maZt+3VoIqjrOzIQZ0SsHLyop9ph2AgxtYt6grf4j6JBE5gvNXig9V1gQMr5J5lL3b X-Received: by 10.98.58.5 with SMTP id h5mr7983985pfa.169.1516617411273; Mon, 22 Jan 2018 02:36:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516617411; cv=none; d=google.com; s=arc-20160816; b=HLEbDVj/E6ET9XVM+4zGJcgjXJTRHuT8pJAeP2mMsaJQBrGgmZrBFE5aEDdIm6D/Rz 0OP62E9kptdGCgrDcNXw2qVazWv4WtnmhfAtn7CSnR1Ou9M9SZBF/txG9YtC+6qAYWgZ gn1CUUvHCd1PwT90wIA5f0b3+zXVHCNJPots90eqxiUQufRQ6FsxMXTDq8E2BMZutv6M cJ/YC3xwN49YRBo/y1CdLMHpM4swaT0VbZUVMkJqg7swq4bjerj9xxnFWiGnn28KAm7U rN26/8QpY6hANo6bXHsZeMyPhvck1iiLq0Po+hL6h0IdbinvsA4Zn4lggNsABPDwBOxQ XVLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=iO1qxDrIAL8Bov42eGg65pozCQIoSne9n7PZqDJqza8=; b=gt3iu0OKIr15IE+oApi2jnKMdfJBbi1u+RT74YLTsENW/XOmfDZpnkUl6d9yDwtEqx hJH7UOLp3hRX80XJr9LCnCDqU5vriMqt0Ju3WOlVoxtfWxSqkblLb8NltLoObvYfwdtF cNUYbDxyHoAkLwQEs7CPQNICl9msqEgIZnUhYvcYX8GuZbQMyByXTr+jVi0SPSDU6AtA VIG9xkAiVOj0Fn6RJjLk/GiUJQhkByFmzivjh+kexplpZR3HWJ+VCzdLRFpq0JS1OJJK oa8w5O7CdAMx3qKpAbfic8EKh16gXgdR8LiU0sD8J/+jZcLE7tEGu8sBEKYcNFvztw4k tc7A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r16si15291899pfe.369.2018.01.22.02.36.51; Mon, 22 Jan 2018 02:36:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751477AbeAVKgt (ORCPT + 28 others); Mon, 22 Jan 2018 05:36:49 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:46570 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751216AbeAVKgV (ORCPT ); Mon, 22 Jan 2018 05:36:21 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 9626A207F3; Mon, 22 Jan 2018 11:36:20 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id F017620724; Mon, 22 Jan 2018 11:35:55 +0100 (CET) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , daniel.vetter@intel.com, jani.nikula@linux.intel.com, seanpaul@chromium.org Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas@vitsch.nl Subject: [PATCH v2 14/19] drm/sun4i: backend: Add support for zpos Date: Mon, 22 Jan 2018 11:35:43 +0100 Message-Id: X-Mailer: git-send-email 2.14.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Our various planes have a configurable zpos, that combined with the pipes allow to configure the composition. Since the interaction between the pipes, zpos and alphas framebuffers are not trivials, let's just enable the zpos as an immutable property for now, and use that zpos in our atomic_update part. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_backend.c | 15 +++++++++++++++ drivers/gpu/drm/sun4i/sun4i_backend.h | 2 ++ drivers/gpu/drm/sun4i/sun4i_framebuffer.c | 4 ++++ drivers/gpu/drm/sun4i/sun4i_layer.c | 3 +++ 4 files changed, 24 insertions(+) -- git-series 0.9.1 Reviewed-by: Chen-Yu Tsai diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index a18c86a15748..c4986054909b 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -272,6 +272,21 @@ int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend, return 0; } +int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer, + struct drm_plane *plane) +{ + struct drm_plane_state *state = plane->state; + unsigned int priority = state->normalized_zpos; + + DRM_DEBUG_DRIVER("Setting layer %d priority to %d\n", layer, priority); + + regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), + SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK, + SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority)); + + return 0; +} + static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state) { u16 src_h = state->src_h >> 16; diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.h b/drivers/gpu/drm/sun4i/sun4i_backend.h index 1ca8b7db6807..04a4f11b87a8 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.h +++ b/drivers/gpu/drm/sun4i/sun4i_backend.h @@ -182,5 +182,7 @@ int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend, int layer, struct drm_plane *plane); int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend, int layer, uint32_t in_fmt); +int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, + int layer, struct drm_plane *plane); #endif /* _SUN4I_BACKEND_H_ */ diff --git a/drivers/gpu/drm/sun4i/sun4i_framebuffer.c b/drivers/gpu/drm/sun4i/sun4i_framebuffer.c index e68004844abe..5b3986437a50 100644 --- a/drivers/gpu/drm/sun4i/sun4i_framebuffer.c +++ b/drivers/gpu/drm/sun4i/sun4i_framebuffer.c @@ -35,6 +35,10 @@ static int sun4i_de_atomic_check(struct drm_device *dev, if (ret) return ret; + ret = drm_atomic_normalize_zpos(dev, state); + if (ret) + return ret; + return drm_atomic_helper_check_planes(dev, state); } diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c index 03549646528a..fbf25d59cf88 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.c +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c @@ -115,6 +115,7 @@ static void sun4i_backend_layer_atomic_update(struct drm_plane *plane, } sun4i_backend_update_layer_coord(backend, layer->id, plane); + sun4i_backend_update_layer_zpos(backend, layer->id, plane); sun4i_backend_layer_enable(backend, layer->id, true); } @@ -237,6 +238,8 @@ struct drm_plane **sun4i_layers_init(struct drm_device *drm, return ERR_CAST(layer); }; + drm_plane_create_zpos_immutable_property(&layer->plane, i); + DRM_DEBUG_DRIVER("Assigning %s plane to pipe %d\n", i ? "overlay" : "primary", plane->pipe); regmap_update_bits(engine->regs, SUN4I_BACKEND_ATTCTL_REG0(i), From patchwork Mon Jan 22 10:35:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 125395 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1081474ljf; Mon, 22 Jan 2018 02:37:15 -0800 (PST) X-Google-Smtp-Source: AH8x226Z0CM72zDMqg9XLQPrfnESQDhM+1yABfVF/3eyBfhAyivgNMIYNs8JC5IkYcE0bcBVXRHw X-Received: by 2002:a17:902:1a2:: with SMTP id b31-v6mr2816597plb.28.1516617434527; Mon, 22 Jan 2018 02:37:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516617434; cv=none; d=google.com; s=arc-20160816; b=xh8Xx7Ms89jkn4AR6z+hfAzpm1P5EN573IxS7enFeVhUpVJon9VdGXQL7+dGjVGMwR 4SPrVa1MBxRHbRyAg4ZKOkGAEZLyYe1VDweDbrnoLMuPz4uDoKeSeqHEgG0buHWSVs2R NEFo0IjSSO77Pzcxw7D8Hdm8N7liJqNuzG2IuasQZXBr+2yHEU0zXifbp/QRuZguq/lT D0xhL+/9E5lej46cDolbr3vKbVuitEhUl1y9aDejbNCJlm3WxUKJ3kujZhSdtpI2LcGQ gzjyA/3kdb941HyU0NEqBeZH7TLRtQwXlVUSaShjgj4C0RU0l1MUMqu6Y5OyFZ23jmR7 G3ZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=6Z9z+TqB1nLLr0E14i9Kui+gsKbIY+jGagCktR4CKG8=; b=ZYd1pF8lK7Vx5mAy/reOmavZVdf9fA1rTxheol94annjPlvy6pTC90MnfkCqkkKT6c 3aE5Sie85/ZPFl7UEYGDvriZ+AkccL+W/ZYvfEnY1ADzE0pZ72JHrGPw0CvrbvzVNAVR QkGj9EGQ7AeoFNg3M5+GLgL8XJARfQkMYjydf7vdxlZ8/GhCyBJQ74bhrSn4pcCfQ7HL CJJqFQk5fQ4LVA2b2OEr9g9pvHxFtca89A/4LZiy9jEJ5pHNqergDQHKUWP1Xi6JTQ7R r/7l72TvCiq1QYwNPUZLDyWa4eg1vO4SzLUQY9KqQYT68p0nfS6wE1Q0RV3K99PaMnxe SirQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r16si15291899pfe.369.2018.01.22.02.37.14; Mon, 22 Jan 2018 02:37:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751431AbeAVKgq (ORCPT + 28 others); Mon, 22 Jan 2018 05:36:46 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:46581 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751372AbeAVKgV (ORCPT ); Mon, 22 Jan 2018 05:36:21 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 9E8EB20724; Mon, 22 Jan 2018 11:36:20 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 5B16B2072C; Mon, 22 Jan 2018 11:35:56 +0100 (CET) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , daniel.vetter@intel.com, jani.nikula@linux.intel.com, seanpaul@chromium.org Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas@vitsch.nl Subject: [PATCH v2 15/19] drm/sun4i: backend: Check for the number of alpha planes Date: Mon, 22 Jan 2018 11:35:44 +0100 Message-Id: <7371f62a1385f2cbe3ed75dfca2e746338eb2286.1516617243.git-series.maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Due to the way the composition is done in hardware, we can only have a single alpha-enabled plane active at a time, placed in the second (highest priority) pipe. Make sure of that in our atomic_check to not end up in an impossible scenario. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_backend.c | 50 ++++++++++++++++++++++++++++- drivers/gpu/drm/sun4i/sun4i_backend.h | 2 +- drivers/gpu/drm/sun4i/sun4i_layer.c | 23 +------------- 3 files changed, 53 insertions(+), 22 deletions(-) -- git-series 0.9.1 Reviewed-by: Chen-Yu Tsai diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index c4986054909b..eb1749d2c0d5 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -329,6 +329,8 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, struct drm_atomic_state *state = crtc_state->state; struct drm_device *drm = state->dev; struct drm_plane *plane; + unsigned int num_planes = 0; + unsigned int num_alpha_planes = 0; unsigned int num_frontend_planes = 0; DRM_DEBUG_DRIVER("Starting checking our planes\n"); @@ -341,6 +343,7 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, drm_atomic_get_plane_state(state, plane); struct sun4i_layer_state *layer_state = state_to_sun4i_layer_state(plane_state); + struct drm_framebuffer *fb = plane_state->fb; if (sun4i_backend_plane_uses_frontend(plane_state)) { DRM_DEBUG_DRIVER("Using the frontend for plane %d\n", @@ -351,6 +354,50 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, } else { layer_state->uses_frontend = false; } + + DRM_DEBUG_DRIVER("Plane FB format is %s\n", + drm_get_format_name(fb->format->format, + &format_name)); + if (fb->format->has_alpha) + num_alpha_planes++; + + num_planes++; + } + + /* + * The hardware is a bit unusual here. + * + * Even though it supports 4 layers, it does the composition + * in two separate steps. + * + * The first one is assigning a layer to one of its two + * pipes. If more that 1 layer is assigned to the same pipe, + * and if pixels overlaps, the pipe will take the pixel from + * the layer with the highest priority. + * + * The second step is the actual alpha blending, that takes + * the two pipes as input, and uses the eventual alpha + * component to do the transparency between the two. + * + * This two steps scenario makes us unable to guarantee a + * robust alpha blending between the 4 layers in all + * situations, since this means that we need to have one layer + * with alpha at the lowest position of our two pipes. + * + * However, we cannot even do that, since the hardware has a + * bug where the lowest plane of the lowest pipe (pipe 0, + * priority 0), if it has any alpha, will discard the pixel + * entirely and just display the pixels in the background + * color (black by default). + * + * Since means that we effectively have only three valid + * configurations with alpha, all of them with the alpha being + * on pipe1 with the lowest position, which can be 1, 2 or 3 + * depending on the number of planes and their zpos. + */ + if (num_alpha_planes > SUN4I_BACKEND_NUM_ALPHA_LAYERS) { + DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n"); + return -EINVAL; } if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) { @@ -358,6 +405,9 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, return -EINVAL; } + DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video\n", + num_planes, num_alpha_planes, num_frontend_planes); + return 0; } diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.h b/drivers/gpu/drm/sun4i/sun4i_backend.h index 04a4f11b87a8..52e77591186a 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.h +++ b/drivers/gpu/drm/sun4i/sun4i_backend.h @@ -146,6 +146,8 @@ #define SUN4I_BACKEND_HWCCOLORTAB_OFF 0x4c00 #define SUN4I_BACKEND_PIPE_OFF(p) (0x5000 + (0x400 * (p))) +#define SUN4I_BACKEND_NUM_LAYERS 4 +#define SUN4I_BACKEND_NUM_ALPHA_LAYERS 1 #define SUN4I_BACKEND_NUM_FRONTEND_LAYERS 1 struct sun4i_backend { diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c index fbf25d59cf88..900e716443b8 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.c +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c @@ -201,32 +201,11 @@ struct drm_plane **sun4i_layers_init(struct drm_device *drm, struct sun4i_backend *backend = engine_to_sun4i_backend(engine); int i; - planes = devm_kcalloc(drm->dev, ARRAY_SIZE(sun4i_backend_planes) + 1, + planes = devm_kcalloc(drm->dev, SUN4I_BACKEND_NUM_LAYERS, sizeof(*planes), GFP_KERNEL); if (!planes) return ERR_PTR(-ENOMEM); - /* - * The hardware is a bit unusual here. - * - * Even though it supports 4 layers, it does the composition - * in two separate steps. - * - * The first one is assigning a layer to one of its two - * pipes. If more that 1 layer is assigned to the same pipe, - * and if pixels overlaps, the pipe will take the pixel from - * the layer with the highest priority. - * - * The second step is the actual alpha blending, that takes - * the two pipes as input, and uses the eventual alpha - * component to do the transparency between the two. - * - * This two steps scenario makes us unable to guarantee a - * robust alpha blending between the 4 layers in all - * situations. So we just expose two layers, one per pipe. On - * SoCs that support it, sprites could fill the need for more - * layers. - */ for (i = 0; i < ARRAY_SIZE(sun4i_backend_planes); i++) { const struct sun4i_plane_desc *plane = &sun4i_backend_planes[i]; struct sun4i_layer *layer; From patchwork Mon Jan 22 10:35:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 125388 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1081296ljf; Mon, 22 Jan 2018 02:36:49 -0800 (PST) X-Google-Smtp-Source: AH8x225/pzASXadj9lDCsw+eHkt3Q1uohTLGkLiL2xE4XjBJZIOkAnQcjf70GF7ljcHb1JAtfDaO X-Received: by 10.98.163.79 with SMTP id s76mr8177127pfe.67.1516617409675; Mon, 22 Jan 2018 02:36:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516617409; cv=none; d=google.com; s=arc-20160816; b=owNn44zSjGu1EUJ026U419SKPsqEQEib3JSHfs5gcods9NIGqqVQOzqXs8rnK7818m ZoF7F0MFXM0pfSI8dDkTc/aRAb1/UT3sSSxl1gZRYC2pFvf7C1EHeYldr/yUJXceJrUq 4GOQDsydCBMCoVzcDRJzdVxLbgTDo3dTuhdMHgp1SJ5ATTNxW7Z+e/m9Y6fI3Xpuatcv C0MK63cJySPevV4aPL3Ik3hh/YNSJM/iJigSHIyIqJiBVeZpUKcPLPOw1RV51BoCwuyw WllRmy7W+JpOxgZBxmH/zdvV4B+gw0Cde7IPVaoRYijHWkKKipL1EOKvjR4D5cf6l7Fq KWbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=a2UZT6iz/5P0+wHWJNsfgAJqWvWcO/NoZLA9CKljQSs=; b=IXA46j0fQFwuN2cE/Ds9td7VZswJIemwVg/SaVYHKcuhNUNRhFGJ7vvshofKVE/iKn JWwzi6yzbqyX6e04rNfqY9YUNRJ+qKf0ZdGyGVIkt245vuFmOt9agaOwjH8TNiicCs7C +Cq3LvuITRFdOKoTVRmhAZhiB0Lhq8OKWoCND1QuFw4IxGMKLT3NHriZFTSTBnEJU/j2 VkKV01l9OKMqQzeCwojIPuwoMSRJqRgz2JMyPxvPXL/2WxiMZ0uwdbTPs8aOE3WQt1Yc R8J+3WbedTdbnRhgRwswdWUzwL0GBoLvNOn0GbzAioO0K87vED0LDiuggPbjsFRoMGvR FQug== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y15si13700535pgc.366.2018.01.22.02.36.49; Mon, 22 Jan 2018 02:36:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751451AbeAVKgr (ORCPT + 28 others); Mon, 22 Jan 2018 05:36:47 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:46588 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751374AbeAVKgV (ORCPT ); Mon, 22 Jan 2018 05:36:21 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id A10F220737; Mon, 22 Jan 2018 11:36:20 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id BCB7120730; Mon, 22 Jan 2018 11:35:56 +0100 (CET) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , daniel.vetter@intel.com, jani.nikula@linux.intel.com, seanpaul@chromium.org Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas@vitsch.nl Subject: [PATCH v2 16/19] drm/sun4i: backend: Assign the pipes automatically Date: Mon, 22 Jan 2018 11:35:45 +0100 Message-Id: X-Mailer: git-send-email 2.14.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since we now have a way to enforce the zpos, check for the number of alpha planes, the only missing part is to assign our pipe automatically instead of hardcoding it. The algorithm is quite simple, but requires two iterations over the list of planes. In the first one (which is the same one that we've had to check for alpha, the frontend usage, and so on), we order the planes by their zpos. We can then do a second iteration over that array by ascending zpos starting with the pipe 0. When and if we encounter our alpha plane, we put it and all the other subsequent planes in the second pipe. And since we have runtime checks and pipe assignments now, we can just remove the static declaration of the planes we used to have. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_backend.c | 41 +++++++++++++++++++++-- drivers/gpu/drm/sun4i/sun4i_layer.c | 50 ++++------------------------ drivers/gpu/drm/sun4i/sun4i_layer.h | 1 +- 3 files changed, 48 insertions(+), 44 deletions(-) -- git-series 0.9.1 Reviewed-by: Chen-Yu Tsai diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index eb1749d2c0d5..38c4b44f6ff5 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -276,12 +276,16 @@ int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer, struct drm_plane *plane) { struct drm_plane_state *state = plane->state; + struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state); unsigned int priority = state->normalized_zpos; + unsigned int pipe = p_state->pipe; - DRM_DEBUG_DRIVER("Setting layer %d priority to %d\n", layer, priority); - + DRM_DEBUG_DRIVER("Setting layer %d priority to %d and pipe %d\n", + layer, priority, pipe); regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), + SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK | SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK, + SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) | SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority)); return 0; @@ -326,12 +330,15 @@ static void sun4i_backend_atomic_begin(struct sunxi_engine *engine, static int sun4i_backend_atomic_check(struct sunxi_engine *engine, struct drm_crtc_state *crtc_state) { + struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 }; struct drm_atomic_state *state = crtc_state->state; struct drm_device *drm = state->dev; struct drm_plane *plane; unsigned int num_planes = 0; unsigned int num_alpha_planes = 0; unsigned int num_frontend_planes = 0; + unsigned int current_pipe = 0; + unsigned int i; DRM_DEBUG_DRIVER("Starting checking our planes\n"); @@ -344,6 +351,7 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, struct sun4i_layer_state *layer_state = state_to_sun4i_layer_state(plane_state); struct drm_framebuffer *fb = plane_state->fb; + struct drm_format_name_buf format_name; if (sun4i_backend_plane_uses_frontend(plane_state)) { DRM_DEBUG_DRIVER("Using the frontend for plane %d\n", @@ -361,9 +369,19 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, if (fb->format->has_alpha) num_alpha_planes++; + DRM_DEBUG_DRIVER("Plane zpos is %d\n", + plane_state->normalized_zpos); + + /* Sort our planes by Zpos */ + plane_states[plane_state->normalized_zpos] = plane_state; + num_planes++; } + /* All our planes were disabled, bail out */ + if (!num_planes) + return 0; + /* * The hardware is a bit unusual here. * @@ -400,6 +418,25 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, return -EINVAL; } + /* We can't have an alpha plane at the lowest position */ + if (plane_states[0]->fb->format->has_alpha) + return -EINVAL; + + for (i = 1; i < num_planes; i++) { + struct drm_plane_state *p_state = plane_states[i]; + struct drm_framebuffer *fb = p_state->fb; + struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state); + + /* + * The only alpha position is the lowest plane of the + * second pipe. + */ + if (fb->format->has_alpha) + current_pipe++; + + s_state->pipe = current_pipe; + } + if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) { DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n"); return -EINVAL; diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c index 900e716443b8..ec7b906dbb84 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.c +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c @@ -19,13 +19,6 @@ #include "sun4i_layer.h" #include "sunxi_engine.h" -struct sun4i_plane_desc { - enum drm_plane_type type; - u8 pipe; - const uint32_t *formats; - uint32_t nformats; -}; - static void sun4i_backend_layer_reset(struct drm_plane *plane) { struct sun4i_layer *layer = plane_to_sun4i_layer(plane); @@ -133,14 +126,7 @@ static const struct drm_plane_funcs sun4i_backend_layer_funcs = { .update_plane = drm_atomic_helper_update_plane, }; -static const uint32_t sun4i_backend_layer_formats_primary[] = { - DRM_FORMAT_ARGB8888, - DRM_FORMAT_RGB888, - DRM_FORMAT_RGB565, - DRM_FORMAT_XRGB8888, -}; - -static const uint32_t sun4i_backend_layer_formats_overlay[] = { +static const uint32_t sun4i_backend_layer_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_ARGB4444, DRM_FORMAT_ARGB1555, @@ -151,24 +137,9 @@ static const uint32_t sun4i_backend_layer_formats_overlay[] = { DRM_FORMAT_XRGB8888, }; -static const struct sun4i_plane_desc sun4i_backend_planes[] = { - { - .type = DRM_PLANE_TYPE_PRIMARY, - .pipe = 0, - .formats = sun4i_backend_layer_formats_primary, - .nformats = ARRAY_SIZE(sun4i_backend_layer_formats_primary), - }, - { - .type = DRM_PLANE_TYPE_OVERLAY, - .pipe = 1, - .formats = sun4i_backend_layer_formats_overlay, - .nformats = ARRAY_SIZE(sun4i_backend_layer_formats_overlay), - }, -}; - static struct sun4i_layer *sun4i_layer_init_one(struct drm_device *drm, struct sun4i_backend *backend, - const struct sun4i_plane_desc *plane) + enum drm_plane_type type) { struct sun4i_layer *layer; int ret; @@ -180,8 +151,9 @@ static struct sun4i_layer *sun4i_layer_init_one(struct drm_device *drm, /* possible crtcs are set later */ ret = drm_universal_plane_init(drm, &layer->plane, 0, &sun4i_backend_layer_funcs, - plane->formats, plane->nformats, - NULL, plane->type, NULL); + sun4i_backend_layer_formats, + ARRAY_SIZE(sun4i_backend_layer_formats), + NULL, type, NULL); if (ret) { dev_err(drm->dev, "Couldn't initialize layer\n"); return ERR_PTR(ret); @@ -206,11 +178,11 @@ struct drm_plane **sun4i_layers_init(struct drm_device *drm, if (!planes) return ERR_PTR(-ENOMEM); - for (i = 0; i < ARRAY_SIZE(sun4i_backend_planes); i++) { - const struct sun4i_plane_desc *plane = &sun4i_backend_planes[i]; + for (i = 0; i < SUN4I_BACKEND_NUM_LAYERS; i++) { + enum drm_plane_type type = i ? DRM_PLANE_TYPE_OVERLAY : DRM_PLANE_TYPE_PRIMARY; struct sun4i_layer *layer; - layer = sun4i_layer_init_one(drm, backend, plane); + layer = sun4i_layer_init_one(drm, backend, type); if (IS_ERR(layer)) { dev_err(drm->dev, "Couldn't initialize %s plane\n", i ? "overlay" : "primary"); @@ -219,12 +191,6 @@ struct drm_plane **sun4i_layers_init(struct drm_device *drm, drm_plane_create_zpos_immutable_property(&layer->plane, i); - DRM_DEBUG_DRIVER("Assigning %s plane to pipe %d\n", - i ? "overlay" : "primary", plane->pipe); - regmap_update_bits(engine->regs, SUN4I_BACKEND_ATTCTL_REG0(i), - SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK, - SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(plane->pipe)); - layer->id = i; planes[i] = &layer->plane; }; diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.h b/drivers/gpu/drm/sun4i/sun4i_layer.h index 75b4868ba87c..36b20265bd31 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.h +++ b/drivers/gpu/drm/sun4i/sun4i_layer.h @@ -24,6 +24,7 @@ struct sun4i_layer { struct sun4i_layer_state { struct drm_plane_state state; + unsigned int pipe; bool uses_frontend; }; From patchwork Mon Jan 22 10:35:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 125396 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1081606ljf; Mon, 22 Jan 2018 02:37:34 -0800 (PST) X-Google-Smtp-Source: AH8x224UPwBw/yrF0QlEKxzshtgmCVeMqPOngkYdQejByuMnKK6kK43b+mmPRaRS+vaAcw1QchZ9 X-Received: by 2002:a17:902:ab93:: with SMTP id f19-v6mr3282530plr.10.1516617454299; Mon, 22 Jan 2018 02:37:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516617454; cv=none; d=google.com; s=arc-20160816; b=tzXG2YPURXCSLCv+ru2ILxoNQeWB4kvni73AYe01JUqNw08K/2PxTOObqzEhU7niI+ AoDEixEDG1UNLLT6UfZoaps+wM3kIwN+k3WQm3QOm6UX1P6OIU3LGdk3PkXBFDojswXz 1TPvqEAdeaeOzMkN6QzGymjw4UpYDSR5H94AagEb1uCp2Hh9sERXTnpximefA42IOhBy eqzeLyOWAwnwnbs449+YHsWJuYgixN6GH/uP0wpxc9dePRSnXSvW8NI4mh5r50JSMaZS WsDcnSNW/P4pbCcxP6k4x4NkAVqoYcGylnTaTNzXPqNuM8GfkN6K60x4XaIcPRlZHGpb 0BBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=6xuHv+GcnuQqacuYD6mrfyt0JkRDejmUwWJXtOGqvJs=; b=Cip6vibW3RsBOq0CPXkFimswvNvDMoQC5+HPQm4c7fDmiPQD39qFzVYlAc55yb5DwG 6PHcRZaDfAinwiqlqVE0RDJSINGzfzfjUpkcWQpPLQMOS0d3wwwkadWhZT3rzk2eSpXk Zjj3rsO/fxq7U5Z5+TI4T9ACGXmJGUO44vJ55KG6LZjIs0+ZOVdVNVVeR3iz6zjzhYuS v5EpobTspkTn4itm8H0oRbMooLv8Wuk7eO9N0ypPrYMQNxcMW0rSSUJmgNT8DtxfBbmJ aEfzZaAkaSMFxdyhSJ/512msaT7KlE57CrsQ/Q0P+JYyuVkdXDs5HOILOXmhhTrrDBOr yy5Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h63si13616983pge.435.2018.01.22.02.37.33; Mon, 22 Jan 2018 02:37:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751492AbeAVKhc (ORCPT + 28 others); Mon, 22 Jan 2018 05:37:32 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:46577 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751371AbeAVKgV (ORCPT ); Mon, 22 Jan 2018 05:36:21 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 9D46720808; Mon, 22 Jan 2018 11:36:20 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 22DFF20737; Mon, 22 Jan 2018 11:35:57 +0100 (CET) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , daniel.vetter@intel.com, jani.nikula@linux.intel.com, seanpaul@chromium.org Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas@vitsch.nl Subject: [PATCH v2 17/19] drm/sun4i: backend: Make zpos configurable Date: Mon, 22 Jan 2018 11:35:46 +0100 Message-Id: X-Mailer: git-send-email 2.14.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that we have everything in place, we can make zpos configurable now. Change the zpos property from an immutable one to a regular. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_layer.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- git-series 0.9.1 Reviewed-by: Chen-Yu Tsai diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c index ec7b906dbb84..9e538f761dcb 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.c +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c @@ -163,6 +163,9 @@ static struct sun4i_layer *sun4i_layer_init_one(struct drm_device *drm, &sun4i_backend_layer_helper_funcs); layer->backend = backend; + drm_plane_create_zpos_property(&layer->plane, 0, 0, + SUN4I_BACKEND_NUM_LAYERS - 1); + return layer; } @@ -189,8 +192,6 @@ struct drm_plane **sun4i_layers_init(struct drm_device *drm, return ERR_CAST(layer); }; - drm_plane_create_zpos_immutable_property(&layer->plane, i); - layer->id = i; planes[i] = &layer->plane; }; From patchwork Mon Jan 22 10:35:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 125384 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1081157ljf; Mon, 22 Jan 2018 02:36:29 -0800 (PST) X-Google-Smtp-Source: AH8x225p6VWpqD2G0zSN/76pyN43q4FRWNChSd/cSWDG6QxAxBLr9CjIaiHnJWUrPuarWqbztjV5 X-Received: by 10.99.100.131 with SMTP id y125mr6723476pgb.359.1516617388930; Mon, 22 Jan 2018 02:36:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516617388; cv=none; d=google.com; s=arc-20160816; b=sbJrXJb7MPkdr7oA+B0A/RvK7ql6In4O+kWZgQ0t2LGJtzOrxPKMWQjepVsAZUNZqS waczINrNZEiAReKZximPwr7uGnMUJZF8jffRh249wmafcqpHtK7D+lg1XP8SLPErV6wB sUxKr5YuYhFHBXzpqmtuUSGEEO/AoeQ/d62slt88IeR/49CN8RzXbtDLMbevHAmLOhIU jnQmuaQPeJGPzzqw1VAQ+rfFaxVeCT/a4obb/mWw53HeicqIn9rvC5/kpm4VXjWIMtwQ 3Yqwt6+By9RjnMeGWg5yHh/zU+j0R1/J1Q/J/zwVYy5dBJ5vOCZLPRQuNv+JolfW8i1c aC6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=kHUBzesckPgXL5rVQG/KkKvP/LwOiqsHJMxDV4s28MI=; b=nGZOZ6Dg+JNFFDe85ku63RALr+dQqHYzi//AtXSIaXQMeUszWa2mswxos1PD4byldT 5FGR4iX9nCsU2pxgR39Ja6PoZVV2P502ZYSO56WfUP18+AiZmH+tZGCcgvBdwcmJkrXM MVosRqEIRLW6WzgGSSCMS32VJJwscmFLoScA2nWzTsAXTYw6mtyGpAygxR9oJ0Km4URQ csJOf6+V7UQGzTAiw61mG0ZkKhGSRzMgC4arICyFfpN6X4okN9dl389u/9TToDPthxIH OaYRAiLpUPGuPCp5z67t2EijcgkCF4lb1dr4dn0xabfcw0frpG9mv5MllUEmg452mT+4 rI1g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x33-v6si3306089plb.477.2018.01.22.02.36.28; Mon, 22 Jan 2018 02:36:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751409AbeAVKg0 (ORCPT + 28 others); Mon, 22 Jan 2018 05:36:26 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:46599 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751379AbeAVKgW (ORCPT ); Mon, 22 Jan 2018 05:36:22 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 044B020730; Mon, 22 Jan 2018 11:36:21 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 7E7A52075C; Mon, 22 Jan 2018 11:35:57 +0100 (CET) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , daniel.vetter@intel.com, jani.nikula@linux.intel.com, seanpaul@chromium.org Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas@vitsch.nl Subject: [PATCH v2 18/19] drm/sun4i: Add support for plane alpha Date: Mon, 22 Jan 2018 11:35:47 +0100 Message-Id: X-Mailer: git-send-email 2.14.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Our backend supports a per-plane alpha property. Support it through our new helper. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_backend.c | 16 +++++++++++++--- drivers/gpu/drm/sun4i/sun4i_backend.h | 3 +++ drivers/gpu/drm/sun4i/sun4i_layer.c | 2 ++ 3 files changed, 18 insertions(+), 3 deletions(-) -- git-series 0.9.1 diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index 38c4b44f6ff5..f5beeec06fd5 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -191,6 +191,15 @@ int sun4i_backend_update_layer_formats(struct sun4i_backend *backend, DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n", interlaced ? "on" : "off"); + val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha); + if (state->alpha != 255) + val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN; + regmap_update_bits(backend->engine.regs, + SUN4I_BACKEND_ATTCTL_REG0(layer), + SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK | + SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN, + val); + ret = sun4i_backend_drm_format_to_layer(plane, fb->format->format, &val); if (ret) { @@ -366,7 +375,7 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, DRM_DEBUG_DRIVER("Plane FB format is %s\n", drm_get_format_name(fb->format->format, &format_name)); - if (fb->format->has_alpha) + if (fb->format->has_alpha || (plane_state->alpha != 255)) num_alpha_planes++; DRM_DEBUG_DRIVER("Plane zpos is %d\n", @@ -419,7 +428,8 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, } /* We can't have an alpha plane at the lowest position */ - if (plane_states[0]->fb->format->has_alpha) + if (plane_states[0]->fb->format->has_alpha || + (plane_states[0]->alpha != 255)) return -EINVAL; for (i = 1; i < num_planes; i++) { @@ -431,7 +441,7 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, * The only alpha position is the lowest plane of the * second pipe. */ - if (fb->format->has_alpha) + if (fb->format->has_alpha || (p_state->alpha != 255)) current_pipe++; s_state->pipe = current_pipe; diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.h b/drivers/gpu/drm/sun4i/sun4i_backend.h index 52e77591186a..03294d5dd1a2 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.h +++ b/drivers/gpu/drm/sun4i/sun4i_backend.h @@ -68,11 +68,14 @@ #define SUN4I_BACKEND_CKMIN_REG 0x884 #define SUN4I_BACKEND_CKCFG_REG 0x888 #define SUN4I_BACKEND_ATTCTL_REG0(l) (0x890 + (0x4 * (l))) +#define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK GENMASK(31, 24) +#define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(x) ((x) << 24) #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK BIT(15) #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(x) ((x) << 15) #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK GENMASK(11, 10) #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(x) ((x) << 10) #define SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN BIT(1) +#define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN BIT(0) #define SUN4I_BACKEND_ATTCTL_REG1(l) (0x8a0 + (0x4 * (l))) #define SUN4I_BACKEND_ATTCTL_REG1_LAY_HSCAFCT GENMASK(15, 14) diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c index 9e538f761dcb..d5598de92f85 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.c +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c @@ -37,6 +37,7 @@ static void sun4i_backend_layer_reset(struct drm_plane *plane) if (state) { plane->state = &state->state; plane->state->plane = plane; + plane->state->alpha = 255; plane->state->zpos = layer->id; } } @@ -163,6 +164,7 @@ static struct sun4i_layer *sun4i_layer_init_one(struct drm_device *drm, &sun4i_backend_layer_helper_funcs); layer->backend = backend; + drm_plane_create_alpha_property(&layer->plane, 255); drm_plane_create_zpos_property(&layer->plane, 0, 0, SUN4I_BACKEND_NUM_LAYERS - 1);