From patchwork Thu Nov 26 15:28:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 333023 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1402489ilb; Thu, 26 Nov 2020 07:22:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJyL9B+PEa5FvoduHjcg/jaVYw/K+/YKl2k3orBKRXIuQwM9B+E3tKiNAJGEKFdPT1IYOkwr X-Received: by 2002:a50:9f61:: with SMTP id b88mr3143137edf.282.1606404172873; Thu, 26 Nov 2020 07:22:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606404172; cv=none; d=google.com; s=arc-20160816; b=krRU/EgP9s2fZpN5FHPNcHNCrclY6W4Gwq88MUKqwAVick03Kc8X16szciK5LbDqM8 QcWT35uAtxPT+yAQ/dyzP9Ia7Zv1v9Jlq09US+fVlDheL4v5YokIoQhX6vsqMb3BwAPO AsGFcYk0p9iPKk/SkGpoy9rmD3sNCF5b18WS0OkKebAsb0CIBk4PLD+Qclsbm3MW/Sgo ZDSQlMs5BMG8fjqLVXcIzOcSJAlXS7L7sTWrBTE/eNqJJ2GHAC++mVVhPv6sxwmb9zMB aAkv/gfEGcAkIDqUGwD/O6HyLSuCDlR848v3/fce6tfa9j82TNy2r8jeUD3IBZDbattR uRcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=aPLHqO7umAzH3uCMdx9gGdOu7TMdN7Har/HDHaaht+Q=; b=SZ87vQcMuoAmlXxZ2I1q3I+PFuh5PWwDCAt9SFnxh/cex+HLxVgfbTJzYAmNqnpCaB Lxv7kTc9zs9LNB92undPTIgqBpN4yqB5H4myUmEl0t7cK64L27K+uXcoO0FRCU+D3Tnp 6c+Spdfpvwej/C+86jD6ZgknlfvAD4j2wdc1Jgf92xh4Lu5E3n++SPXGustlIienObhb 950ybV/0tkQg9dOfJskzelwhafjoaIJORmFeKjD19nDA3t/8EwxBIH1h5M36RbImZgG0 JAAwzx+3HA/KuuFd+Lt8f+zy1irdB0xpQr29QS9xHYBphJcTfdKiwbyWAZhw5OqRFKyt O9BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B7EzWmQ7; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Today, it only zeroing the structure. Use this function from mhi_alloc_controller so that any further initialization can be factorized in initalize function. Signed-off-by: Loic Poulain --- drivers/bus/mhi/core/init.c | 7 +++++++ include/linux/mhi.h | 6 ++++++ 2 files changed, 13 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c index 96cde9c..4acad28 100644 --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c @@ -1021,11 +1021,18 @@ void mhi_unregister_controller(struct mhi_controller *mhi_cntrl) } EXPORT_SYMBOL_GPL(mhi_unregister_controller); +void mhi_initialize_controller(struct mhi_controller *mhi_cntrl) +{ + memset(mhi_cntrl, 0, sizeof(*mhi_cntrl)); +} +EXPORT_SYMBOL_GPL(mhi_initialize_controller); + struct mhi_controller *mhi_alloc_controller(void) { struct mhi_controller *mhi_cntrl; mhi_cntrl = kzalloc(sizeof(*mhi_cntrl), GFP_KERNEL); + mhi_initialize_controller(mhi_cntrl); return mhi_cntrl; } diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 5721a0a..30c676d 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -537,6 +537,12 @@ struct mhi_driver { #define to_mhi_device(dev) container_of(dev, struct mhi_device, dev) /** + * mhi_initialize_controller - Initialize MHI Controller structure + * @mhi_cntrl: MHI controller structure to initialize + */ +void mhi_initialize_controller(struct mhi_controller *mhi_cntrl); + +/** * mhi_alloc_controller - Allocate the MHI Controller structure * Allocate the mhi_controller structure using zero initialized memory */ From patchwork Thu Nov 26 15:29:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 333025 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1402498ilb; Thu, 26 Nov 2020 07:22:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJx+Q3bCZJODPBSeq6NfQCYsUbsR+4cE4CRD9MiSGb12OAHMZQ+6GMpH5JL7PLHvzlvwoegj X-Received: by 2002:aa7:d54b:: with SMTP id u11mr3075984edr.341.1606404173760; Thu, 26 Nov 2020 07:22:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606404173; cv=none; d=google.com; s=arc-20160816; b=mtAvTuWUBSKDPimmzxW/cGstgkJzDgTK/+jgwzl3tUmORXph5yG/Z+gWNNv4o9SiQ/ o8P5Sq6VMrZ1pqjh0BTzfaFvwRhjXD9l9VsTu5aEHmNBJ7bi5j3H0ftleWq8hsyx9mOy 09CUtxWja/LU1MxbfmVDRyvcVcSfJsMTVQHtlJ3p8VUdUTDLPZI/khvDbnP8JhAzGbqG 83+yfVUp9JR7hdz08MJzSx4wPDoLagtJEQ1YKKopbuNr8eU0stQVdho9LJXItOoVxIRq 4CQN/y0ONhqGzPnQvyIBDcw1Ojw98hlJrMNcosdbBmq0tB6VBCN5hJdEvZCFO5t2AM+O /3Uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=ay1QH2bUvbOIA2ZUFWy+JbT8fUAqvJZs5kOEe6ZTqSo=; b=zrBLOyf9K/C2un6KyFxXsYgIEiFFAmj7VSFZIXfv2kvMsjpMfSOsLwAudUJeWm0+uN npnK1nQu/f7M7egp3trlDqLu/6+Nr2Su5yvH5M3H5pi6xCN5NGfJDxxfJI12/Kt1TQGW MT3bkWyWOidZb/xoYpPIdLnt/QM/o8D7R22+V7U57/j5SHej/B4yDujHuhFH/W1c7SIf 7ySY1vy1DGOeqfB/7SJWPDTzBrGmj4varKBSk21ZwMAUf3Sv/EZ2ND7qaKXYxpd6pJfP VKCesbfV4a5BLfI28utIfTf1W8ySXhbpxNrvioz4BtxTIZ0CpXydHKbziXukHFtvMXR7 iWSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wo0gu/9z"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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That can be prevented by setting a larger number of events (i.e 2 x number of channel ring elements). Tested with FN980m module. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index f5bee76..d3896ef 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -91,7 +91,7 @@ struct mhi_pci_dev_info { #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ { \ - .num_elements = 128, \ + .num_elements = 256, \ .irq_moderation_ms = 5, \ .irq = (ev_ring) + 1, \ .priority = 1, \ From patchwork Thu Nov 26 15:29:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 333026 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1402503ilb; Thu, 26 Nov 2020 07:22:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJyCLcoTjI82LYkSyZBPnR1VIQQ/ni/XS3a3sxNgXHkwSuDGQqJwdNV5qL1SGv2M0RI/h8Mg X-Received: by 2002:a17:906:94d4:: with SMTP id d20mr2953688ejy.475.1606404174164; Thu, 26 Nov 2020 07:22:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606404174; cv=none; d=google.com; s=arc-20160816; b=SyU1gBA++HmMEIq5l8QN6GseJvmGmIzpMGLz2vizr5FSfM+WWn2EUiO6EuPe27T9OY DfvvDlDI6bz6feqrKv3APBxg5LN+yYdtNz+H4FIdFBB1jGkH2lrzo4X+NVZbjkR9pqmI /+NLCDfRjgafCLXgCGyYYmfRhmVaEQjxDBKB3VqbSh0tvZZpXBNUIuzlsUQBFQpCvcrP For1k73vsMybK2xboyugZMkiq5HTS0m3A+eJUGnT+BPLeI6/35CCF2j+0OAdhHH8UzRs OuS8rnaHI7YntBELMkKKsIxozax09Ro+e++uNNidw57IfpUoI7hyVH1bcpU0jUZJw2zL quNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=tNd+xLAqvcNUNm4KkwNzCttW0SqoWPgvkdRlPwE5A3M=; b=SlAuh9/3mVUa2QKPf9528mryK1UIEe2819BwvFmJu1mR6Sh6heUci9TdLgznQHJZ51 mT2PAvZ84FK9xfr70HjwhT8SplAYo7ZnQTQdbXjm77lBdWznNriKlNhYiGYcHI/Yz1Vf vKVlpVRt1AyWFfXG8NjqCccdCAtjWo3hW8nEnVQxuzzudxcMr0PIJyEcJmzQlruWxLAQ dpMsW2KljP25+ueMa5Be/g0txTCq5Ru6pPIRpf3dEganb16iuaVoGF+mHINxHUpo5VPx 0VyPJZ6umTFVSmMaSibcgS1Neuadoa7w3fQf8ET6Wm1GW7Iob91snKynM9VCYhCmK2ho bZSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rnz5Bph4; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This has been tested with Telit FN980m module. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index d3896ef..4363676 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -15,6 +15,8 @@ #define MHI_PCI_DEFAULT_BAR_NUM 0 +#define DEV_RESET_REG (0xB0) + /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration @@ -166,6 +168,11 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, /* Nothing to do for now */ } +static inline void mhi_pci_reset(struct mhi_controller *mhi_cntrl) +{ + writel(1, mhi_cntrl->regs + DEV_RESET_REG); +} + static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, unsigned int bar_num, u64 dma_mask) { @@ -329,6 +336,10 @@ static void mhi_pci_remove(struct pci_dev *pdev) mhi_power_down(mhi_cntrl, true); mhi_unprepare_after_power_down(mhi_cntrl); mhi_unregister_controller(mhi_cntrl); + + /* MHI-layer reset could not be enough, always hard-reset the device */ + mhi_pci_reset(mhi_cntrl); + mhi_free_controller(mhi_cntrl); } From patchwork Thu Nov 26 15:29:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 333027 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1402509ilb; Thu, 26 Nov 2020 07:22:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJwGHWQviV/D+h44Rg5naPEuQ4uHCIwOtKjMGWGAwEjBed4nW+CZHCJmpv7FaD7JEUP3AkP8 X-Received: by 2002:a17:906:4994:: with SMTP id p20mr3170934eju.391.1606404174779; Thu, 26 Nov 2020 07:22:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606404174; cv=none; d=google.com; s=arc-20160816; b=FfqE4M2HVP8cldHWA8pcUInRcnxPEPC64vh+wO2gZyY4eLc0T4ynuQsdgSN5f6sgbM 82m5/AebqXji9GhD4pEk6M/PvqhYHVzaB1qZrV5Ymk6ProZV8H5WL+F4YAvJGiZvPzqY LkCXp0ppvN4cR4gxqHdF4XBA4tbM0pDyX2Wn5CWb3KQv4Kyeoqyvwk5mhDW/oTVkEHle BTuphXqsrFDmvBFx1DunORR33ARV1dpZN9XL0Sy4F7YmIa8rfPMyu+aspA+y7gcKADsS aAL3xB4WpIGBzEg73CD/ChFCzCl17Z794br6IucNi5XqXCal5adveBU1BHZsmfrIkqMD ZtRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Q9zTqSWRADrCT+W1kE3DJbDxj2aY3KJG9TA1g4Ejo4Y=; b=jfWs7mJvU3gdaufKkLji857TvfSIofNftT9r2w6hiDtnBw5C7/Q2s2S9aGkmoTP6sK 1PTgmShw7NPLeO5KBGEWBy6fMMy1Yrp5DUrQg2WOEIAcXIj9X3ZVOPtlQjuEsaUyRZTv U0I9717Dalq3YO3zWtbQiYeEdlx0tIPgmSQf1UiE4jrYIbmatSVGalHCA87B5SJ1M720 llC3GcKg3SBIJTzPWPgd2aDzVtOhSm/GOkcAr+YuvEZfakVm4Q5L3JnxVxHjyvjTJdDq XD6+7/v9hWM4aVuSKahgdJaENdhaljyAIKNbcadanCKhCCNlnSFxPHD8cfVhPKkbSdUz AFoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uqI9Io6V; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w10si3453177edx.350.2020.11.26.07.22.54; Thu, 26 Nov 2020 07:22:54 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uqI9Io6V; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391308AbgKZPWV (ORCPT + 15 others); Thu, 26 Nov 2020 10:22:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391056AbgKZPWV (ORCPT ); Thu, 26 Nov 2020 10:22:21 -0500 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D239FC0613D4 for ; Thu, 26 Nov 2020 07:22:19 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id w24so2782082wmi.0 for ; Thu, 26 Nov 2020 07:22:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Q9zTqSWRADrCT+W1kE3DJbDxj2aY3KJG9TA1g4Ejo4Y=; b=uqI9Io6VNt5GihnMLaEVjkZ2AjV7skOUv9OT5KrqKfajn9EynTem1gxWDYwDirXs2f sihl9AcrjOt7CFbice5ORcyrd2bcHmV/8wmogJPq/Y121QBDz34tE6YDcJu9pouHBBaV ANlqIO5cuAPCJcI8t9X4YTxr7RkgI1mLLo/IuluLlzrKG6JfiAOqXBmkbgOwArmd7gzQ 0SOcAhHlkdC004ENzrHmcsh2DqRjAjY83WjxZysngksUL/AwFFY4OO9uhpwAxDGm5nUh xWtbjzL7VNk9YEkyjtl9eAQbuaAOaF4f2MKg4WMwe5aTWYKRzqk4qqsTu3g8/2LQWh1b v99A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Q9zTqSWRADrCT+W1kE3DJbDxj2aY3KJG9TA1g4Ejo4Y=; b=mhzQctoYefMT5NwBbMzrtu8AFsV3clZZh8I9iZW3t4dhUmgUjKa+VrOX3UVHyWFiNu AHu3uYBjPVngn2zxuPBbT/B5cFL3E5/tn83x0EimfKEWDB5BIfQHGtrKiwmGyOxScba/ m6g49Pfp8+bkI+U6qKjjvjLsPNi26F7yiG8sDoo2guREBZ5/D1KKcnRSCQvbDDMPU4Kl MnjXX9ON51IupgNOI76XzoUP/JTjRmSD5al7hJmmzsnIKp7N7W7YCuXcSKHOJmjvIYck N5QGmnF65w2sQ/26Nl2b/Zi/uIBQIP9j1cw/tERH7tisj65z9Y5tZB145W0Rlh5buGvK 9SYA== X-Gm-Message-State: AOAM532WGksjP1lAVXbNe5rP4N+CRUeXsh7OsAjNdZtbdES7Bcbez9J1 Z2YOTPOmsaPtzHMUv6mqpxv4kQ== X-Received: by 2002:a1c:3c84:: with SMTP id j126mr3985310wma.151.1606404138584; Thu, 26 Nov 2020 07:22:18 -0800 (PST) Received: from localhost.localdomain ([88.122.66.28]) by smtp.gmail.com with ESMTPSA id l10sm2756144wme.42.2020.11.26.07.22.17 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Nov 2020 07:22:18 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, Loic Poulain Subject: [PATCH v3 4/9] mhi: pci_generic: Enable burst mode for hardware channels Date: Thu, 26 Nov 2020 16:29:02 +0100 Message-Id: <1606404547-10737-5-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606404547-10737-1-git-send-email-loic.poulain@linaro.org> References: <1606404547-10737-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hardware channels have a feature called burst mode that allows to queue transfer ring element(s) (TRE) to a channel without ringing the device doorbell. In that mode, the device is polling the channel context for new elements. This reduces the frequency of host initiated doorbells and increase throughput. Create a new dedicated macro for hardware channels with burst enabled. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 4363676..6b6e5bf 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -78,6 +78,36 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } +#define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_TO_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = true, \ + } \ + +#define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_FROM_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = true, \ + } + #define MHI_EVENT_CONFIG_DATA(ev_ring) \ { \ .num_elements = 128, \ @@ -112,8 +142,8 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), - MHI_CHANNEL_CONFIG_UL(100, "IP_HW0", 128, 1), - MHI_CHANNEL_CONFIG_DL(101, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), }; static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { From patchwork Thu Nov 26 15:29:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 333028 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1402515ilb; Thu, 26 Nov 2020 07:22:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJwQv6k/kWjgbLBtbdiD32djZPLPean6cl4v0Sc6E6iHMgHr29ETmLRaeZqe2LX/Ta/aJcpk X-Received: by 2002:a17:906:bd2:: with SMTP id y18mr3097864ejg.503.1606404175247; Thu, 26 Nov 2020 07:22:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606404175; cv=none; d=google.com; s=arc-20160816; b=HYuWtpLG9qFxVOa6mw/gbeZc4GBiBEoYkE1neYbBxsPCQOiFglQmflPFoFKgJq02fA L0Pw0hJz67ZiDpNXGlTkR7SEmNymnjrAhoehgPrtS5ud8bo7at+c5xXJCMAxKtCh0CYQ 7OyFFEZtGe8VkEJCseUD2Ojyx2ApclqLlf0WGMMIhet+xbC+8Hkvs9SfY0Fjoc43mONu NEHkwAoy3WJyZQIoJiPwjB3wfrPdniS5ilugbqG1NCC1mEPIyYp5hrpgmsv606+BmE01 0tQARFxXgIfZ3Ou56BI0KyX8R3kbsPHSZ18PBhTlJ/DFXBHIxLtTAbH1RKEoYyCym+s3 QaVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=i28TA7DOXXOlf677dk3S2DHq5Mg0aoCnvns0vKvzXw8=; b=gokbDGjuREzC9lWZZ5CKwv4lp+DfTB15G6cRbAyjfGYGeTch4CzVawUeKSlUIL7CWV lVLOkhZm5fcHeKMigkTd8lcPNRVJFEF4taVhsM5/ZM9L6SJb6240sYJPI3duJxCBGxlD Z+Mxbqh1BeKaElDVWN2gLv3AaLNPrTPyoYiQqD2t7JjIj843A0ub7blhhRwa7w48qwW8 L/JNMOJbIyVzAJ66BN3sZiHcWbnb2fEYRYyfyib6Hd0Otus1ZeY+4WgdLQpt2NFQVx4i 34rWapOjTJgADPMNdPXsnC1r9YeAmOn2PFpF6STnHfKbzwkcYCvD6PKn1u+Gjm6pl0vl N1ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QqQYzHqQ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 119 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 106 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 6b6e5bf..67fcbcf 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 Linaro Ltd */ +#include #include #include #include @@ -179,6 +180,16 @@ static const struct pci_device_id mhi_pci_id_table[] = { }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); +enum mhi_pci_device_status { + MHI_PCI_DEV_STARTED, +}; + +struct mhi_pci_device { + struct mhi_controller mhi_cntrl; + struct pci_saved_state *pci_state; + unsigned long status; +}; + static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 *out) { @@ -203,6 +214,20 @@ static inline void mhi_pci_reset(struct mhi_controller *mhi_cntrl) writel(1, mhi_cntrl->regs + DEV_RESET_REG); } +static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) +{ + struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); + u16 vendor = 0; + + if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor)) + return false; + + if (vendor == (u16) ~0 || vendor == 0) + return false; + + return true; +} + static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, unsigned int bar_num, u64 dma_mask) { @@ -298,16 +323,20 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; const struct mhi_controller_config *mhi_cntrl_config; + struct mhi_pci_device *mhi_pdev; struct mhi_controller *mhi_cntrl; int err; dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name); - mhi_cntrl = mhi_alloc_controller(); - if (!mhi_cntrl) + mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); + if (!mhi_pdev) return -ENOMEM; mhi_cntrl_config = info->config; + mhi_cntrl = &mhi_pdev->mhi_cntrl; + + mhi_initialize_controller(mhi_cntrl); mhi_cntrl->cntrl_dev = &pdev->dev; mhi_cntrl->iova_start = 0; mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width); @@ -322,17 +351,21 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); if (err) - goto err_release; + return err; err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); if (err) - goto err_release; + return err; + + pci_set_drvdata(pdev, mhi_pdev); - pci_set_drvdata(pdev, mhi_cntrl); + /* Have stored pci confspace at hand for restore in sudden PCI error */ + pci_save_state(pdev); + mhi_pdev->pci_state = pci_store_saved_state(pdev); err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); if (err) - goto err_release; + return err; /* MHI bus does not power up the controller by default */ err = mhi_prepare_for_power_up(mhi_cntrl); @@ -347,37 +380,97 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto err_unprepare; } + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + return 0; err_unprepare: mhi_unprepare_after_power_down(mhi_cntrl); err_unregister: mhi_unregister_controller(mhi_cntrl); -err_release: - mhi_free_controller(mhi_cntrl); return err; } static void mhi_pci_remove(struct pci_dev *pdev) { - struct mhi_controller *mhi_cntrl = pci_get_drvdata(pdev); + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, true); + mhi_unprepare_after_power_down(mhi_cntrl); + } - mhi_power_down(mhi_cntrl, true); - mhi_unprepare_after_power_down(mhi_cntrl); mhi_unregister_controller(mhi_cntrl); /* MHI-layer reset could not be enough, always hard-reset the device */ mhi_pci_reset(mhi_cntrl); +} + +void mhi_pci_reset_prepare(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + dev_info(&pdev->dev, "reset\n"); + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } + + /* cause internal device reset */ + mhi_pci_reset(mhi_cntrl); + + /* Be sure device reset has been executed */ + msleep(500); +} + +void mhi_pci_reset_done(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + /* Restore initial known working PCI state */ + pci_load_saved_state(pdev, mhi_pdev->pci_state); + pci_restore_state(pdev); + + /* Is device status available ? */ + if (!mhi_pci_is_alive(mhi_cntrl)) { + dev_err(&pdev->dev, "reset failed\n"); + return; + } - mhi_free_controller(mhi_cntrl); + err = mhi_prepare_for_power_up(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to prepare MHI controller\n"); + return; + } + + err = mhi_sync_power_up(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to power up MHI controller\n"); + mhi_unprepare_after_power_down(mhi_cntrl); + return; + } + + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); } +static const struct pci_error_handlers mhi_pci_err_handler = { + .reset_prepare = mhi_pci_reset_prepare, + .reset_done = mhi_pci_reset_done, +}; + static struct pci_driver mhi_pci_driver = { .name = "mhi-pci-generic", .id_table = mhi_pci_id_table, .probe = mhi_pci_probe, - .remove = mhi_pci_remove + .remove = mhi_pci_remove, + .err_handler = &mhi_pci_err_handler, }; module_pci_driver(mhi_pci_driver); From patchwork Thu Nov 26 15:29:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 333029 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1402520ilb; Thu, 26 Nov 2020 07:22:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJyh4sjDGxGFIe3eXfC87mosmNVMF3bq6APJA33H6yPf/+KuCmVcG397DCPRAsCW8m1bNnvN X-Received: by 2002:a17:906:3bd6:: with SMTP id v22mr3226536ejf.160.1606404175678; Thu, 26 Nov 2020 07:22:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606404175; cv=none; d=google.com; s=arc-20160816; b=RvU88iq7oOMen0ogPJ4WrC1DEMnLvSHxiGjnOExePaQ0uHCCVElfJ78DH1nWerUUdl Chj6rBVV8QRD0xTHCtxvf+nL/28TGGE6NZW1LsYk4sACyKMNE2BqdZ3Q5L8mXCmO9tTv /EuTn6qfDsgqH8sqaY4KLP4Y9eyAoBSLYpF58a/xC22c+LRzTIjYi4ZdfJgueVGaHuY2 5MlP279zcMjPWdG+lt1gNtbAjLx3vptOaG0om2fse79RNRdGoT38bwv4ll3rzoI/8DOv nrpLWrX70iZCyCBbwTq8TCUgnrFsJx1EoJIRe70EybW+IwQWFsydu1jBKGDWXaCGNOm+ QkdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=S2YIODlUjYnbR8vGoOQUbNfWgpKp3X534Xh5o6umMnc=; b=HOVwHBJdRepw7+ePQ37DwAhgyIXRokaQoTTpqinQYB3NtUISdDaXwqbivuYRn4gUUX 1QIU2KXnl1ZREqF8AeLvMYB/m/Z2XVSfisUyhKRQjSXGJMG74Q6BpjNIcm1praslyAvA STEvPPXjEcIT21lQ5Z8moYrRx3Rl7IyPJnmPEBViGUhUutHbVVTwHSMVQNjAjkS1x5+0 Ytu5uadoctJ0NgNPqLUbSvuE08R7OTbi9B7f6A0RztYQHESQ10IO8jENlvkEwZ0ECqZY FLBmZbe6ZW7MPmAzd5ljXZEdXYn62oAhfGTqc3zcKor8VMA1wlWQSLRyDCgDskkS+uX3 DzoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CCzGvHau; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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During suspend, MHI device controller must be put in M3 state and PCI bus in D3 state. Add a recovery procedure allowing to reinitialize the device in case of error during resume steps, which can happen if device loses power (and so its context) while system suspend. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 102 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 67fcbcf..9919ad6 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -13,6 +13,7 @@ #include #include #include +#include #define MHI_PCI_DEFAULT_BAR_NUM 0 @@ -187,6 +188,7 @@ enum mhi_pci_device_status { struct mhi_pci_device { struct mhi_controller mhi_cntrl; struct pci_saved_state *pci_state; + struct work_struct recovery_work; unsigned long status; }; @@ -319,6 +321,48 @@ static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) /* no PM for now */ } +static void mhi_pci_recovery_work(struct work_struct *work) +{ + struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, + recovery_work); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); + int err; + + dev_warn(&pdev->dev, "device recovery started\n"); + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } + + /* Check if we can recover without full reset */ + pci_set_power_state(pdev, PCI_D0); + pci_load_saved_state(pdev, mhi_pdev->pci_state); + pci_restore_state(pdev); + + if (!mhi_pci_is_alive(mhi_cntrl)) + goto err_try_reset; + + err = mhi_prepare_for_power_up(mhi_cntrl); + if (err) + goto err_try_reset; + + err = mhi_sync_power_up(mhi_cntrl); + if (err) + goto err_unprepare; + + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + return; + +err_unprepare: + mhi_unprepare_after_power_down(mhi_cntrl); +err_try_reset: + if (pci_reset_function(pdev)) + dev_err(&pdev->dev, "Recovery failed\n"); +} + static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; @@ -333,6 +377,8 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (!mhi_pdev) return -ENOMEM; + INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); + mhi_cntrl_config = info->config; mhi_cntrl = &mhi_pdev->mhi_cntrl; @@ -397,6 +443,8 @@ static void mhi_pci_remove(struct pci_dev *pdev) struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + cancel_work_sync(&mhi_pdev->recovery_work); + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, true); mhi_unprepare_after_power_down(mhi_cntrl); @@ -465,12 +513,66 @@ static const struct pci_error_handlers mhi_pci_err_handler = { .reset_done = mhi_pci_reset_done, }; +int __maybe_unused mhi_pci_suspend(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + cancel_work_sync(&mhi_pdev->recovery_work); + + /* Transition to M3 state */ + mhi_pm_suspend(mhi_cntrl); + + pci_save_state(pdev); + pci_disable_device(pdev); + pci_wake_from_d3(pdev, true); + pci_set_power_state(pdev, PCI_D3hot); + + return 0; +} + +static int __maybe_unused mhi_pci_resume(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); + pci_set_master(pdev); + + err = pci_enable_device(pdev); + if (err) + goto err_recovery; + + /* Exit M3, transition to M0 state */ + err = mhi_pm_resume(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to resume device: %d\n", err); + goto err_recovery; + } + + return 0; + +err_recovery: + /* The device may have loose power or crashed, try recovering it */ + queue_work(system_long_wq, &mhi_pdev->recovery_work); + return 0; +} + +static const struct dev_pm_ops mhi_pci_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mhi_pci_suspend, mhi_pci_resume) +}; + static struct pci_driver mhi_pci_driver = { .name = "mhi-pci-generic", .id_table = mhi_pci_id_table, .probe = mhi_pci_probe, .remove = mhi_pci_remove, .err_handler = &mhi_pci_err_handler, + .driver.pm = &mhi_pci_pm_ops }; module_pci_driver(mhi_pci_driver); From patchwork Thu Nov 26 15:29:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 333030 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1402527ilb; Thu, 26 Nov 2020 07:22:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJxY2fuNJra+lglvbu3CGJmN7evR/9g1mgAf7k+cz8Xi/jANBw3hCqqPQw5iIbuuITBcaB5O X-Received: by 2002:a17:906:6d8e:: with SMTP id h14mr3238229ejt.522.1606404176127; Thu, 26 Nov 2020 07:22:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606404176; cv=none; d=google.com; s=arc-20160816; b=RuN/FtN4uf3VgnWF2ZG06Ktn9OP5LtVRgzuVodxh5QR8b8NuH8dPrKd3q/iHzfLYeA UkgI2FQbGBKMMncub4+qYhsak766An4m2Lz/5TImbmrzjTZ1B6Rdymxgj9wlOaUGhEb0 7hkAz60IYTHWLuHA1QQ5do32Kv6j4ylNapPlHhlTENd7r7f4jFP7FqcNWhXwwrUjaXZO ULdWqYTUjt7+NGut5lPd9Dqavb6gbNtYm8XJnrHN6xCOVNiKUk/946gpUTb8xz9Rm42x 0H14bUcRr4qxFncAHlqCXlRTGOeQ0894IoR5m+sOwVNDzxnpq3XKJ/U0hLzNVnl7fwaK llCQ== ARC-Message-Signature: i=1; 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This patch enables error reporting and implements error_detected, slot_reset and resume callbacks. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 50 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 9919ad6..3ac5cd2 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 Linaro Ltd */ +#include #include #include #include @@ -409,6 +410,8 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_save_state(pdev); mhi_pdev->pci_state = pci_store_saved_state(pdev); + pci_enable_pcie_error_reporting(pdev); + err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); if (err) return err; @@ -508,7 +511,54 @@ void mhi_pci_reset_done(struct pci_dev *pdev) set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); } +static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); + + if (state == pci_channel_io_perm_failure) + return PCI_ERS_RESULT_DISCONNECT; + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } else { + /* Nothing to do */ + return PCI_ERS_RESULT_RECOVERED; + } + + pci_disable_device(pdev); + + return PCI_ERS_RESULT_NEED_RESET; +} + +static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) +{ + if (pci_enable_device(pdev)) { + dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + + return PCI_ERS_RESULT_RECOVERED; +} + +static void mhi_pci_io_resume(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + + dev_err(&pdev->dev, "PCI slot reset done\n"); + + queue_work(system_long_wq, &mhi_pdev->recovery_work); +} + static const struct pci_error_handlers mhi_pci_err_handler = { + .error_detected = mhi_pci_error_detected, + .slot_reset = mhi_pci_slot_reset, + .resume = mhi_pci_io_resume, .reset_prepare = mhi_pci_reset_prepare, .reset_done = mhi_pci_reset_done, }; From patchwork Thu Nov 26 15:29:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 333032 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1402542ilb; Thu, 26 Nov 2020 07:22:57 -0800 (PST) X-Google-Smtp-Source: ABdhPJyViP2Ud4rXKDCG4mCN5pph6UtpDj2otkVjm/L33RBfjAx3Pcop20+Yhex+AwvnMqiUV+lR X-Received: by 2002:a17:906:af0a:: with SMTP id lx10mr3139968ejb.75.1606404177031; Thu, 26 Nov 2020 07:22:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606404177; cv=none; d=google.com; s=arc-20160816; b=qKQVbI2rg2v7txiLtG7Wng2Kh3Bn7iUrCFSqd9pIJpXt2udEtv4GCiFKGIV6O5NAOW 1JtFJJ7KyY9gXRT2xMTTdJuF/XqqIwM1NCTqDq4Ep+zi0QpzcqoKygDv8ky/nLYkVrkU vJtCMZuBf7KKxsF6CLCC172Jgyv8W0U29TlMzPoswXN9k6SvZGYnnloXfI9V8Y7aIYBN j8Wm3KvjTEdb9NaTy+FpwqodCmlr8oRDPrV5PRxH2T7dbckDaEp/qY3GArpwA+kr1Xom hm4+x76gJ4YjE/wqgn5Q1B+BdPNAEhVBBz5Pwm+OqvqVw++KJ19G5oqANoeoRZPycS77 dc0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=T9NdeCY8lnXyB3TYArwpP2Vm2Myt8lw3Dn2sdkapntA=; b=Ha93qutqaslWs1S+69+Py0Muwe+3AduFVwDCn+Qtwl/VNJclzQfn3JUFAHm4yFubX4 yZyAabE4cC4zWXBYe803glAikXVSMhzXmaPgRIRbleW60fI4oq7N08G+56SPzlJbGG6h prM2jM7Nbg/NuFqa6rSFlAopABrgENqwUBsc3iHK0iLeAZ64Tb4gR9V5O6h7nUUUD0BX F8LdvZvU9XEg2/0TP+VTDAab4C1p8Zxv4bVetKLNRbC/u3sGlk/Riu56/9rdOTC6uAUz IbCjald6szpEWHP0ZyIA2MMc1rcBB49pr2pKHuRrA/yeB1T8hHt5qWYn+fP/1JgSfMvu xaug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a5rhygAQ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w10si3453177edx.350.2020.11.26.07.22.56; Thu, 26 Nov 2020 07:22:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a5rhygAQ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391261AbgKZPW0 (ORCPT + 15 others); Thu, 26 Nov 2020 10:22:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391314AbgKZPWZ (ORCPT ); Thu, 26 Nov 2020 10:22:25 -0500 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E512C0613D4 for ; Thu, 26 Nov 2020 07:22:24 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id g14so2495286wrm.13 for ; Thu, 26 Nov 2020 07:22:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T9NdeCY8lnXyB3TYArwpP2Vm2Myt8lw3Dn2sdkapntA=; b=a5rhygAQ31gr+pcb9zgfWoQQfi6406vqyZKupj4U2kYr7ELRyjqTbg4wL0gb8fwl9C FlWQVTlXWEfM7mQwV9Qsm8qOpJBARWG5H07FUm6QLw7pJ2I64jvpgfWhqQ/Yo96GqJhR IXjRU157qlTHwyH5ZViBGNTCxgq3nHPh0cErqjmRiGgvoY0eUQkGM+qeKxh2WwuBLyyZ M6gTnX//vJcv8Ngzm95GisKW1aUch+21jWnIOCAZMuVwEjLLchJzySZqDNACSdnlGHh2 TFsIDdIlxz9VoNz+gEKKTVy0bM5ZrJZQjsys7j+562ndjc3I12tBVouHFnmyqryf1S2Z EuZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T9NdeCY8lnXyB3TYArwpP2Vm2Myt8lw3Dn2sdkapntA=; b=DgbTGBZcdlRJjwUKXqdLDIOGdIt10IbpV5RYekbwYQZe0ClnSBa21cV9ItH6uKT2Ao cUrmdxh6Up3FvX80g0HWo9K7yCIZryd8TLjjifFcS2dUfWYxzD8Us7WRmhGraLEYGAUh cCexkgK/JKg6lkZYfRXlX3+3XFIM0AIUwdypPjE8+8IMqKOKrA6KUHAPSsPnRH29kxip TzndIpi8dI/0ZbCNE/UtU6Afgh5+bSZxhWdIuY/tGiUavV7/NttW5gkWLemY7FcuvLQ9 w+/uYhf8rwuBZk6wHsuXa2ww+GfZdhbgdey08mbFGrVbArYVnNbbZeVHijnpo14fZ6iN PwcA== X-Gm-Message-State: AOAM532z23yC5eW1lHHHxnNPqugOFUKaFGrVaz2GJUK+rSrn1ttRZEzV kVlceGu3miMhZBNjzJPj2eh+bA== X-Received: by 2002:adf:9144:: with SMTP id j62mr4422501wrj.419.1606404142755; Thu, 26 Nov 2020 07:22:22 -0800 (PST) Received: from localhost.localdomain ([88.122.66.28]) by smtp.gmail.com with ESMTPSA id l10sm2756144wme.42.2020.11.26.07.22.21 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Nov 2020 07:22:22 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, Loic Poulain Subject: [PATCH v3 8/9] mhi: pci_generic: Add health-check Date: Thu, 26 Nov 2020 16:29:06 +0100 Message-Id: <1606404547-10737-9-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606404547-10737-1-git-send-email-loic.poulain@linaro.org> References: <1606404547-10737-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If the modem crashes for any reason, we may not be able to detect it at MHI level (MHI registers not reachable anymore). This patch implements a health-check mechanism to check regularly that device is alive (MHI layer can communicate with). If device is not alive (because a crash or unexpected reset), the recovery procedure is triggered. Tested successfully with Telit FN980m module. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam Reviewed-by: Hemant Kumar diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 3ac5cd2..26c2dfa 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -14,12 +14,15 @@ #include #include #include +#include #include #define MHI_PCI_DEFAULT_BAR_NUM 0 #define DEV_RESET_REG (0xB0) +#define HEALTH_CHECK_PERIOD (HZ * 5) + /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration @@ -190,6 +193,7 @@ struct mhi_pci_device { struct mhi_controller mhi_cntrl; struct pci_saved_state *pci_state; struct work_struct recovery_work; + struct timer_list health_check_timer; unsigned long status; }; @@ -332,6 +336,8 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_warn(&pdev->dev, "device recovery started\n"); + del_timer(&mhi_pdev->health_check_timer); + /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, false); @@ -355,6 +361,7 @@ static void mhi_pci_recovery_work(struct work_struct *work) goto err_unprepare; set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); return; err_unprepare: @@ -364,6 +371,21 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_err(&pdev->dev, "Recovery failed\n"); } +static void health_check(struct timer_list *t) +{ + struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + if (!mhi_pci_is_alive(mhi_cntrl)) { + dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); + queue_work(system_long_wq, &mhi_pdev->recovery_work); + return; + } + + /* reschedule in two seconds */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); +} + static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; @@ -379,6 +401,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return -ENOMEM; INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); + timer_setup(&mhi_pdev->health_check_timer, health_check, 0); mhi_cntrl_config = info->config; mhi_cntrl = &mhi_pdev->mhi_cntrl; @@ -431,6 +454,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + /* start health check */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + return 0; err_unprepare: @@ -446,6 +472,7 @@ static void mhi_pci_remove(struct pci_dev *pdev) struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { @@ -466,6 +493,8 @@ void mhi_pci_reset_prepare(struct pci_dev *pdev) dev_info(&pdev->dev, "reset\n"); + del_timer(&mhi_pdev->health_check_timer); + /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, false); @@ -509,6 +538,7 @@ void mhi_pci_reset_done(struct pci_dev *pdev) } set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); } static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, @@ -569,6 +599,7 @@ int __maybe_unused mhi_pci_suspend(struct device *dev) struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); /* Transition to M3 state */ @@ -604,6 +635,9 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) goto err_recovery; } + /* Resume health check */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + return 0; err_recovery: From patchwork Thu Nov 26 15:29:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 333031 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp1402535ilb; Thu, 26 Nov 2020 07:22:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJygTv/bCFtY02+1psW0uVCQA53lAtrf4Hqe3UTISOTiIz17PTFnCA9Fn7T+u9mGXDRmdINz X-Received: by 2002:aa7:dd0d:: with SMTP id i13mr3067999edv.174.1606404176608; Thu, 26 Nov 2020 07:22:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606404176; cv=none; d=google.com; s=arc-20160816; b=cwudkFq3yfc4VDxzL9I2nh4G7S08DpKxw7YGfbjqQwKyFwB7G65WfkQsw8rELnRSHb peQR6d0Q1pphmXBJXPlg3tcsPbJTaxzZJ9NNlleOd20rE8jOAXrYRA/PaethM6VshfbS PjEBdkJFT2yTpfdUAEjg7UReUeyPVKWMm0Ym8mOJEftrluyRZXGz/04V3gslP9iqA++t GSZMJN6kylAN7HgnmBb89JvMncipHcAlzga9hUu3VjZpoXwitk8mdTqNNmf64Ct5F7hm /9NtVOvkxgmVjUXcluphJl99H2FRwNKwfUGoZ/r/DhGFhPDu5UonikaCMda6Ot0NUSb4 qChA== ARC-Message-Signature: i=1; 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Increase the timeout to prevent MHI power-up issues. Signed-off-by: Loic Poulain Reviewed-by: Hemant Kumar --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Manivannan Sadhasivam diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 26c2dfa..bbecec0 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -162,7 +162,7 @@ static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { .max_channels = 128, - .timeout_ms = 5000, + .timeout_ms = 8000, .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), .ch_cfg = modem_qcom_v1_mhi_channels, .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),