From patchwork Sun Jan 21 12:27:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 125280 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp655418ljf; Sun, 21 Jan 2018 03:38:02 -0800 (PST) X-Google-Smtp-Source: AH8x227qPA7XvRP2UI7ptyTI1edc+PDg9RZE2QLo+2BeEeiN+NBEfq5pcoNr9B0MzF+/U3y83Kds X-Received: by 10.98.204.75 with SMTP id a72mr4993350pfg.211.1516534682237; Sun, 21 Jan 2018 03:38:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516534682; cv=none; d=google.com; s=arc-20160816; b=cxEVbCpRkXFBMG8QWn8Ap8QWab6Q2/V15q0PWRko+fsPRaK3TGjivxGtpKQ6pdD+9x u0kKnoPRjlsf3AyeGHfndnq6pfEO0ibvYrseOyDvjHws/J28oiw4I6mdBlm/f9jwLYww tlPoIePt0Q405/G1VDTUSAmGvWvTvAgZwRBIkxI3tIfLqnNu0Yf5Q02g+iWJ4WjTw5NO KWo38dlC+a3aSQhB/Vxi9lYBzGltbm3/tQo8CcjaNeh3VLQa0k8OhG/RjibVXvl8VVnC 2zTa6syoiFaVkf+c1SyOZRb5Q8Kj7qdaC1VrCoi3Gzr6dl8gdWevoes07rG0YbDqsMIS X2gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=TrU2oBPBXfdC9+5iDEd4oTSZjoh1Qhl+qWvOHSoiWxI=; b=KW3g9hn4L6BKeq2CC0P3fdrTq/wcvGGOo/n9cVGVqHidD+a7nnkgb/nqAI+LBcyC6p PUZlycotQ+1i7Gv9PphaURfcuzGvYqyJLXz+N+A0EV58kVMXGGalToq0qdJEMGqYx69l bQmUHdat23rWDG+hv6TG6yZp2oFiwq/i4jOfZlMtolxnwjUA02Vod69w2PXS19ZEYgxz s8cI3vbBJr2T5xbpsys+PyQ/oERJzx7HQkGvg+2LVOyNwGUPo5061BWyTftIknEcYwrK Mct3Sq5OrG/gfHKrHy5KHG7/unAnkHHIGHfh0nBaIiS2Z0kFjplNUk5XTim2/NPWuuXN Mwpg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z10si11906948pgv.473.2018.01.21.03.38.01; Sun, 21 Jan 2018 03:38:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751473AbeAULh7 (ORCPT + 28 others); Sun, 21 Jan 2018 06:37:59 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:50588 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751154AbeAULgV (ORCPT ); Sun, 21 Jan 2018 06:36:21 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 63A812C2934D1; Sun, 21 Jan 2018 19:36:11 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.361.1; Sun, 21 Jan 2018 19:36:05 +0800 From: John Garry To: , , , , , , , , , , CC: , , , , , , , , Zhichang Yuan , Gabriele Paoloni , John Garry Subject: [PATCH v11 1/9] LIB: Introduce a generic PIO mapping method Date: Sun, 21 Jan 2018 20:27:19 +0800 Message-ID: <1516537647-50553-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516537647-50553-1-git-send-email-john.garry@huawei.com> References: <1516537647-50553-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhichang Yuan In commit 41f8bba7f555 ("of/pci: Add pci_register_io_range() and pci_pio_to_address()"), a new I/O space management was supported. With that driver, the I/O ranges configured for PCI/PCIe hosts on some architectures can be mapped to logical PIO, converted easily between CPU address and the corresponding logicial PIO. Based on this, PCI I/O devices can be accessed in a memory read/write way through the unified in/out accessors. But on some archs/platforms, there are bus hosts which access I/O peripherals with host-local I/O port addresses rather than memory addresses after memory-mapped. To support those devices, a more generic I/O mapping method is introduced here. Through this patch, both the CPU addresses and the host-local port can be mapped into the logical PIO space with different logical/fake PIOs. After this, all the I/O accesses to either PCI MMIO devices or host-local I/O peripherals can be unified into the existing I/O accessors defined in asm-generic/io.h and be redirected to the right device-specific hooks based on the input logical PIO. Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni Signed-off-by: John Garry --- include/asm-generic/io.h | 2 + include/linux/logic_pio.h | 141 +++++++++++++++++++++++ lib/Kconfig | 15 +++ lib/Makefile | 2 + lib/logic_pio.c | 286 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 446 insertions(+) create mode 100644 include/linux/logic_pio.h create mode 100644 lib/logic_pio.c -- 1.9.1 diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index b4531e3..b7996a79 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -351,6 +351,8 @@ static inline void writesq(volatile void __iomem *addr, const void *buffer, #define IO_SPACE_LIMIT 0xffff #endif +#include + /* * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be * implemented on hardware that needs an additional delay for I/O accesses to diff --git a/include/linux/logic_pio.h b/include/linux/logic_pio.h new file mode 100644 index 0000000..9545c77 --- /dev/null +++ b/include/linux/logic_pio.h @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2017 Hisilicon Limited, All Rights Reserved. + * Author: Gabriele Paoloni + * Author: Zhichang Yuan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __LINUX_LOGIC_PIO_H +#define __LINUX_LOGIC_PIO_H + +#ifdef __KERNEL__ + +#include + +#define PIO_INDIRECT 0x01UL /* indirect IO flag */ +#define PIO_CPU_MMIO 0x00UL /* memory mapped io flag */ + +struct logic_pio_hwaddr { + struct list_head list; + struct fwnode_handle *fwnode; + resource_size_t hw_start; + resource_size_t io_start; + resource_size_t size; /* range size populated */ + unsigned long flags; + + void *devpara; /* private parameter of the host device */ + struct hostio_ops *ops; /* ops operating on this node */ +}; + +struct hostio_ops { + u32 (*pfin)(void *devobj, unsigned long ptaddr, size_t dlen); + void (*pfout)(void *devobj, unsigned long ptaddr, u32 outval, + size_t dlen); + u32 (*pfins)(void *devobj, unsigned long ptaddr, void *inbuf, + size_t dlen, unsigned int count); + void (*pfouts)(void *devobj, unsigned long ptaddr, + const void *outbuf, size_t dlen, unsigned int count); +}; + +#ifdef CONFIG_INDIRECT_PIO +u8 logic_inb(unsigned long addr); +void logic_outb(u8 value, unsigned long addr); +void logic_outw(u16 value, unsigned long addr); +void logic_outl(u32 value, unsigned long addr); +u16 logic_inw(unsigned long addr); +u32 logic_inl(unsigned long addr); +void logic_outb(u8 value, unsigned long addr); +void logic_outw(u16 value, unsigned long addr); +void logic_outl(u32 value, unsigned long addr); +void logic_insb(unsigned long addr, void *buffer, unsigned int count); +void logic_insl(unsigned long addr, void *buffer, unsigned int count); +void logic_insw(unsigned long addr, void *buffer, unsigned int count); +void logic_outsb(unsigned long addr, const void *buffer, unsigned int count); +void logic_outsw(unsigned long addr, const void *buffer, unsigned int count); +void logic_outsl(unsigned long addr, const void *buffer, unsigned int count); + +#ifndef inb +#define inb logic_inb +#endif + +#ifndef inw +#define inw logic_inw +#endif + +#ifndef inl +#define inl logic_inl +#endif + +#ifndef outb +#define outb logic_outb +#endif + +#ifndef outw +#define outw logic_outw +#endif + +#ifndef outl +#define outl logic_outl +#endif + +#ifndef insb +#define insb logic_insb +#endif + +#ifndef insw +#define insw logic_insw +#endif + +#ifndef insl +#define insl logic_insl +#endif + +#ifndef outsb +#define outsb logic_outsb +#endif + +#ifndef outsw +#define outsw logic_outsw +#endif + +#ifndef outsl +#define outsl logic_outsl +#endif + +/* + * Below we reserve 0x4000 bytes for Indirect IO as so far this library is only + * used by Hisilicon LPC Host. If needed in future we may reserve a wider IO + * area by redefining the macro below. + */ +#define PIO_INDIRECT_SIZE 0x4000 +#define MMIO_UPPER_LIMIT (IO_SPACE_LIMIT - PIO_INDIRECT_SIZE) +#else +#define MMIO_UPPER_LIMIT IO_SPACE_LIMIT +#endif /* CONFIG_INDIRECT_PIO */ + + +struct logic_pio_hwaddr *find_io_range_by_fwnode(struct fwnode_handle *fwnode); + +unsigned long logic_pio_trans_hwaddr(struct fwnode_handle *fwnode, + resource_size_t hw_addr, resource_size_t size); + +int logic_pio_register_range(struct logic_pio_hwaddr *newrange); + + +extern resource_size_t logic_pio_to_hwaddr(unsigned long pio); + +extern unsigned long logic_pio_trans_cpuaddr(resource_size_t hw_addr); + +#endif /* __KERNEL__ */ +#endif /* __LINUX_LOGIC_PIO_H */ diff --git a/lib/Kconfig b/lib/Kconfig index e960894..7ad1e69 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -55,6 +55,21 @@ config ARCH_USE_CMPXCHG_LOCKREF config ARCH_HAS_FAST_MULTIPLIER bool +config INDIRECT_PIO + bool "Access I/O in non-MMIO mode" + depends on ARM64 + help + On some platforms where no separate I/O space exists, there are I/O + hosts which can not be accessed in MMIO mode. Using the logical PIO + mechanism, the host-local I/O resource can be mapped into system + logic PIO space shared with MMIO hosts, such as PCI/PCIE, then the + system can access the I/O devices with the mapped logic PIO through + I/O accessors. + This way has a relatively little I/O performance cost. Please make + sure your devices really need this configure item enabled. + + When in doubt, say N. + config CRC_CCITT tristate "CRC-CCITT functions" help diff --git a/lib/Makefile b/lib/Makefile index a90d4fc..4a9eacd 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -81,6 +81,8 @@ obj-$(CONFIG_HAS_IOMEM) += iomap_copy.o devres.o obj-$(CONFIG_CHECK_SIGNATURE) += check_signature.o obj-$(CONFIG_DEBUG_LOCKING_API_SELFTESTS) += locking-selftest.o +obj-y += logic_pio.o + obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o obj-$(CONFIG_BTREE) += btree.o diff --git a/lib/logic_pio.c b/lib/logic_pio.c new file mode 100644 index 0000000..adc22bd --- /dev/null +++ b/lib/logic_pio.c @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2017 Hisilicon Limited, All Rights Reserved. + * Author: Gabriele Paoloni + * Author: Zhichang Yuan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +/* The unique hardware address list. */ +static LIST_HEAD(io_range_list); +static DEFINE_MUTEX(io_range_mutex); + +/* + * register a new io range node in the io range list. + * + * @newrange: pointer to the io range to be registered. + * + * returns 0 on success, the error code in case of failure + */ +int logic_pio_register_range(struct logic_pio_hwaddr *new_range) +{ + struct logic_pio_hwaddr *range; + int ret = 0; + resource_size_t start = new_range->hw_start; + resource_size_t end = new_range->hw_start + new_range->size; + resource_size_t allocated_mmio_size = 0; + resource_size_t allocated_iio_size = MMIO_UPPER_LIMIT; + + if (!new_range || !new_range->fwnode || !new_range->size) + return -EINVAL; + + mutex_lock(&io_range_mutex); + list_for_each_entry_rcu(range, &io_range_list, list) { + + if (range->fwnode == new_range->fwnode) { + /* range already there */ + ret = -EFAULT; + goto end_register; + } + if (range->flags == PIO_CPU_MMIO && + new_range->flags == PIO_CPU_MMIO) { + /* for MMIO ranges we need to check for overlap */ + if (start >= range->hw_start + range->size || + end < range->hw_start) + allocated_mmio_size += range->size; + else { + ret = -EFAULT; + goto end_register; + } + } else if (range->flags == PIO_INDIRECT && + new_range->flags == PIO_INDIRECT) { + allocated_iio_size += range->size; + } + } + + /* range not registered yet, check for available space */ + if (new_range->flags == PIO_CPU_MMIO) { + + if (allocated_mmio_size + new_range->size - 1 > + MMIO_UPPER_LIMIT) { + /* if it's too big check if 64K space can be reserved */ + if (allocated_mmio_size + SZ_64K - 1 > + MMIO_UPPER_LIMIT) { + ret = -E2BIG; + goto end_register; + } + new_range->size = SZ_64K; + pr_warn("Requested IO range too big, new size set to 64K\n"); + } + + new_range->io_start = allocated_mmio_size; + + } else if (new_range->flags == PIO_INDIRECT) { + + if (allocated_iio_size + new_range->size - 1 > + IO_SPACE_LIMIT) { + ret = -E2BIG; + goto end_register; + } + new_range->io_start = allocated_iio_size; + + } else { + /* invalid flag */ + ret = -EINVAL; + goto end_register; + } + + list_add_tail_rcu(&new_range->list, &io_range_list); + +end_register: + mutex_unlock(&io_range_mutex); + return ret; +} + +/* + * traverse the io_range_list to find the registered node whose device node + * and/or physical IO address match to. + */ +struct logic_pio_hwaddr *find_io_range_by_fwnode(struct fwnode_handle *fwnode) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (range->fwnode == fwnode) + return range; + } + return NULL; +} + +/* return a registered range given an input PIO token */ +static struct logic_pio_hwaddr *find_io_range(unsigned long pio) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (pio >= range->io_start && + pio < range->io_start + range->size) + return range; + } + pr_err("PIO entry token invalid\n"); + return NULL; +} + +/* + * Translate the input logical pio to the corresponding hardware address. + * The input pio should be unique in the whole logical PIO space. + */ +resource_size_t logic_pio_to_hwaddr(unsigned long pio) +{ + struct logic_pio_hwaddr *range; + resource_size_t hwaddr = -1; + + range = find_io_range(pio); + if (range) + hwaddr = range->hw_start + pio - range->io_start; + + return hwaddr; +} + +/* + * This function is generic for translating a hardware address to logical PIO. + * @hw_addr: the hardware address of host, can be CPU address or host-local + * address; + */ +unsigned long +logic_pio_trans_hwaddr(struct fwnode_handle *fwnode, resource_size_t addr, + resource_size_t size) +{ + struct logic_pio_hwaddr *range; + + range = find_io_range_by_fwnode(fwnode); + if (!range || range->flags == PIO_CPU_MMIO) { + pr_err("range not found or invalid\n"); + return -1; + } + if (range->size < size) { + pr_err("resource size 0x%llx cannot fit in IO range size 0x%llx\n", + size, range->size); + return -1; + } + return addr - range->hw_start + range->io_start; +} + +unsigned long +logic_pio_trans_cpuaddr(resource_size_t addr) +{ + struct logic_pio_hwaddr *range; + + list_for_each_entry_rcu(range, &io_range_list, list) { + if (range->flags != PIO_CPU_MMIO) + continue; + if (addr >= range->hw_start && + addr < range->hw_start + range->size) + return addr - range->hw_start + + range->io_start; + } + pr_err("addr not registered in io_range_list\n"); + return -1; +} + +#if defined(CONFIG_INDIRECT_PIO) && defined(PCI_IOBASE) +#define BUILD_LOGIC_IO(bw, type) \ +type logic_in##bw(unsigned long addr) \ +{ \ + type ret = -1; \ + \ + if (addr < MMIO_UPPER_LIMIT) { \ + ret = read##bw(PCI_IOBASE + addr); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + ret = entry->ops->pfin(entry->devpara, \ + addr, sizeof(type)); \ + else \ + WARN_ON_ONCE(1); \ + } \ + return ret; \ +} \ + \ +void logic_out##bw(type value, unsigned long addr) \ +{ \ + if (addr < MMIO_UPPER_LIMIT) { \ + write##bw(value, PCI_IOBASE + addr); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + entry->ops->pfout(entry->devpara, \ + addr, value, sizeof(type)); \ + else \ + WARN_ON_ONCE(1); \ + } \ +} \ + \ +void logic_ins##bw(unsigned long addr, void *buffer, unsigned int count)\ +{ \ + if (addr < MMIO_UPPER_LIMIT) { \ + reads##bw(PCI_IOBASE + addr, buffer, count); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + entry->ops->pfins(entry->devpara, \ + addr, buffer, sizeof(type), count); \ + else \ + WARN_ON_ONCE(1); \ + } \ + \ +} \ + \ +void logic_outs##bw(unsigned long addr, const void *buffer, \ + unsigned int count) \ +{ \ + if (addr < MMIO_UPPER_LIMIT) { \ + writes##bw(PCI_IOBASE + addr, buffer, count); \ + } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ + struct logic_pio_hwaddr *entry = find_io_range(addr); \ + \ + if (entry && entry->ops) \ + entry->ops->pfouts(entry->devpara, \ + addr, buffer, sizeof(type), count); \ + else \ + WARN_ON_ONCE(1); \ + } \ +} + +BUILD_LOGIC_IO(b, u8) + +EXPORT_SYMBOL(logic_inb); +EXPORT_SYMBOL(logic_outb); +EXPORT_SYMBOL(logic_insb); +EXPORT_SYMBOL(logic_outsb); + +BUILD_LOGIC_IO(w, u16) + +EXPORT_SYMBOL(logic_inw); +EXPORT_SYMBOL(logic_outw); +EXPORT_SYMBOL(logic_insw); +EXPORT_SYMBOL(logic_outsw); + +BUILD_LOGIC_IO(l, u32) + +EXPORT_SYMBOL(logic_inl); +EXPORT_SYMBOL(logic_outl); +EXPORT_SYMBOL(logic_insl); +EXPORT_SYMBOL(logic_outsl); +#endif /* CONFIG_INDIRECT_PIO && PCI_IOBASE */ From patchwork Sun Jan 21 12:27:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 125279 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp655403ljf; Sun, 21 Jan 2018 03:38:00 -0800 (PST) X-Google-Smtp-Source: AH8x227E+ka1udy8gRkai2ezc5OWRQEiHComwFj0xCZqCmCRE2Hn93DrtrwxwcINcrZodYQbUc4e X-Received: by 10.101.101.71 with SMTP id a7mr4366771pgw.192.1516534680068; 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[209.132.180.67]) by mx.google.com with ESMTP id u189si10864117pgc.253.2018.01.21.03.37.59; Sun, 21 Jan 2018 03:38:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751444AbeAULh6 (ORCPT + 28 others); Sun, 21 Jan 2018 06:37:58 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:50555 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751147AbeAULgV (ORCPT ); Sun, 21 Jan 2018 06:36:21 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 3D26EF990E1B9; Sun, 21 Jan 2018 19:36:11 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.361.1; Sun, 21 Jan 2018 19:36:06 +0800 From: John Garry To: , , , , , , , , , , CC: , , , , , , , , Gabriele Paoloni , Zhichang Yuan Subject: [PATCH v11 4/9] PCI: Apply the new generic I/O management on PCI IO hosts Date: Sun, 21 Jan 2018 20:27:22 +0800 Message-ID: <1516537647-50553-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516537647-50553-1-git-send-email-john.garry@huawei.com> References: <1516537647-50553-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Gabriele Paoloni After introducing the new generic I/O space management in logic pio, the original PCI MMIO relevant helpers need to be updated based on the new interfaces. This patch adapts the corresponding code to match the changes introduced by logic pio. Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni Signed-off-by: Arnd Bergmann #earlier draft Acked-by: Bjorn Helgaas --- drivers/pci/pci.c | 95 +++++++++--------------------------------------- include/asm-generic/io.h | 2 +- 2 files changed, 18 insertions(+), 79 deletions(-) -- 1.9.1 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d60f0a3..54048fe 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -3368,17 +3369,6 @@ int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) } EXPORT_SYMBOL(pci_request_regions_exclusive); -#ifdef PCI_IOBASE -struct io_range { - struct list_head list; - phys_addr_t start; - resource_size_t size; -}; - -static LIST_HEAD(io_range_list); -static DEFINE_SPINLOCK(io_range_lock); -#endif - /* * Record the PCI IO range (expressed as CPU physical address + size). * Return a negative value if an error has occured, zero otherwise @@ -3386,51 +3376,28 @@ struct io_range { int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, resource_size_t size) { - int err = 0; - + int ret = 0; #ifdef PCI_IOBASE - struct io_range *range; - resource_size_t allocated_size = 0; - - /* check if the range hasn't been previously recorded */ - spin_lock(&io_range_lock); - list_for_each_entry(range, &io_range_list, list) { - if (addr >= range->start && addr + size <= range->start + size) { - /* range already registered, bail out */ - goto end_register; - } - allocated_size += range->size; - } + struct logic_pio_hwaddr *range; - /* range not registed yet, check for available space */ - if (allocated_size + size - 1 > IO_SPACE_LIMIT) { - /* if it's too big check if 64K space can be reserved */ - if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) { - err = -E2BIG; - goto end_register; - } - - size = SZ_64K; - pr_warn("Requested IO range too big, new size set to 64K\n"); - } + if (!size || addr + size < addr) + return -EINVAL; - /* add the range to the list */ range = kzalloc(sizeof(*range), GFP_ATOMIC); - if (!range) { - err = -ENOMEM; - goto end_register; - } + if (!range) + return -ENOMEM; - range->start = addr; + range->fwnode = fwnode; range->size = size; + range->hw_start = addr; + range->flags = PIO_CPU_MMIO; - list_add_tail(&range->list, &io_range_list); - -end_register: - spin_unlock(&io_range_lock); + ret = logic_pio_register_range(range); + if (ret) + kfree(range); #endif - return err; + return ret; } phys_addr_t pci_pio_to_address(unsigned long pio) @@ -3438,21 +3405,10 @@ phys_addr_t pci_pio_to_address(unsigned long pio) phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; #ifdef PCI_IOBASE - struct io_range *range; - resource_size_t allocated_size = 0; - - if (pio > IO_SPACE_LIMIT) + if (pio >= MMIO_UPPER_LIMIT) return address; - spin_lock(&io_range_lock); - list_for_each_entry(range, &io_range_list, list) { - if (pio >= allocated_size && pio < allocated_size + range->size) { - address = range->start + pio - allocated_size; - break; - } - allocated_size += range->size; - } - spin_unlock(&io_range_lock); + address = logic_pio_to_hwaddr(pio); #endif return address; @@ -3461,25 +3417,8 @@ phys_addr_t pci_pio_to_address(unsigned long pio) unsigned long __weak pci_address_to_pio(phys_addr_t address) { #ifdef PCI_IOBASE - struct io_range *res; - resource_size_t offset = 0; - unsigned long addr = -1; - - spin_lock(&io_range_lock); - list_for_each_entry(res, &io_range_list, list) { - if (address >= res->start && address < res->start + res->size) { - addr = address - res->start + offset; - break; - } - offset += res->size; - } - spin_unlock(&io_range_lock); - - return addr; + return logic_pio_trans_cpuaddr(address); #else - if (address > IO_SPACE_LIMIT) - return (unsigned long)-1; - return (unsigned long) address; #endif } diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index b7996a79..5a59931 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -901,7 +901,7 @@ static inline void iounmap(void __iomem *addr) #define ioport_map ioport_map static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) { - return PCI_IOBASE + (port & IO_SPACE_LIMIT); + return PCI_IOBASE + (port & MMIO_UPPER_LIMIT); } #endif From patchwork Sun Jan 21 12:27:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 125282 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp655714ljf; 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[209.132.180.67]) by mx.google.com with ESMTP id l9si8927813pff.155.2018.01.21.03.39.04; Sun, 21 Jan 2018 03:39:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751290AbeAULjC (ORCPT + 28 others); Sun, 21 Jan 2018 06:39:02 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:50568 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751149AbeAULgS (ORCPT ); Sun, 21 Jan 2018 06:36:18 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 16D982C040162; Sun, 21 Jan 2018 19:36:11 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.361.1; Sun, 21 Jan 2018 19:36:07 +0800 From: John Garry To: , , , , , , , , , , CC: , , , , , , , , Zhichang Yuan , Gabriele Paoloni Subject: [PATCH v11 5/9] OF: Add missing I/O range exception for indirect-IO devices Date: Sun, 21 Jan 2018 20:27:23 +0800 Message-ID: <1516537647-50553-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516537647-50553-1-git-send-email-john.garry@huawei.com> References: <1516537647-50553-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhichang Yuan There are some special ISA/LPC devices that work on a specific I/O range where it is not correct to specify a 'ranges' property in DTS parent node as cpu addresses translated from DTS node are only for memory space on some architectures, such as Arm64. Without the parent 'ranges' property, current of_translate_address() return an error. Here we add special handlings for this case. During the OF address translation, some checkings will be perfromed to identify whether the device node is registered as indirect-IO. If yes, the I/O translation will be done in a different way from that one of PCI MMIO. In this way, the I/O 'reg' property of the special ISA/LPC devices will be parsed correctly. Signed-off-by: zhichang.yuan Signed-off-by: Gabriele Paoloni Signed-off-by: Arnd Bergmann #earlier draft Acked-by: Rob Herring --- drivers/of/address.c | 91 +++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 75 insertions(+), 16 deletions(-) -- 1.9.1 diff --git a/drivers/of/address.c b/drivers/of/address.c index 85975fe..2cca626 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -564,9 +564,14 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus, * that translation is impossible (that is we are not dealing with a value * that can be mapped to a cpu physical address). This is not really specified * that way, but this is traditionally the way IBM at least do things + * + * Whenever the translation fails, the *host pointer will be set to the + * device that had registered logical PIO mapping, and the return code is + * relative to that node. */ static u64 __of_translate_address(struct device_node *dev, - const __be32 *in_addr, const char *rprop) + const __be32 *in_addr, const char *rprop, + struct device_node **host) { struct device_node *parent = NULL; struct of_bus *bus, *pbus; @@ -579,6 +584,7 @@ static u64 __of_translate_address(struct device_node *dev, /* Increase refcount at current level */ of_node_get(dev); + *host = NULL; /* Get parent & match bus type */ parent = of_get_parent(dev); if (parent == NULL) @@ -599,6 +605,8 @@ static u64 __of_translate_address(struct device_node *dev, /* Translate */ for (;;) { + struct logic_pio_hwaddr *iorange; + /* Switch to parent bus */ of_node_put(dev); dev = parent; @@ -611,6 +619,19 @@ static u64 __of_translate_address(struct device_node *dev, break; } + /* + * For indirectIO device which has no ranges property, get + * the address from reg directly. + */ + iorange = find_io_range_by_fwnode(&dev->fwnode); + if (iorange && (iorange->flags != PIO_CPU_MMIO)) { + result = of_read_number(addr + 1, na - 1); + pr_debug("indirectIO matched(%s) 0x%llx\n", + of_node_full_name(dev), result); + *host = of_node_get(dev); + break; + } + /* Get new parent bus and counts */ pbus = of_match_bus(parent); pbus->count_cells(dev, &pna, &pns); @@ -642,13 +663,32 @@ static u64 __of_translate_address(struct device_node *dev, u64 of_translate_address(struct device_node *dev, const __be32 *in_addr) { - return __of_translate_address(dev, in_addr, "ranges"); + struct device_node *host; + u64 ret; + + ret = __of_translate_address(dev, in_addr, "ranges", &host); + if (host) { + of_node_put(host); + return OF_BAD_ADDR; + } + + return ret; } EXPORT_SYMBOL(of_translate_address); u64 of_translate_dma_address(struct device_node *dev, const __be32 *in_addr) { - return __of_translate_address(dev, in_addr, "dma-ranges"); + struct device_node *host; + u64 ret; + + ret = __of_translate_address(dev, in_addr, "dma-ranges", &host); + + if (host) { + of_node_put(host); + return OF_BAD_ADDR; + } + + return ret; } EXPORT_SYMBOL(of_translate_dma_address); @@ -690,29 +730,48 @@ const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, } EXPORT_SYMBOL(of_get_address); +static u64 of_translate_ioport(struct device_node *dev, const __be32 *in_addr, + u64 size) +{ + u64 taddr; + unsigned long port; + struct device_node *host; + + taddr = __of_translate_address(dev, in_addr, "ranges", &host); + if (host) { + /* host specific port access */ + port = logic_pio_trans_hwaddr(&host->fwnode, taddr, size); + of_node_put(host); + } else { + /* memory mapped I/O range */ + port = pci_address_to_pio(taddr); + } + + if (port == (unsigned long)-1) + return OF_BAD_ADDR; + + return port; +} + static int __of_address_to_resource(struct device_node *dev, const __be32 *addrp, u64 size, unsigned int flags, const char *name, struct resource *r) { u64 taddr; - if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0) + if (flags & IORESOURCE_MEM) + taddr = of_translate_address(dev, addrp); + else if (flags & IORESOURCE_IO) + taddr = of_translate_ioport(dev, addrp, size); + else return -EINVAL; - taddr = of_translate_address(dev, addrp); + if (taddr == OF_BAD_ADDR) return -EINVAL; memset(r, 0, sizeof(struct resource)); - if (flags & IORESOURCE_IO) { - unsigned long port; - port = pci_address_to_pio(taddr); - if (port == (unsigned long)-1) - return -EINVAL; - r->start = port; - r->end = port + size - 1; - } else { - r->start = taddr; - r->end = taddr + size - 1; - } + + r->start = taddr; + r->end = taddr + size - 1; r->flags = flags; r->name = name ? name : dev->full_name; From patchwork Sun Jan 21 12:27:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 125277 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp655058ljf; Sun, 21 Jan 2018 03:36:50 -0800 (PST) X-Google-Smtp-Source: AH8x225BnrERxFv5Mw1j5OKSD3wAEgyFhPgSxzWfv2bAzm9IZKi4/zpdiYTz/jgxHjkgOnyVd/N2 X-Received: by 10.99.111.68 with SMTP id k65mr4385242pgc.446.1516534610640; Sun, 21 Jan 2018 03:36:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516534610; cv=none; d=google.com; s=arc-20160816; b=TtKhnQpnwUt0rnCqNDuh786VtMKYUGy/zuHnDtoXYgDmccvyHEtErE6rL/D04rO0Zj HyG5mnE2Xy1+sQyBlYYgRELfb2wA0ErBUjBAmXGtq+8qxHKjyC9cmYFm8zrQrTC4hPiM WnbePGMjPMMhilM4f/0Id2s+MW6HS6aGk4XAnFrRsKmv8qDVWECvKS943jsKI9582HT4 dPbxnFZkqWRTbL3k/yUyvAIf0Qpnk/QeGWtQ0dPRzIbGjM2rsqq7xfo4egR415uiK3UK dP47RWKEhmaA+eT0s1vfktghhx3FGk4nQkWleMSTo5vgWdRnHi+atfpzzkgk0xYKDrf5 2DTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=6U80ExICsO5sQX3fWn1uKQVKhW43rlpZUO2A3BuYDyE=; b=M5wiCVGMqZNJfJp8/u7n2QHbKMNr1ykpy+8cynTAydLQNcqZF6VSlTaymV/QJ+uwTv +drDHsX+aNsIhWZlfp5Vtt2SYbhxOxib3Ugrphn1od/EAjIRBrrLkap/tJRBBkm8P+nm 3E6yDPgPUGdSii9ANtu6xXkyuF7jVVbm5wi504czAyVmlD20zpOvXNkZznK4ERhw+7bw jN3zjafwbKRi3prMR9ryPGSvy4ugBxsvvrKPJBV1eRnKCZDN0Ud2f5TxT3BJhdey9nIn RJ9+Whvi5wcBsEbREAbe9HfMjUbB1o5ih/GTtNmZ2pZPWUkK6dUUb/ufqOQbtD+nEnfp AQwQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h63si11926950pge.435.2018.01.21.03.36.50; Sun, 21 Jan 2018 03:36:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751391AbeAULgs (ORCPT + 28 others); Sun, 21 Jan 2018 06:36:48 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:4262 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751342AbeAULgn (ORCPT ); Sun, 21 Jan 2018 06:36:43 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id CD222F9FA20C4; Sun, 21 Jan 2018 19:36:15 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.361.1; Sun, 21 Jan 2018 19:36:07 +0800 From: John Garry To: , , , , , , , , , , CC: , , , , , , , , Zhichang Yuan , "Zou Rongrong" , Gabriele Paoloni Subject: [PATCH v11 6/9] LPC: Support the LPC host on Hip06/Hip07 with DT bindings Date: Sun, 21 Jan 2018 20:27:24 +0800 Message-ID: <1516537647-50553-7-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516537647-50553-1-git-send-email-john.garry@huawei.com> References: <1516537647-50553-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhichang Yuan The low-pin-count(LPC) interface of Hip06/Hip07 accesses the peripherals in I/O port addresses. This patch implements the LPC host controller driver which perform the I/O operations on the underlying hardware. We don't want to touch those existing peripherals' driver, such as ipmi-bt. So this driver applies the indirect-IO introduced in the previous patch after registering an indirect-IO node to the indirect-IO devices list which will be searched in the I/O accessors to retrieve the host-local I/O port. Signed-off-by: Zou Rongrong Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni Acked-by: Rob Herring #dts part --- .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ++ drivers/bus/Kconfig | 8 + drivers/bus/Makefile | 1 + drivers/bus/hisi_lpc.c | 526 +++++++++++++++++++++ 4 files changed, 568 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt create mode 100644 drivers/bus/hisi_lpc.c -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt new file mode 100644 index 0000000..213181f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt @@ -0,0 +1,33 @@ +Hisilicon Hip06 low-pin-count device + Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which + provides I/O access to some legacy ISA devices. + Hip06 is based on arm64 architecture where there is no I/O space. So, the + I/O ports here are not cpu addresses, and there is no 'ranges' property in + LPC device node. + +Required properties: +- compatible: value should be as follows: + (a) "hisilicon,hip06-lpc" + (b) "hisilicon,hip07-lpc" +- #address-cells: must be 2 which stick to the ISA/EISA binding doc. +- #size-cells: must be 1 which stick to the ISA/EISA binding doc. +- reg: base memory range where the LPC register set is mapped. + +Note: + The node name before '@' must be "isa" to represent the binding stick to the + ISA/EISA binding specification. + +Example: + +isa@a01b0000 { + compatible = "hisilicon,hip06-lpc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x0 0xa01b0000 0x0 0x1000>; + + ipmi0: bt@e4 { + compatible = "ipmi-bt"; + device_type = "ipmi"; + reg = <0x01 0xe4 0x04>; + }; +}; diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 57e011d..91debe4 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -65,6 +65,14 @@ config BRCMSTB_GISB_ARB arbiter. This driver provides timeout and target abort error handling and internal bus master decoding. +config HISILICON_LPC + bool "Support for ISA I/O space on Hisilicon hip06/7" + depends on (ARM64 && (ARCH_HISI || COMPILE_TEST)) + select INDIRECT_PIO + help + Driver needed for some legacy ISA devices attached to Low-Pin-Count + on Hisilicon hip06/7 SoC. + config IMX_WEIM bool "Freescale EIM DRIVER" depends on ARCH_MXC diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 9bcd0bf..abc7a42 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_ARM_CCI) += arm-cci.o obj-$(CONFIG_ARM_CCN) += arm-ccn.o obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o +obj-$(CONFIG_HISILICON_LPC) += hisi_lpc.o obj-$(CONFIG_IMX_WEIM) += imx-weim.o obj-$(CONFIG_MIPS_CDMM) += mips_cdmm.o obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o diff --git a/drivers/bus/hisi_lpc.c b/drivers/bus/hisi_lpc.c new file mode 100644 index 0000000..4ce089a --- /dev/null +++ b/drivers/bus/hisi_lpc.c @@ -0,0 +1,526 @@ +/* + * Copyright (C) 2017 Hisilicon Limited, All Rights Reserved. + * Author: Zhichang Yuan + * Author: Zou Rongrong + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LPC_MIN_BUS_RANGE 0x0 + +/* + * The default maximal IO size for Hip06/Hip07 LPC bus. + * Defining the I/O range size as 0x4000 here should be sufficient for + * all peripherals under the bus. + */ +#define LPC_BUS_IO_SIZE 0x4000 + +/* + * Setting this bit means each IO operation will target to a + * different port address: + * 0 means repeatedly IO operations will stick on the same port, + * such as BT; + */ +#define FG_INCRADDR_LPC 0x02 + +struct lpc_cycle_para { + unsigned int opflags; + unsigned int csize; /* the data length of each operation */ +}; + +struct hisilpc_dev { + spinlock_t cycle_lock; + void __iomem *membase; + struct logic_pio_hwaddr *io_host; +}; + +/* The maximum continuous cycles per burst */ +#define LPC_MAX_BURST 16 +/* The IO cycle counts supported is four per operation at maximum */ +#define LPC_MAX_DULEN 4 +#if LPC_MAX_DULEN > LPC_MAX_BURST +#error "LPC.. MAX_DULEN must be not bigger than MAX_OPCNT!" +#endif + +#if LPC_MAX_BURST % LPC_MAX_DULEN +#error "LPC.. LPC_MAX_BURST must be multiple of LPC_MAX_DULEN!" +#endif + +#define LPC_REG_START 0x00 /* start a new LPC cycle */ +#define LPC_REG_OP_STATUS 0x04 /* the current LPC status */ +#define LPC_REG_IRQ_ST 0x08 /* interrupt enable&status */ +#define LPC_REG_OP_LEN 0x10 /* how many LPC cycles each start */ +#define LPC_REG_CMD 0x14 /* command for the required LPC cycle */ +#define LPC_REG_ADDR 0x20 /* LPC target address */ +#define LPC_REG_WDATA 0x24 /* data to be written */ +#define LPC_REG_RDATA 0x28 /* data coming from peer */ + + +/* The command register fields */ +#define LPC_CMD_SAMEADDR 0x08 +#define LPC_CMD_TYPE_IO 0x00 +#define LPC_CMD_WRITE 0x01 +#define LPC_CMD_READ 0x00 +/* the bit attribute is W1C. 1 represents OK. */ +#define LPC_STAT_BYIRQ 0x02 + +#define LPC_STATUS_IDLE 0x01 +#define LPC_OP_FINISHED 0x02 + +#define LPC_START_WORK 0x01 + +/* The minimal nanosecond interval for each query on LPC cycle status. */ +#define LPC_NSEC_PERWAIT 100 +/* + * The maximum waiting time is about 128us. + * It is specific for stream I/O, such as ins. + * The fastest IO cycle time is about 390ns, but the worst case will wait + * for extra 256 lpc clocks, so (256 + 13) * 30ns = 8 us. The maximum + * burst cycles is 16. So, the maximum waiting time is about 128us under + * worst case. + * choose 1300 as the maximum. + */ +#define LPC_MAX_WAITCNT 1300 +/* About 10us. This is specific for single IO operation, such as inb. */ +#define LPC_PEROP_WAITCNT 100 + +static inline int wait_lpc_idle(unsigned char *mbase, + unsigned int waitcnt) { + u32 opstatus; + + while (waitcnt--) { + ndelay(LPC_NSEC_PERWAIT); + opstatus = readl(mbase + LPC_REG_OP_STATUS); + if (opstatus & LPC_STATUS_IDLE) + return (opstatus & LPC_OP_FINISHED) ? 0 : (-EIO); + } + return -ETIME; +} + +/* + * hisilpc_target_in - trigger a series of lpc cycles to read required data + * from target peripheral. + * @lpcdev: pointer to hisi lpc device + * @para: some parameters used to control the lpc I/O operations + * @ptaddr: the lpc I/O target port address + * @buf: where the read back data is stored + * @opcnt: how many I/O operations required in this calling + * + * Only one byte data is read each I/O operation. + * + * Returns 0 on success, non-zero on fail. + */ +static int +hisilpc_target_in(struct hisilpc_dev *lpcdev, struct lpc_cycle_para *para, + unsigned long ptaddr, unsigned char *buf, + unsigned long opcnt) +{ + unsigned long cnt_per_trans; + unsigned int cmd_word; + unsigned int waitcnt; + int ret; + + if (!buf || !opcnt || !para || !para->csize || !lpcdev) + return -EINVAL; + + cmd_word = LPC_CMD_TYPE_IO | LPC_CMD_READ; + waitcnt = LPC_PEROP_WAITCNT; + if (!(para->opflags & FG_INCRADDR_LPC)) { + cmd_word |= LPC_CMD_SAMEADDR; + waitcnt = LPC_MAX_WAITCNT; + } + + ret = 0; + cnt_per_trans = (para->csize == 1) ? opcnt : para->csize; + for (; opcnt && !ret; cnt_per_trans = para->csize) { + unsigned long flags; + + /* whole operation must be atomic */ + spin_lock_irqsave(&lpcdev->cycle_lock, flags); + + writel_relaxed(cnt_per_trans, lpcdev->membase + LPC_REG_OP_LEN); + + writel_relaxed(cmd_word, lpcdev->membase + LPC_REG_CMD); + + writel_relaxed(ptaddr, lpcdev->membase + LPC_REG_ADDR); + + writel(LPC_START_WORK, lpcdev->membase + LPC_REG_START); + + /* whether the operation is finished */ + ret = wait_lpc_idle(lpcdev->membase, waitcnt); + if (!ret) { + opcnt -= cnt_per_trans; + for (cnt_per_trans--; cnt_per_trans--; buf++) + *buf = readb_relaxed(lpcdev->membase + + LPC_REG_RDATA); + *buf = readb(lpcdev->membase + LPC_REG_RDATA); + } + + spin_unlock_irqrestore(&lpcdev->cycle_lock, flags); + } + + return ret; +} + +/* + * hisilpc_target_out - trigger a series of lpc cycles to write required + * data to target peripheral. + * @lpcdev: pointer to hisi lpc device + * @para: some parameters used to control the lpc I/O operations + * @ptaddr: the lpc I/O target port address + * @buf: where the data to be written is stored + * @opcnt: how many I/O operations required + * + * Only one byte data is read each I/O operation. + * + * Returns 0 on success, non-zero on fail. + * + */ +static int +hisilpc_target_out(struct hisilpc_dev *lpcdev, struct lpc_cycle_para *para, + unsigned long ptaddr, const unsigned char *buf, + unsigned long opcnt) +{ + unsigned long cnt_per_trans; + unsigned int cmd_word; + unsigned int waitcnt; + int ret; + + if (!buf || !opcnt || !para || !lpcdev) + return -EINVAL; + + /* default is increasing address */ + cmd_word = LPC_CMD_TYPE_IO | LPC_CMD_WRITE; + waitcnt = LPC_PEROP_WAITCNT; + if (!(para->opflags & FG_INCRADDR_LPC)) { + cmd_word |= LPC_CMD_SAMEADDR; + waitcnt = LPC_MAX_WAITCNT; + } + + ret = 0; + cnt_per_trans = (para->csize == 1) ? opcnt : para->csize; + for (; opcnt && !ret; cnt_per_trans = para->csize) { + unsigned long flags; + + spin_lock_irqsave(&lpcdev->cycle_lock, flags); + + writel_relaxed(cnt_per_trans, lpcdev->membase + LPC_REG_OP_LEN); + writel_relaxed(cmd_word, lpcdev->membase + LPC_REG_CMD); + writel_relaxed(ptaddr, lpcdev->membase + LPC_REG_ADDR); + + opcnt -= cnt_per_trans; + for (; cnt_per_trans--; buf++) + writeb_relaxed(*buf, lpcdev->membase + LPC_REG_WDATA); + + writel(LPC_START_WORK, lpcdev->membase + LPC_REG_START); + + /* whether the operation is finished */ + ret = wait_lpc_idle(lpcdev->membase, waitcnt); + + spin_unlock_irqrestore(&lpcdev->cycle_lock, flags); + } + + return ret; +} + +static inline unsigned long +hisi_lpc_pio_to_addr(struct hisilpc_dev *lpcdev, unsigned long pio) +{ + return pio - lpcdev->io_host->io_start + + lpcdev->io_host->hw_start; +} + + +/** + * hisilpc_comm_in - read/input the data from the I/O peripheral + * through LPC. + * @devobj: pointer to the device information relevant to LPC controller. + * @pio: the target I/O port address. + * @dlen: the data length required to read from the target I/O port. + * + * when succeed, the data read back is stored in buffer pointed by inbuf. + * For inb, return the data read from I/O or -1 when error occur. + */ +static u32 hisilpc_comm_in(void *devobj, unsigned long pio, size_t dlen) +{ + int ret = 0; + unsigned char rd_data = 0; + unsigned long ptaddr; + struct lpc_cycle_para iopara; + struct hisilpc_dev *lpcdev = devobj; + + if (!lpcdev || !dlen || dlen > LPC_MAX_DULEN) + return -1; + + ptaddr = hisi_lpc_pio_to_addr(lpcdev, pio); + + iopara.opflags = FG_INCRADDR_LPC; + iopara.csize = dlen; + + ret = hisilpc_target_in(lpcdev, &iopara, ptaddr, &rd_data, dlen); + if (ret) + return -1; + + return le32_to_cpu((u32)rd_data); +} + +/** + * hisilpc_comm_out - output the data whose maximum length is four bytes + to the I/O peripheral through the LPC host. + * @devobj: pointer to the device information relevant to LPC controller. + * @pio: the target I/O port address. + * @outval: a value to be outputted from caller, maximum is four bytes. + * @dlen: the data length required writing to the target I/O port. + * + * This function is corresponding to out(b,w,l) only + * + */ +static void hisilpc_comm_out(void *devobj, unsigned long pio, + u32 outval, size_t dlen) +{ + unsigned long ptaddr; + struct hisilpc_dev *lpcdev = devobj; + struct lpc_cycle_para iopara; + const unsigned char *newbuf; + + if (!lpcdev || !dlen || dlen > LPC_MAX_DULEN) + return; + + outval = cpu_to_le32(outval); + + newbuf = (const unsigned char *)&outval; + ptaddr = hisi_lpc_pio_to_addr(lpcdev, pio); + + iopara.opflags = FG_INCRADDR_LPC; + iopara.csize = dlen; + + hisilpc_target_out(lpcdev, &iopara, ptaddr, newbuf, dlen); +} + +/* + * hisilpc_comm_ins - read/input the data in buffer to the I/O + * peripheral through LPC, it corresponds to ins(b,w,l) + * @devobj: pointer to the device information relevant to LPC controller. + * @pio: the target I/O port address. + * @inbuf: a buffer where read/input data bytes are stored. + * @dlen: the data length required writing to the target I/O port. + * @count: how many data units whose length is dlen will be read. + * + * when succeed, the data read back is stored in buffer pointed by inbuf. + * Returns 0 on success, -errno otherwise + * + */ +static u32 +hisilpc_comm_ins(void *devobj, unsigned long pio, void *inbuf, + size_t dlen, unsigned int count) +{ + struct hisilpc_dev *lpcdev = devobj; + struct lpc_cycle_para iopara; + unsigned char *newbuf; + unsigned int loopcnt, cntleft; + unsigned long ptaddr; + + if (!lpcdev || !inbuf || !count || !dlen || dlen > LPC_MAX_DULEN || + count % dlen) + return -EINVAL; + + iopara.opflags = 0; + if (dlen > 1) + iopara.opflags |= FG_INCRADDR_LPC; + iopara.csize = dlen; + + ptaddr = hisi_lpc_pio_to_addr(lpcdev, pio); + newbuf = inbuf; + /* + * ensure data stream whose length is multiple of dlen to be processed + * each IO input + */ + cntleft = count * dlen; + do { + int ret; + + loopcnt = min_t(unsigned int, LPC_MAX_BURST, cntleft); + ret = hisilpc_target_in(lpcdev, &iopara, ptaddr, + newbuf, loopcnt); + if (ret) + return ret; + newbuf += loopcnt; + cntleft -= loopcnt; + } while (cntleft); + + return 0; +} + +/* + * hisilpc_comm_outs - write/output the data in buffer to the I/O + * peripheral through LPC, it corresponds to outs(b,w,l) + * @devobj: pointer to the device information relevant to LPC controller. + * @pio: the target I/O port address. + * @outbuf: a buffer where write/output data bytes are stored. + * @dlen: the data length required writing to the target I/O port . + * @count: how many data units whose length is dlen will be written. + * + */ +static void +hisilpc_comm_outs(void *devobj, unsigned long pio, const void *outbuf, + size_t dlen, unsigned int count) +{ + struct hisilpc_dev *lpcdev = devobj; + struct lpc_cycle_para iopara; + const unsigned char *newbuf; + unsigned int loopcnt, cntleft; + unsigned long ptaddr; + + if (!lpcdev || !outbuf || !count || !dlen || dlen > LPC_MAX_DULEN || + count % dlen) + return; + + iopara.opflags = 0; + if (dlen > 1) + iopara.opflags |= FG_INCRADDR_LPC; + iopara.csize = dlen; + + ptaddr = hisi_lpc_pio_to_addr(lpcdev, pio); + newbuf = outbuf; + /* + * ensure data stream whose length is multiple of dlen to be processed + * each IO input + */ + cntleft = count * dlen; + do { + loopcnt = min_t(unsigned int, LPC_MAX_BURST, cntleft); + if (hisilpc_target_out(lpcdev, &iopara, ptaddr, newbuf, + loopcnt)) + break; + newbuf += loopcnt; + cntleft -= loopcnt; + } while (cntleft); +} + +static struct hostio_ops hisi_lpc_ops = { + .pfin = hisilpc_comm_in, + .pfout = hisilpc_comm_out, + .pfins = hisilpc_comm_ins, + .pfouts = hisilpc_comm_outs, +}; + +/** + * hisilpc_probe - the probe callback function for hisi lpc device, + * will finish all the initialization. + * @pdev: the platform device corresponding to hisi lpc + * + * Returns 0 on success, non-zero on fail. + */ +static int hisilpc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct hisilpc_dev *lpcdev; + int ret = 0; + + lpcdev = devm_kzalloc(dev, sizeof(struct hisilpc_dev), GFP_KERNEL); + if (!lpcdev) + return -ENOMEM; + + spin_lock_init(&lpcdev->cycle_lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + lpcdev->membase = devm_ioremap_resource(dev, res); + if (IS_ERR(lpcdev->membase)) { + dev_err(dev, "remap failed\n"); + return PTR_ERR(lpcdev->membase); + } + + /* register the LPC host PIO resources */ + { + struct logic_pio_hwaddr *range; + + range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL); + if (!range) + return -ENOMEM; + range->fwnode = dev->fwnode; + range->flags = PIO_INDIRECT; + range->size = LPC_BUS_IO_SIZE; + range->hw_start = LPC_MIN_BUS_RANGE; + + ret = logic_pio_register_range(range); + if (ret) { + kfree(range); + dev_err(dev, "register IO range failed (%d)!\n", ret); + return -ret; + } + lpcdev->io_host = range; + + /* + * It is time to start the children scanning: + * For ACPI children, the corresponding devices had been + * created during the ACPI enumeration. + * The OF scanning must be performed after initialization of + * 'lpcdev' to avoid some children which complete the scanning + * trigger the MMIO accesses which will probably cause a panic. + */ + ret = of_platform_populate(dev->of_node, NULL, NULL, dev); + if (ret) { + /* + * When LPC probing is not completely successful, set + * 'devpara' as NULL. This will make all the LPC I/O + * return failure directly without any hardware + * operations. It will prevent some peripherals which + * had not finished the initialization to manipulate + * I/O for safety. + */ + lpcdev->io_host->devpara = NULL; + dev_err(dev, "populate children failed(%d)\n", ret); + return ret; + } + } + lpcdev->io_host->devpara = lpcdev; + lpcdev->io_host->ops = &hisi_lpc_ops; + + dev_info(dev, "registered range[%pa - sz:%pa]\n", + &lpcdev->io_host->io_start, + &lpcdev->io_host->size); + + return ret; +} + +static const struct of_device_id hisilpc_of_match[] = { + { .compatible = "hisilicon,hip06-lpc", }, + { .compatible = "hisilicon,hip07-lpc", }, + {}, +}; + +static struct platform_driver hisilpc_driver = { + .driver = { + .name = "hisi_lpc", + .of_match_table = hisilpc_of_match, + }, + .probe = hisilpc_probe, +}; + +builtin_platform_driver(hisilpc_driver); From patchwork Sun Jan 21 12:27:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 125278 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp655288ljf; Sun, 21 Jan 2018 03:37:35 -0800 (PST) X-Google-Smtp-Source: AH8x225o1OM02Qg8lL0J8rnXYPNdP2jyANwRo0Be8FNNDxEKAfa47rauKGReuuPgs9owT/bULa0o X-Received: by 10.101.74.129 with SMTP id b1mr4443376pgu.317.1516534655086; Sun, 21 Jan 2018 03:37:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516534655; cv=none; d=google.com; s=arc-20160816; b=ks9mOPT2qiJJqAIJ1CY7XHV7pNUwHPCUu7gGe73SSIp3UYOwrlYlNuShStLrZYCWQR RcSFhywiEhXR110isgH2GQJjrDUaNIHhDzpyP1Al1eVi+X9OhtKF3che+dxI+Lmw9cbP ZItd6M/gx1alFKnLZTIUtqDIhqEC92+0XIJLXZd2wyLrLvAnGuLhoRs2vDctFIUfBGsf LF9K9CKMBWL95Xs20xSbIQnuEqrGPBzHUD17R09wObmEZDQH7Bl9zroVHZ7MYxIEWgKs m9ouhVnAvOXAkJbLCqKEaz09Hdd1q/wBx03JAEID1PsKXxbvbwKJEltx0CA+XufMUS/W hgLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=6ZZxifXEQQyFfDkle+jxFcl3M233tnoM8/X7ExcFYT8=; b=UJu/dsyXcInPDlCgo4Y0t0BDwlJJ+73ovScMUKSmezWEg0K09j/K7I6xK/WcMhm00k H/OycCKLvkqzJgH69/HUQk6ccIuINxzsUjHhm84qT9ENmL5ZmB3Gipu29GLILJtcDH4Z HVAQHH24IQbmRr7qlVnwVsGZSZ8c5ZhVY3EKkSll2GJBVuwzHzPOg/FKRT3ztSZOAfUa NbXGMRs9BpATaY2IHHNmKLUSwtQzLvAxQZfMni1pBtVocOs6uqnjSd+NP8Bk1EIAaDFr BCHnrGs4ib4oCH4+Vsu2Tzxw4sU9maWRyW29W+faA3+4o8icQY/BCvMukpsQVf6Nbews Q0KQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h9-v6si2492696plt.274.2018.01.21.03.37.34; Sun, 21 Jan 2018 03:37:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751392AbeAULhb (ORCPT + 28 others); Sun, 21 Jan 2018 06:37:31 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:50647 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751237AbeAULgW (ORCPT ); Sun, 21 Jan 2018 06:36:22 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 110858B03E61D; Sun, 21 Jan 2018 19:36:16 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.361.1; Sun, 21 Jan 2018 19:36:07 +0800 From: John Garry To: , , , , , , , , , , CC: , , , , , , , , John Garry , "Zhichang Yuan" , Gabriele Paoloni Subject: [PATCH v11 7/9] ACPI: Translate the I/O range of non-MMIO devices before scanning Date: Sun, 21 Jan 2018 20:27:25 +0800 Message-ID: <1516537647-50553-8-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516537647-50553-1-git-send-email-john.garry@huawei.com> References: <1516537647-50553-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On some platforms(such as Hip06/Hip07), the legacy ISA/LPC devices access I/O with some special host-local I/O ports known on x86. As their I/O space are not memory mapped like PCI/PCIE MMIO host bridges, this patch is meant to support a new class of I/O host controllers where the local IO ports of the children devices are translated into the Indirect I/O address space. Through the handler attach callback, all the I/O translations are done before starting the enumeration on children devices and the translated addresses are replaced in the children resources. Signed-off-by: John Garry Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni --- drivers/acpi/arm64/Makefile | 1 + drivers/acpi/arm64/acpi_indirectio.c | 273 +++++++++++++++++++++++++++++++++++ drivers/acpi/internal.h | 5 + drivers/acpi/scan.c | 1 + 4 files changed, 280 insertions(+) create mode 100644 drivers/acpi/arm64/acpi_indirectio.c -- 1.9.1 diff --git a/drivers/acpi/arm64/Makefile b/drivers/acpi/arm64/Makefile index 1017def..f4a7f46 100644 --- a/drivers/acpi/arm64/Makefile +++ b/drivers/acpi/arm64/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_ACPI_IORT) += iort.o obj-$(CONFIG_ACPI_GTDT) += gtdt.o +obj-$(CONFIG_INDIRECT_PIO) += acpi_indirectio.o diff --git a/drivers/acpi/arm64/acpi_indirectio.c b/drivers/acpi/arm64/acpi_indirectio.c new file mode 100644 index 0000000..2649f57 --- /dev/null +++ b/drivers/acpi/arm64/acpi_indirectio.c @@ -0,0 +1,273 @@ +/* + * ACPI support for indirect-IO bus. + * + * Copyright (C) 2017 HiSilicon Limited, All Rights Reserved. + * Author: Gabriele Paoloni + * Author: Zhichang Yuan + * Author: John Garry + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +ACPI_MODULE_NAME("indirect IO"); + +#define ACPI_INDIRECTIO_NAME_LENGTH 255 + +#define INDIRECT_IO_INFO(desc) ((unsigned long)&desc) + +struct acpi_indirectio_mfd_cell { + struct mfd_cell_acpi_match acpi_match; + char name[ACPI_INDIRECTIO_NAME_LENGTH]; + char pnpid[ACPI_INDIRECTIO_NAME_LENGTH]; +}; + +struct acpi_indirectio_host_data { + resource_size_t io_size; + resource_size_t io_start; +}; + +struct acpi_indirectio_device_desc { + struct acpi_indirectio_host_data pdata; /* device relevant info data */ + int (*pre_setup)(struct acpi_device *adev, + struct acpi_indirectio_host_data *pdata); +}; + +static int acpi_translate_logicio_res(struct acpi_device *adev, + struct acpi_device *host, struct resource *resource) +{ + unsigned long sys_port; + struct device *dev = &adev->dev; + resource_size_t length = resource->end - resource->start; + + sys_port = logic_pio_trans_hwaddr(&host->fwnode, resource->start, + length); + + if (sys_port == -1) { + dev_err(dev, "translate bus-addr(0x%llx) fail!\n", + resource->start); + return -EFAULT; + } + + resource->start = sys_port; + resource->end = sys_port + length; + + return 0; +} + +/* + * update/set the current I/O resource of the designated device node. + * after this calling, the enumeration can be started as the I/O resource + * had been translated to logicial I/O from bus-local I/O. + * + * @child: the device node to be updated the I/O resource; + * @hostdev: the device node where 'adev' is attached, which can be not + * the parent of 'adev'; + * @res: double pointer to be set to the address of the updated resources + * @num_res: address of the variable to contain the number of updated resources + * + * return 0 when successful, negative is for failure. + */ +int acpi_indirectio_set_logicio_res(struct device *child, + struct device *hostdev, + const struct resource **res, + int *num_res) +{ + struct acpi_device *adev; + struct acpi_device *host; + struct resource_entry *rentry; + LIST_HEAD(resource_list); + struct resource *resources = NULL; + int count; + int i; + int ret = -EIO; + + if (!child || !hostdev) + return -EINVAL; + + host = to_acpi_device(hostdev); + adev = to_acpi_device(child); + + /* check the device state */ + if (!adev->status.present) { + dev_info(child, "ACPI: device is not present!\n"); + return 0; + } + /* whether the child had been enumerated? */ + if (acpi_device_enumerated(adev)) { + dev_info(child, "ACPI: had been enumerated!\n"); + return 0; + } + + count = acpi_dev_get_resources(adev, &resource_list, NULL, NULL); + if (count <= 0) { + dev_err(&adev->dev, "failed to get ACPI resources\n"); + return count ? count : -EIO; + } + + resources = kcalloc(count, sizeof(struct resource), GFP_KERNEL); + if (!resources) { + acpi_dev_free_resource_list(&resource_list); + return -ENOMEM; + } + count = 0; + list_for_each_entry(rentry, &resource_list, node) + resources[count++] = *rentry->res; + + acpi_dev_free_resource_list(&resource_list); + + /* translate the I/O resources */ + for (i = 0; i < count; i++) { + if (resources[i].flags & IORESOURCE_IO) { + ret = acpi_translate_logicio_res(adev, host, + &resources[i]); + if (ret) { + kfree(resources); + dev_err(child, + "Translate I/O range failed (%d)!\n", + ret); + return ret; + } + } + } + *res = resources; + *num_res = count; + + return ret; +} + +int +acpi_indirectio_pre_setup(struct acpi_device *adev, + struct acpi_indirectio_host_data *pdata) +{ + struct platform_device *pdev; + struct mfd_cell *mfd_cells; + struct logic_pio_hwaddr *range; + struct acpi_device *child; + struct acpi_indirectio_mfd_cell *acpi_indirectio_mfd_cells; + int size, ret, count = 0, cell_num = 0; + + range = kzalloc(sizeof(*range), GFP_KERNEL); + if (!range) + return -ENOMEM; + range->fwnode = &adev->fwnode; + range->flags = PIO_INDIRECT; + range->size = pdata->io_size; + range->hw_start = pdata->io_start; + + ret = logic_pio_register_range(range); + if (ret) + goto free_range; + + list_for_each_entry(child, &adev->children, node) + cell_num++; + + /* allocate the mfd cells */ + size = sizeof(*mfd_cells) + sizeof(*acpi_indirectio_mfd_cells); + mfd_cells = kcalloc(cell_num, size, GFP_KERNEL); + if (!mfd_cells) { + ret = -ENOMEM; + goto free_range; + } + + acpi_indirectio_mfd_cells = (struct acpi_indirectio_mfd_cell *) + &mfd_cells[cell_num]; + /* Only consider the children of the host */ + list_for_each_entry(child, &adev->children, node) { + struct mfd_cell *mfd_cell = &mfd_cells[count]; + struct acpi_indirectio_mfd_cell *acpi_indirectio_mfd_cell = + &acpi_indirectio_mfd_cells[count]; + const struct mfd_cell_acpi_match *acpi_match = + &acpi_indirectio_mfd_cell->acpi_match; + char *name = &acpi_indirectio_mfd_cell[count].name[0]; + char *pnpid = &acpi_indirectio_mfd_cell[count].pnpid[0]; + struct mfd_cell_acpi_match match = { + .pnpid = pnpid, + }; + + snprintf(name, ACPI_INDIRECTIO_NAME_LENGTH, "indirect-io-%s", + acpi_device_hid(child)); + snprintf(pnpid, ACPI_INDIRECTIO_NAME_LENGTH, "%s", + acpi_device_hid(child)); + + memcpy((void *)acpi_match, (void *)&match, sizeof(*acpi_match)); + mfd_cell->name = name; + mfd_cell->acpi_match = acpi_match; + + ret = + acpi_indirectio_set_logicio_res(&child->dev, + &adev->dev, + &mfd_cell->resources, + &mfd_cell->num_resources); + if (ret) { + dev_err(&child->dev, "set resource failed (%d)\n", ret); + goto free_mfd_res; + } + count++; + } + + pdev = acpi_create_platform_device(adev, NULL); + if (IS_ERR_OR_NULL(pdev)) { + dev_err(&adev->dev, "Create platform device for host failed!\n"); + ret = PTR_ERR(pdev); + goto free_mfd_res; + } + acpi_device_set_enumerated(adev); + + ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, + mfd_cells, cell_num, NULL, 0, NULL); + if (ret) { + dev_err(&pdev->dev, "failed to add mfd cells (%d)\n", ret); + goto free_mfd_res; + } + + return ret; + +free_mfd_res: + while (cell_num--) + kfree(mfd_cells[cell_num].resources); + kfree(mfd_cells); +free_range: + kfree(range); + + return ret; +} + +/* All the host devices which apply indirect-IO can be listed here. */ +static const struct acpi_device_id acpi_indirect_host_id[] = { + {""}, +}; + +static int acpi_indirectio_attach(struct acpi_device *adev, + const struct acpi_device_id *id) +{ + struct acpi_indirectio_device_desc *hostdata; + int ret; + + hostdata = (struct acpi_indirectio_device_desc *)id->driver_data; + if (!hostdata || !hostdata->pre_setup) + return -EINVAL; + + ret = hostdata->pre_setup(adev, &hostdata->pdata); + + if (ret < 0) + return ret; + + return 1; +} + +static struct acpi_scan_handler acpi_indirect_handler = { + .ids = acpi_indirect_host_id, + .attach = acpi_indirectio_attach, +}; + +void __init acpi_indirectio_scan_init(void) +{ + acpi_scan_add_handler(&acpi_indirect_handler); +} diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h index 1d0a501..d6b1a95 100644 --- a/drivers/acpi/internal.h +++ b/drivers/acpi/internal.h @@ -31,6 +31,11 @@ void acpi_platform_init(void); void acpi_pnp_init(void); void acpi_int340x_thermal_init(void); +#ifdef CONFIG_INDIRECT_PIO +void acpi_indirectio_scan_init(void); +#else +static inline void acpi_indirectio_scan_init(void) {} +#endif #ifdef CONFIG_ARM_AMBA void acpi_amba_init(void); #else diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index b0fe527..8ea6f69 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -2141,6 +2141,7 @@ int __init acpi_scan_init(void) acpi_amba_init(); acpi_watchdog_init(); acpi_init_lpit(); + acpi_indirectio_scan_init(); acpi_scan_add_handler(&generic_device_handler); From patchwork Sun Jan 21 12:27:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 125281 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp655552ljf; Sun, 21 Jan 2018 03:38:29 -0800 (PST) X-Google-Smtp-Source: AH8x2247Sd9I1/LUQ+Du/gOiGBcjILkWGghz8xv0zLqk3FkfnKDsu6gf8yX/2ARkG55rdfFu18wi X-Received: by 10.101.90.71 with SMTP id z7mr4364504pgs.15.1516534709050; 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[209.132.180.67]) by mx.google.com with ESMTP id z10si11906948pgv.473.2018.01.21.03.38.28; Sun, 21 Jan 2018 03:38:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751415AbeAULh5 (ORCPT + 28 others); Sun, 21 Jan 2018 06:37:57 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:50635 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751178AbeAULgV (ORCPT ); Sun, 21 Jan 2018 06:36:21 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 26F7AEE451622; Sun, 21 Jan 2018 19:36:16 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.361.1; Sun, 21 Jan 2018 19:36:07 +0800 From: John Garry To: , , , , , , , , , , CC: , , , , , , , , John Garry , "Zhichang Yuan" , Gabriele Paoloni Subject: [PATCH v11 8/9] LPC, ACPI: Add the HISI LPC ACPI support Date: Sun, 21 Jan 2018 20:27:26 +0800 Message-ID: <1516537647-50553-9-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516537647-50553-1-git-send-email-john.garry@huawei.com> References: <1516537647-50553-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Based on the previous patches, this patch supports the LPC host on Hip06/Hip07 for ACPI FW. Signed-off-by: John Garry Signed-off-by: Zhichang Yuan Signed-off-by: Gabriele Paoloni Tested-by: dann frazier --- drivers/acpi/arm64/acpi_indirectio.c | 11 ++++++++++- drivers/bus/hisi_lpc.c | 17 ++++++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/drivers/acpi/arm64/acpi_indirectio.c b/drivers/acpi/arm64/acpi_indirectio.c index 2649f57..6403f84 100644 --- a/drivers/acpi/arm64/acpi_indirectio.c +++ b/drivers/acpi/arm64/acpi_indirectio.c @@ -142,7 +142,7 @@ int acpi_indirectio_set_logicio_res(struct device *child, return ret; } -int +static int acpi_indirectio_pre_setup(struct acpi_device *adev, struct acpi_indirectio_host_data *pdata) { @@ -239,8 +239,17 @@ int acpi_indirectio_set_logicio_res(struct device *child, return ret; } +const struct acpi_indirectio_device_desc hisi_lpc_host_desc = { + .pdata = { + .io_size = PIO_INDIRECT_SIZE, + .io_start = 0, + }, + .pre_setup = acpi_indirectio_pre_setup, +}; + /* All the host devices which apply indirect-IO can be listed here. */ static const struct acpi_device_id acpi_indirect_host_id[] = { + {"HISI0191", INDIRECT_IO_INFO(hisi_lpc_host_desc)}, {""}, }; diff --git a/drivers/bus/hisi_lpc.c b/drivers/bus/hisi_lpc.c index 4ce089a..9cabb84 100644 --- a/drivers/bus/hisi_lpc.c +++ b/drivers/bus/hisi_lpc.c @@ -457,7 +457,13 @@ static int hisilpc_probe(struct platform_device *pdev) } /* register the LPC host PIO resources */ - { + if (has_acpi_companion(dev)) { + lpcdev->io_host = find_io_range_by_fwnode(dev->fwnode); + if (!lpcdev->io_host) { + dev_err(dev, "range not registered!\n"); + return -EFAULT; + } + } else { struct logic_pio_hwaddr *range; range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL); @@ -515,10 +521,19 @@ static int hisilpc_probe(struct platform_device *pdev) {}, }; +#ifdef CONFIG_ACPI +static const struct acpi_device_id hisilpc_acpi_match[] = { + {"HISI0191", }, + {}, +}; + +#endif + static struct platform_driver hisilpc_driver = { .driver = { .name = "hisi_lpc", .of_match_table = hisilpc_of_match, + .acpi_match_table = ACPI_PTR(hisilpc_acpi_match), }, .probe = hisilpc_probe, }; From patchwork Sun Jan 21 12:27:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 125276 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp654992ljf; Sun, 21 Jan 2018 03:36:38 -0800 (PST) X-Google-Smtp-Source: AH8x225a+dgx3uLc6CNb41IU0uPGR/qwRQZdu0cIbS5S3N1wy9m9HLE+H3F/K6hwMuBO6z4SUT5V X-Received: by 10.101.96.207 with SMTP id r15mr4335323pgv.139.1516534598436; Sun, 21 Jan 2018 03:36:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516534598; cv=none; d=google.com; s=arc-20160816; b=Yc/yGsLhghRMHmVQXXk42eZpbT02iIJoVrk9nJOwu4QEpBXSunSFgk/8UoZfjqLDkA 7kYkhbj4XTyhrjxz4BA8a4CAIaCWAKynnwijKiBZjDLZALMHZLfWE8EqoH+1qZUPOQtm yNfrEG3Ipx/CkdBJxSmtQULnYS9GXc2CPuObUVEGSSmcrTi8q2WqNNvsSFqqOXoO1GXV WWtyI3qYKC4/bT8rAaDvNmB6+6WhXYjGrSGlHAB9g2g1lUo2vcL2yz8SJWf5D9zih6xi m+B+usrnT2VwLYrO0hvd+bFKiPT5336Zodytql3gL/UDSURbyhKj+p9MeyPudJPigLXn WugA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=rgYP1zpzp0EyAFY2LJxOJWNw2wh5qE8wpJbehDTYRZg=; b=teCmQSVLnx1bovb4BXuM/BSu6LnQDsqAZXKYsp74ddPtYp6XJTO0nhkHRR5YoqgrcD RW28HJZEct6CHaWa0Kd84lEpUnyHjrF0bZzjvlZofoLHxsWbXrTdD/aHgXWrv5MHaDns kCH6c5fAWIV47gt770pg0qcwZCOIG6D1+Q13ZGeMTfXhZhSi1fZVzWnhSJyuj5PEs5pi VqzeECe4mRYoqfPzVVXwZB/73zU6WJctTKzUi5THr3YTvr1eIocUXqmWv1r3gSNNAwQC nAHtKLEYcrmg2qnfF5ae/u7aie3P8b86b7R9bfR4yS0ABkCDySBURCfK8wWn7nsHmEKH LlBA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s62si12144454pgb.333.2018.01.21.03.36.38; Sun, 21 Jan 2018 03:36:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751333AbeAULgg (ORCPT + 28 others); Sun, 21 Jan 2018 06:36:36 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:4261 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751150AbeAULgd (ORCPT ); Sun, 21 Jan 2018 06:36:33 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C3E0B241AC390; Sun, 21 Jan 2018 19:36:15 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.361.1; Sun, 21 Jan 2018 19:36:08 +0800 From: John Garry To: , , , , , , , , , , CC: , , , , , , , , John Garry Subject: [PATCH v11 9/9] MAINTAINERS: Add maintainer for HiSilicon LPC driver Date: Sun, 21 Jan 2018 20:27:27 +0800 Message-ID: <1516537647-50553-10-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516537647-50553-1-git-send-email-john.garry@huawei.com> References: <1516537647-50553-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Added maintainer for drivers/bus/hisi_lpc.c Signed-off-by: John Garry --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) -- 1.9.1 diff --git a/MAINTAINERS b/MAINTAINERS index f1e3ee6..ab09908 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6386,6 +6386,13 @@ W: http://www.hisilicon.com S: Maintained F: drivers/net/ethernet/hisilicon/hns3/ +HISILICON LPC BUS DRIVER +M: john.garry@huawei.com +W: http://www.hisilicon.com +S: Maintained +F: drivers/bus/hisi_lpc.c +F: Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt + HISILICON NETWORK SUBSYSTEM DRIVER M: Yisen Zhuang M: Salil Mehta