From patchwork Wed Nov 25 07:19:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 332503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC34EC64E7C for ; Wed, 25 Nov 2020 07:19:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B71420B80 for ; Wed, 25 Nov 2020 07:19:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728079AbgKYHTl (ORCPT ); Wed, 25 Nov 2020 02:19:41 -0500 Received: from relay1-d.mail.gandi.net ([217.70.183.193]:12287 "EHLO relay1-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728036AbgKYHTl (ORCPT ); Wed, 25 Nov 2020 02:19:41 -0500 X-Originating-IP: 91.175.115.186 Received: from localhost (91-175-115-186.subs.proxad.net [91.175.115.186]) (Authenticated sender: gregory.clement@bootlin.com) by relay1-d.mail.gandi.net (Postfix) with ESMTPSA id 80E1C24000A; Wed, 25 Nov 2020 07:19:38 +0000 (UTC) From: Gregory CLEMENT To: Sebastian Reichel , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Thomas Petazzoni , Alexandre Belloni , Lars Povlsen , , Gregory CLEMENT Subject: [PATCH v2 3/3] MIPS: dts: mscc: add reset support for Luton and Jaguar2 Date: Wed, 25 Nov 2020 08:19:20 +0100 Message-Id: <20201125071920.126978-4-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125071920.126978-1-gregory.clement@bootlin.com> References: <20201125071920.126978-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow Luton and Jaguar2 SoCs to use reset feature by adding the reset node. Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/mscc/jaguar2.dtsi | 5 +++++ arch/mips/boot/dts/mscc/luton.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/mips/boot/dts/mscc/jaguar2.dtsi b/arch/mips/boot/dts/mscc/jaguar2.dtsi index 42b2b0a51ddc..7032fe550277 100644 --- a/arch/mips/boot/dts/mscc/jaguar2.dtsi +++ b/arch/mips/boot/dts/mscc/jaguar2.dtsi @@ -60,6 +60,11 @@ cpu_ctrl: syscon@70000000 { reg = <0x70000000 0x2c>; }; + reset@71010008 { + compatible = "mscc,jaguar2-chip-reset"; + reg = <0x71010008 0x4>; + }; + intc: interrupt-controller@70000070 { compatible = "mscc,jaguar2-icpu-intr"; reg = <0x70000070 0x94>; diff --git a/arch/mips/boot/dts/mscc/luton.dtsi b/arch/mips/boot/dts/mscc/luton.dtsi index 2a170b84c5a9..4a26c2874386 100644 --- a/arch/mips/boot/dts/mscc/luton.dtsi +++ b/arch/mips/boot/dts/mscc/luton.dtsi @@ -56,6 +56,11 @@ cpu_ctrl: syscon@10000000 { reg = <0x10000000 0x2c>; }; + reset@00070090 { + compatible = "mscc,luton-chip-reset"; + reg = <0x70090 0x4>; + }; + intc: interrupt-controller@10000084 { compatible = "mscc,luton-icpu-intr"; reg = <0x10000084 0x70>;