From patchwork Tue Mar 21 15:36:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 95643 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1527770qgd; Tue, 21 Mar 2017 09:31:43 -0700 (PDT) X-Received: by 10.84.218.2 with SMTP id q2mr34443569pli.141.1490113902998; Tue, 21 Mar 2017 09:31:42 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t188si4000601pgt.331.2017.03.21.09.31.42; Tue, 21 Mar 2017 09:31:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932635AbdCUPgn (ORCPT + 19 others); Tue, 21 Mar 2017 11:36:43 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60395 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757929AbdCUPgg (ORCPT ); Tue, 21 Mar 2017 11:36:36 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id C3E5B207CF; Tue, 21 Mar 2017 16:36:34 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 6676B207CC; Tue, 21 Mar 2017 16:36:34 +0100 (CET) From: Quentin Schulz To: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, lee.jones@linaro.org, linux@armlinux.org.uk, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: Quentin Schulz , thomas.petazzoni@free-electrons.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.xyz Subject: [PATCH v3 01/11] ARM: sun8i: a33: add operating-points-v2 property to all nodes Date: Tue, 21 Mar 2017 16:36:01 +0100 Message-Id: <20170321153611.16228-2-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170321153611.16228-1-quentin.schulz@free-electrons.com> References: <20170321153611.16228-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The OPP are declared as shared but no operating points are declared for cpu1, 2 and 3. Thus, the following error happens during the boot: cpu cpu1: dev_pm_opp_of_get_sharing_cpus: Couldn't find tcpu_dev node. This patch applies the operating points to each cpu of the A33. Signed-off-by: Quentin Schulz --- added in v2 arch/arm/boot/dts/sun8i-a33.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.9.3 Acked-by: Chen-Yu Tsai diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index e1e74b8..39b2d78 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -75,16 +75,22 @@ operating-points-v2 = <&cpu0_opp_table>; }; + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + operating-points-v2 = <&cpu0_opp_table>; }; }; From patchwork Tue Mar 21 15:36:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 95656 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1536846qgd; Tue, 21 Mar 2017 09:53:46 -0700 (PDT) X-Received: by 10.98.216.202 with SMTP id e193mr40805666pfg.80.1490115226148; Tue, 21 Mar 2017 09:53:46 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 2si21914445pgi.1.2017.03.21.09.53.45; Tue, 21 Mar 2017 09:53:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758145AbdCUPgm (ORCPT + 19 others); Tue, 21 Mar 2017 11:36:42 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60414 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757931AbdCUPgh (ORCPT ); Tue, 21 Mar 2017 11:36:37 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 341E620B76; Tue, 21 Mar 2017 16:36:35 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id C4EB3207CC; Tue, 21 Mar 2017 16:36:34 +0100 (CET) From: Quentin Schulz To: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, lee.jones@linaro.org, linux@armlinux.org.uk, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: Quentin Schulz , thomas.petazzoni@free-electrons.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.xyz Subject: [PATCH v3 02/11] ARM: sun8i: a33: add all operating points Date: Tue, 21 Mar 2017 16:36:02 +0100 Message-Id: <20170321153611.16228-3-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170321153611.16228-1-quentin.schulz@free-electrons.com> References: <20170321153611.16228-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds almost all operating points allowed for the A33 as defined by fex files available at: https://github.com/linux-sunxi/sunxi-boards/tree/master/sys_config/a33 There are more possible frequencies in this patch than there are in the fex files because the fex files only give an interval of possible frequencies for a given voltage. All supported frequencies are defined in the original driver code in Allwinner vendor tree. There are two missing frequencies though: 1104MHz and 1200MHz which require the CPU to have 1.32V supplied, which is higher than the default voltage. Without all A33 boards defining the CPU regulator, we cannot have these two frequencies as it would cause the CPU to try to run a higher frequency without "overvolting" which is very likely to crash the CPU. Therefore, these two frequencies must be enabled on a per-board basis. Signed-off-by: Quentin Schulz --- v2: - updated commit log, - removed 1.1GHz as it requires overvolting the CPU which need the CPU regulator to be set which is set on a per-board basis, arch/arm/boot/dts/sun8i-a33.dtsi | 54 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) -- 2.9.3 Acked-by: Chen-Yu Tsai diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 39b2d78..b1cdff66 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -49,18 +49,72 @@ compatible = "operating-points-v2"; opp-shared; + opp@120000000 { + opp-hz = /bits/ 64 <120000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@240000000 { + opp-hz = /bits/ 64 <240000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + opp@648000000 { opp-hz = /bits/ 64 <648000000>; opp-microvolt = <1040000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; + opp@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + opp@816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; + opp@912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + opp@1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000>; From patchwork Tue Mar 21 15:36:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 95636 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1503851qgd; Tue, 21 Mar 2017 08:39:54 -0700 (PDT) X-Received: by 10.84.233.199 with SMTP id m7mr3774906pln.25.1490110794392; Tue, 21 Mar 2017 08:39:54 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 68si2990676pga.325.2017.03.21.08.39.54; Tue, 21 Mar 2017 08:39:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932820AbdCUPgo (ORCPT + 19 others); Tue, 21 Mar 2017 11:36:44 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60442 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757976AbdCUPgi (ORCPT ); Tue, 21 Mar 2017 11:36:38 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id E2BDE20F68; Tue, 21 Mar 2017 16:36:35 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 8535120F4D; Tue, 21 Mar 2017 16:36:35 +0100 (CET) From: Quentin Schulz To: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, lee.jones@linaro.org, linux@armlinux.org.uk, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: Quentin Schulz , thomas.petazzoni@free-electrons.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.xyz Subject: [PATCH v3 04/11] Documentation: DT: bindings: mfd: add A33 GPADC binding Date: Tue, 21 Mar 2017 16:36:04 +0100 Message-Id: <20170321153611.16228-5-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170321153611.16228-1-quentin.schulz@free-electrons.com> References: <20170321153611.16228-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds documentation for the A33 GPADC binding. Signed-off-by: Quentin Schulz --- v3: - fixed missing allwinner in front of compatible, - updated compatible to allwinner,sun8i-a33-ths to better reflect the datasheet's name, - updated example's DT node name and label to ths, added in v2 .../devicetree/bindings/mfd/sun4i-gpadc.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt -- 2.9.3 Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt new file mode 100644 index 0000000..badff36 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt @@ -0,0 +1,59 @@ +Allwinner SoCs' GPADC Device Tree bindings +------------------------------------------ +The Allwinner SoCs all have an ADC that can also act as a thermal sensor +and sometimes as a touchscreen controller. + +Required properties: + - compatible: "allwinner,sun8i-a33-ths", + - reg: mmio address range of the chip, + - #thermal-sensor-cells: shall be 0, + - #io-channel-cells: shall be 0, + +Example: + ths: ths@01c25000 { + compatible = "allwinner,sun8i-a33-ths"; + reg = <0x01c25000 0x100>; + #thermal-sensor-cells = <0>; + #io-channel-cells = <0>; + }; + +sun4i, sun5i and sun6i SoCs are also supported via the older binding: + +sun4i resistive touchscreen controller +-------------------------------------- + +Required properties: + - compatible: "allwinner,sun4i-a10-ts", "allwinner,sun5i-a13-ts" or + "allwinner,sun6i-a31-ts" + - reg: mmio address range of the chip + - interrupts: interrupt to which the chip is connected + - #thermal-sensor-cells: shall be 0 + +Optional properties: + - allwinner,ts-attached : boolean indicating that an actual touchscreen + is attached to the controller + - allwinner,tp-sensitive-adjust : integer (4 bits) + adjust sensitivity of pen down detection + between 0 (least sensitive) and 15 + (defaults to 15) + - allwinner,filter-type : integer (2 bits) + select median and averaging filter + samples used for median / averaging filter + 0: 4/2 + 1: 5/3 + 2: 8/4 + 3: 16/8 + (defaults to 1) + +Example: + + rtp: rtp@01c25000 { + compatible = "allwinner,sun4i-a10-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + allwinner,ts-attached; + #thermal-sensor-cells = <0>; + /* sensitive/noisy touch panel */ + allwinner,tp-sensitive-adjust = <0>; + allwinner,filter-type = <3>; + }; From patchwork Tue Mar 21 15:36:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 95637 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1507558qgd; Tue, 21 Mar 2017 08:48:16 -0700 (PDT) X-Received: by 10.98.67.157 with SMTP id l29mr40976043pfi.251.1490111296349; Tue, 21 Mar 2017 08:48:16 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q12si21698831pli.218.2017.03.21.08.48.15; Tue, 21 Mar 2017 08:48:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757574AbdCUPqK (ORCPT + 19 others); Tue, 21 Mar 2017 11:46:10 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60479 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932589AbdCUPgn (ORCPT ); Tue, 21 Mar 2017 11:36:43 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 41E7520F6A; Tue, 21 Mar 2017 16:36:36 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id DBEE120713; Tue, 21 Mar 2017 16:36:35 +0100 (CET) From: Quentin Schulz To: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, lee.jones@linaro.org, linux@armlinux.org.uk, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: Quentin Schulz , thomas.petazzoni@free-electrons.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.xyz Subject: [PATCH v3 05/11] Documentation: DT: bindings: input: touschcreen: remove sun4i documentation Date: Tue, 21 Mar 2017 16:36:05 +0100 Message-Id: <20170321153611.16228-6-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170321153611.16228-1-quentin.schulz@free-electrons.com> References: <20170321153611.16228-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch removes the sun4i touchscreen controller binding documentation since it has been merged with the sun4i GPADC binding documentation. Signed-off-by: Quentin Schulz Acked-by: Rob Herring --- added in v2 .../bindings/input/touchscreen/sun4i.txt | 38 ---------------------- 1 file changed, 38 deletions(-) delete mode 100644 Documentation/devicetree/bindings/input/touchscreen/sun4i.txt -- 2.9.3 diff --git a/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt b/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt deleted file mode 100644 index 89abecd..0000000 --- a/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt +++ /dev/null @@ -1,38 +0,0 @@ -sun4i resistive touchscreen controller --------------------------------------- - -Required properties: - - compatible: "allwinner,sun4i-a10-ts", "allwinner,sun5i-a13-ts" or - "allwinner,sun6i-a31-ts" - - reg: mmio address range of the chip - - interrupts: interrupt to which the chip is connected - - #thermal-sensor-cells: shall be 0 - -Optional properties: - - allwinner,ts-attached : boolean indicating that an actual touchscreen - is attached to the controller - - allwinner,tp-sensitive-adjust : integer (4 bits) - adjust sensitivity of pen down detection - between 0 (least sensitive) and 15 - (defaults to 15) - - allwinner,filter-type : integer (2 bits) - select median and averaging filter - samples used for median / averaging filter - 0: 4/2 - 1: 5/3 - 2: 8/4 - 3: 16/8 - (defaults to 1) - -Example: - - rtp: rtp@01c25000 { - compatible = "allwinner,sun4i-a10-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - allwinner,ts-attached; - #thermal-sensor-cells = <0>; - /* sensitive/noisy touch panel */ - allwinner,tp-sensitive-adjust = <0>; - allwinner,filter-type = <3>; - }; From patchwork Tue Mar 21 15:36:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 95673 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1600930qgd; Tue, 21 Mar 2017 12:33:27 -0700 (PDT) X-Received: by 10.99.121.195 with SMTP id u186mr39271310pgc.96.1490124807008; Tue, 21 Mar 2017 12:33:27 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s3si22210102pgn.55.2017.03.21.12.33.26; Tue, 21 Mar 2017 12:33:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934032AbdCUT3f (ORCPT + 17 others); Tue, 21 Mar 2017 15:29:35 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60480 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757985AbdCUPgi (ORCPT ); Tue, 21 Mar 2017 11:36:38 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id A86A120713; Tue, 21 Mar 2017 16:36:36 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 440A420713; Tue, 21 Mar 2017 16:36:36 +0100 (CET) From: Quentin Schulz To: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, lee.jones@linaro.org, linux@armlinux.org.uk, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: Quentin Schulz , thomas.petazzoni@free-electrons.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.xyz Subject: [PATCH v3 06/11] iio: adc: sun4i-gpadc-iio: move code used in MFD probing to new function Date: Tue, 21 Mar 2017 16:36:06 +0100 Message-Id: <20170321153611.16228-7-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170321153611.16228-1-quentin.schulz@free-electrons.com> References: <20170321153611.16228-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This moves code used in MFD probing to a new sun4i_gpadc_probe_mfd function. This driver was initially written for A10, A13 and A31 SoCs which already had a DT binding for this IP, thus we needed to use an MFD to probe the different drivers without changing the DT binding of these SoCs. For SoCs that will require to create a DT binding for this IP, we can avoid using an MFD, thus we need two separate functions: one for probing via MFD and one for probing without MFD. This split the code specific to MFD probing in a function separated from the driver probe function. Signed-off-by: Quentin Schulz Acked-by: Jonathan Cameron --- v3: - updated commit log, added in v2 drivers/iio/adc/sun4i-gpadc-iio.c | 78 ++++++++++++++++++++++----------------- 1 file changed, 45 insertions(+), 33 deletions(-) -- 2.9.3 diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c index a8e134f..7cb997a 100644 --- a/drivers/iio/adc/sun4i-gpadc-iio.c +++ b/drivers/iio/adc/sun4i-gpadc-iio.c @@ -454,31 +454,16 @@ static int sun4i_irq_init(struct platform_device *pdev, const char *name, return 0; } -static int sun4i_gpadc_probe(struct platform_device *pdev) +static int sun4i_gpadc_probe_mfd(struct platform_device *pdev, + struct iio_dev *indio_dev) { - struct sun4i_gpadc_iio *info; - struct iio_dev *indio_dev; + struct sun4i_gpadc_iio *info = iio_priv(indio_dev); + struct sun4i_gpadc_dev *sun4i_gpadc_dev = + dev_get_drvdata(pdev->dev.parent); int ret; - struct sun4i_gpadc_dev *sun4i_gpadc_dev; - - sun4i_gpadc_dev = dev_get_drvdata(pdev->dev.parent); - - indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); - if (!indio_dev) - return -ENOMEM; - info = iio_priv(indio_dev); - platform_set_drvdata(pdev, indio_dev); - - mutex_init(&info->mutex); info->regmap = sun4i_gpadc_dev->regmap; - info->indio_dev = indio_dev; - init_completion(&info->completion); - indio_dev->name = dev_name(&pdev->dev); - indio_dev->dev.parent = &pdev->dev; - indio_dev->dev.of_node = pdev->dev.of_node; - indio_dev->info = &sun4i_gpadc_iio_info; - indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->num_channels = ARRAY_SIZE(sun4i_gpadc_channels); indio_dev->channels = sun4i_gpadc_channels; @@ -519,8 +504,7 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) dev_err(&pdev->dev, "could not register thermal sensor: %ld\n", PTR_ERR(tzd)); - ret = PTR_ERR(tzd); - goto err; + return PTR_ERR(tzd); } } else { indio_dev->num_channels = @@ -528,36 +512,65 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) indio_dev->channels = sun4i_gpadc_channels_no_temp; } - pm_runtime_set_autosuspend_delay(&pdev->dev, - SUN4I_GPADC_AUTOSUSPEND_DELAY); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_set_suspended(&pdev->dev); - pm_runtime_enable(&pdev->dev); - if (IS_ENABLED(CONFIG_THERMAL_OF)) { ret = sun4i_irq_init(pdev, "TEMP_DATA_PENDING", sun4i_gpadc_temp_data_irq_handler, "temp_data", &info->temp_data_irq, &info->ignore_temp_data_irq); if (ret < 0) - goto err; + return ret; } ret = sun4i_irq_init(pdev, "FIFO_DATA_PENDING", sun4i_gpadc_fifo_data_irq_handler, "fifo_data", &info->fifo_data_irq, &info->ignore_fifo_data_irq); if (ret < 0) - goto err; + return ret; if (IS_ENABLED(CONFIG_THERMAL_OF)) { ret = iio_map_array_register(indio_dev, sun4i_gpadc_hwmon_maps); if (ret < 0) { dev_err(&pdev->dev, "failed to register iio map array\n"); - goto err; + return ret; } } + return 0; +} + +static int sun4i_gpadc_probe(struct platform_device *pdev) +{ + struct sun4i_gpadc_iio *info; + struct iio_dev *indio_dev; + int ret; + + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); + if (!indio_dev) + return -ENOMEM; + + info = iio_priv(indio_dev); + platform_set_drvdata(pdev, indio_dev); + + mutex_init(&info->mutex); + info->indio_dev = indio_dev; + init_completion(&info->completion); + indio_dev->name = dev_name(&pdev->dev); + indio_dev->dev.parent = &pdev->dev; + indio_dev->dev.of_node = pdev->dev.of_node; + indio_dev->info = &sun4i_gpadc_iio_info; + indio_dev->modes = INDIO_DIRECT_MODE; + + ret = sun4i_gpadc_probe_mfd(pdev, indio_dev); + if (ret) + return ret; + + pm_runtime_set_autosuspend_delay(&pdev->dev, + SUN4I_GPADC_AUTOSUSPEND_DELAY); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + pm_runtime_enable(&pdev->dev); + ret = devm_iio_device_register(&pdev->dev, indio_dev); if (ret < 0) { dev_err(&pdev->dev, "could not register the device\n"); @@ -570,7 +583,6 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) if (IS_ENABLED(CONFIG_THERMAL_OF)) iio_map_array_unregister(indio_dev); -err: pm_runtime_put(&pdev->dev); pm_runtime_disable(&pdev->dev); From patchwork Tue Mar 21 15:36:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 95671 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1590868qgd; Tue, 21 Mar 2017 12:06:34 -0700 (PDT) X-Received: by 10.98.207.68 with SMTP id b65mr41490064pfg.12.1490123194255; Tue, 21 Mar 2017 12:06:34 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s11si17550553pgc.164.2017.03.21.12.06.33; Tue, 21 Mar 2017 12:06:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758001AbdCUTDO (ORCPT + 17 others); Tue, 21 Mar 2017 15:03:14 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60492 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757987AbdCUPgj (ORCPT ); Tue, 21 Mar 2017 11:36:39 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 0ED3B21021; Tue, 21 Mar 2017 16:36:37 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 9D5F620F78; Tue, 21 Mar 2017 16:36:36 +0100 (CET) From: Quentin Schulz To: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, lee.jones@linaro.org, linux@armlinux.org.uk, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: Quentin Schulz , thomas.petazzoni@free-electrons.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.xyz Subject: [PATCH v3 07/11] iio: adc: sun4i-gpadc-iio: add support for A33 thermal sensor Date: Tue, 21 Mar 2017 16:36:07 +0100 Message-Id: <20170321153611.16228-8-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170321153611.16228-1-quentin.schulz@free-electrons.com> References: <20170321153611.16228-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds support for the Allwinner A33 thermal sensor. Unlike the A10, A13 and A31, the Allwinner A33 only has one channel which is dedicated to the thermal sensor. Moreover, its thermal sensor does not generate interruptions, thus we only need to directly read the register storing the temperature value. The MFD used by the A10, A13 and A31, was created to avoid breaking the DT binding, but since the nodes for the ADC weren't there for the A33, it is not needed. Though the A33 does not have an internal ADC, it has a thermal sensor which shares the same registers with GPADC of the already supported SoCs and almost the same bits, for the same purpose (thermal sensor). The thermal sensor behaves exactly the same (except the presence of interrupts or not) on the different SoCs. Signed-off-by: Quentin Schulz Acked-by: Lee Jones --- v3: - switched compatible from allwinner,sun8i-a33-gpadc-iio to allwinner,sun8i-a33-ths to better reflect the datasheet's name, - fixed the non-working if (!IS_ENABLED(THERMAL_OF)) by prefixing it with CONFIG, v2: - removed added comments in Kconfig, - simplified Kconfig depends on condition, - removed THERMAL_OF requirement for sun8i, - renamed sun8i_gpadc_channels to sun8i_a33_gpadc_channels, - renamed use_dt boolean in no_irq as it reflects better why we need it, - removed spurious/unneeded modifications done in v1, drivers/iio/adc/Kconfig | 2 +- drivers/iio/adc/sun4i-gpadc-iio.c | 100 ++++++++++++++++++++++++++++++++++++-- include/linux/mfd/sun4i-gpadc.h | 4 ++ 3 files changed, 102 insertions(+), 4 deletions(-) -- 2.9.3 diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 9f8b4b1..8c8ead6 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -562,7 +562,7 @@ config STX104 config SUN4I_GPADC tristate "Support for the Allwinner SoCs GPADC" depends on IIO - depends on MFD_SUN4I_GPADC + depends on MFD_SUN4I_GPADC || MACH_SUN8I help Say yes here to build support for Allwinner (A10, A13 and A31) SoCs GPADC. This ADC provides 4 channels which can be used as an ADC or as diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c index 7cb997a..74705aa 100644 --- a/drivers/iio/adc/sun4i-gpadc-iio.c +++ b/drivers/iio/adc/sun4i-gpadc-iio.c @@ -85,6 +85,12 @@ static const struct gpadc_data sun6i_gpadc_data = { .adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK, }; +static const struct gpadc_data sun8i_a33_gpadc_data = { + .temp_offset = -1662, + .temp_scale = 162, + .tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN, +}; + struct sun4i_gpadc_iio { struct iio_dev *indio_dev; struct completion completion; @@ -96,6 +102,7 @@ struct sun4i_gpadc_iio { unsigned int temp_data_irq; atomic_t ignore_temp_data_irq; const struct gpadc_data *data; + bool no_irq; /* prevents concurrent reads of temperature and ADC */ struct mutex mutex; }; @@ -138,6 +145,23 @@ static const struct iio_chan_spec sun4i_gpadc_channels_no_temp[] = { SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"), }; +static const struct iio_chan_spec sun8i_a33_gpadc_channels[] = { + { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .datasheet_name = "temp_adc", + }, +}; + +static const struct regmap_config sun4i_gpadc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + static int sun4i_prepare_for_irq(struct iio_dev *indio_dev, int channel, unsigned int irq) { @@ -247,6 +271,17 @@ static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val) { struct sun4i_gpadc_iio *info = iio_priv(indio_dev); + if (info->no_irq) { + pm_runtime_get_sync(indio_dev->dev.parent); + + regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val); + + pm_runtime_mark_last_busy(indio_dev->dev.parent); + pm_runtime_put_autosuspend(indio_dev->dev.parent); + + return 0; + } + return sun4i_gpadc_read(indio_dev, 0, val, info->temp_data_irq); } @@ -454,6 +489,58 @@ static int sun4i_irq_init(struct platform_device *pdev, const char *name, return 0; } +static const struct of_device_id sun4i_gpadc_of_id[] = { + { + .compatible = "allwinner,sun8i-a33-ths", + .data = &sun8i_a33_gpadc_data, + }, + { /* sentinel */ } +}; + +static int sun4i_gpadc_probe_dt(struct platform_device *pdev, + struct iio_dev *indio_dev) +{ + struct sun4i_gpadc_iio *info = iio_priv(indio_dev); + const struct of_device_id *of_dev; + struct thermal_zone_device *tzd; + struct resource *mem; + void __iomem *base; + int ret; + + of_dev = of_match_device(sun4i_gpadc_of_id, &pdev->dev); + if (!of_dev) + return -ENODEV; + + info->no_irq = true; + info->data = (struct gpadc_data *)of_dev->data; + indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels); + indio_dev->channels = sun8i_a33_gpadc_channels; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(base)) + return PTR_ERR(base); + + info->regmap = devm_regmap_init_mmio(&pdev->dev, base, + &sun4i_gpadc_regmap_config); + if (IS_ERR(info->regmap)) { + ret = PTR_ERR(info->regmap); + dev_err(&pdev->dev, "failed to init regmap: %d\n", ret); + return ret; + } + + if (!IS_ENABLED(CONFIG_THERMAL_OF)) + return 0; + + tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, info, + &sun4i_ts_tz_ops); + if (IS_ERR(tzd)) + dev_err(&pdev->dev, "could not register thermal sensor: %ld\n", + PTR_ERR(tzd)); + + return PTR_ERR_OR_ZERO(tzd); +} + static int sun4i_gpadc_probe_mfd(struct platform_device *pdev, struct iio_dev *indio_dev) { @@ -462,6 +549,7 @@ static int sun4i_gpadc_probe_mfd(struct platform_device *pdev, dev_get_drvdata(pdev->dev.parent); int ret; + info->no_irq = false; info->regmap = sun4i_gpadc_dev->regmap; indio_dev->num_channels = ARRAY_SIZE(sun4i_gpadc_channels); @@ -561,7 +649,11 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) indio_dev->info = &sun4i_gpadc_iio_info; indio_dev->modes = INDIO_DIRECT_MODE; - ret = sun4i_gpadc_probe_mfd(pdev, indio_dev); + if (pdev->dev.of_node) + ret = sun4i_gpadc_probe_dt(pdev, indio_dev); + else + ret = sun4i_gpadc_probe_mfd(pdev, indio_dev); + if (ret) return ret; @@ -580,7 +672,7 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) return 0; err_map: - if (IS_ENABLED(CONFIG_THERMAL_OF)) + if (!info->no_irq && IS_ENABLED(CONFIG_THERMAL_OF)) iio_map_array_unregister(indio_dev); pm_runtime_put(&pdev->dev); @@ -592,10 +684,11 @@ static int sun4i_gpadc_probe(struct platform_device *pdev) static int sun4i_gpadc_remove(struct platform_device *pdev) { struct iio_dev *indio_dev = platform_get_drvdata(pdev); + struct sun4i_gpadc_iio *info = iio_priv(indio_dev); pm_runtime_put(&pdev->dev); pm_runtime_disable(&pdev->dev); - if (IS_ENABLED(CONFIG_THERMAL_OF)) + if (!info->no_irq && IS_ENABLED(CONFIG_THERMAL_OF)) iio_map_array_unregister(indio_dev); return 0; @@ -611,6 +704,7 @@ static const struct platform_device_id sun4i_gpadc_id[] = { static struct platform_driver sun4i_gpadc_driver = { .driver = { .name = "sun4i-gpadc-iio", + .of_match_table = sun4i_gpadc_of_id, .pm = &sun4i_gpadc_pm_ops, }, .id_table = sun4i_gpadc_id, diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h index 509e736..139872c 100644 --- a/include/linux/mfd/sun4i-gpadc.h +++ b/include/linux/mfd/sun4i-gpadc.h @@ -38,6 +38,10 @@ #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x)) #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(3, 0) +/* TP_CTRL1 bits for sun8i SoCs */ +#define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN BIT(8) +#define SUN8I_GPADC_CTRL1_GPADC_CALI_EN BIT(7) + #define SUN4I_GPADC_CTRL2 0x08 #define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x) ((GENMASK(3, 0) & (x)) << 28) From patchwork Tue Mar 21 15:36:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 95670 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1580009qgd; Tue, 21 Mar 2017 11:37:57 -0700 (PDT) X-Received: by 10.98.19.156 with SMTP id 28mr40587253pft.208.1490121477126; Tue, 21 Mar 2017 11:37:57 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 21si22167937pgy.201.2017.03.21.11.37.56; Tue, 21 Mar 2017 11:37:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758111AbdCUSed (ORCPT + 18 others); Tue, 21 Mar 2017 14:34:33 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60526 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758011AbdCUPgk (ORCPT ); Tue, 21 Mar 2017 11:36:40 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 1271020F4D; Tue, 21 Mar 2017 16:36:38 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 011A820F7B; Tue, 21 Mar 2017 16:36:36 +0100 (CET) From: Quentin Schulz To: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, lee.jones@linaro.org, linux@armlinux.org.uk, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: Quentin Schulz , thomas.petazzoni@free-electrons.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.xyz Subject: [PATCH v3 08/11] ARM: dtsi: sun8i: a33: add thermal sensor Date: Tue, 21 Mar 2017 16:36:08 +0100 Message-Id: <20170321153611.16228-9-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170321153611.16228-1-quentin.schulz@free-electrons.com> References: <20170321153611.16228-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds the DT node for the thermal sensor present in the Allwinner A33 GPADC. Signed-off-by: Quentin Schulz --- v3: - switched compatible to allwinner,sun8i-a33-ths, - renamed DT node name and label to ths to better match datasheet's name, arch/arm/boot/dts/sun8i-a33.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.9.3 diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index b1cdff66..f391f71 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -266,6 +266,13 @@ status = "disabled"; }; + ths: ths@01c25000 { + compatible = "allwinner,sun8i-a33-ths"; + reg = <0x01c25000 0x100>; + #thermal-sensor-cells = <0>; + #io-channel-cells = <0>; + }; + fe0: display-frontend@01e00000 { compatible = "allwinner,sun8i-a33-display-frontend"; reg = <0x01e00000 0x20000>; @@ -376,6 +383,11 @@ }; }; }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&ths>; + }; }; &ccu { From patchwork Tue Mar 21 15:36:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 95666 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1555727qgd; Tue, 21 Mar 2017 10:38:11 -0700 (PDT) X-Received: by 10.98.159.82 with SMTP id g79mr41450483pfe.189.1490117891492; Tue, 21 Mar 2017 10:38:11 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t6si21953486pgn.178.2017.03.21.10.38.11; Tue, 21 Mar 2017 10:38:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933807AbdCURel (ORCPT + 17 others); Tue, 21 Mar 2017 13:34:41 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60547 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758023AbdCUPgk (ORCPT ); Tue, 21 Mar 2017 11:36:40 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 7E94221D3A; Tue, 21 Mar 2017 16:36:38 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 58B55212EA; Tue, 21 Mar 2017 16:36:37 +0100 (CET) From: Quentin Schulz To: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, lee.jones@linaro.org, linux@armlinux.org.uk, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: Quentin Schulz , thomas.petazzoni@free-electrons.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.xyz Subject: [PATCH v3 09/11] ARM: dtsi: sun8i: a33: add CPU thermal throttling Date: Tue, 21 Mar 2017 16:36:09 +0100 Message-Id: <20170321153611.16228-10-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170321153611.16228-1-quentin.schulz@free-electrons.com> References: <20170321153611.16228-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds CPU thermal throttling for the Allwinner A33. It uses the thermal sensor present in the SoC's GPADC. Signed-off-by: Quentin Schulz --- v3: - switched to new phandle because of modified DT node name for the GPADC (named THS), - got rid of cooling-min-level and cooling-max-level as it's not used in any code in the kernel, v2: - updated cooling-max-level to reflect newly added OPPs, arch/arm/boot/dts/sun8i-a33.dtsi | 45 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.9.3 diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index f391f71..73552bb 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -43,6 +43,7 @@ */ #include "sun8i-a23-a33.dtsi" +#include / { cpu0_opp_table: opp_table0 { @@ -127,6 +128,7 @@ clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@1 { @@ -170,6 +172,49 @@ }; }; + thermal-zones { + cpu_thermal { + /* milliseconds */ + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&ths>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_alert1: cpu_alert1 { + /* milliCelsius */ + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + memory { reg = <0x40000000 0x80000000>; }; From patchwork Tue Mar 21 15:36:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 95667 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1561707qgd; Tue, 21 Mar 2017 10:54:08 -0700 (PDT) X-Received: by 10.84.174.131 with SMTP id r3mr25161976plb.136.1490118848570; Tue, 21 Mar 2017 10:54:08 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g24si15691837pfd.250.2017.03.21.10.54.08; Tue, 21 Mar 2017 10:54:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933790AbdCURek (ORCPT + 17 others); Tue, 21 Mar 2017 13:34:40 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60560 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758038AbdCUPgk (ORCPT ); Tue, 21 Mar 2017 11:36:40 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 933EC212EA; Tue, 21 Mar 2017 16:36:38 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id B5CED212F0; Tue, 21 Mar 2017 16:36:37 +0100 (CET) From: Quentin Schulz To: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, lee.jones@linaro.org, linux@armlinux.org.uk, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: thomas.petazzoni@free-electrons.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.xyz, Quentin Schulz Subject: [PATCH v3 10/11] ARM: sun8i: a33: Add devfreq-based GPU cooling Date: Tue, 21 Mar 2017 16:36:10 +0100 Message-Id: <20170321153611.16228-11-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170321153611.16228-1-quentin.schulz@free-electrons.com> References: <20170321153611.16228-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Maxime Ripard This adds GPU thermal throttling for the Allwinner A33. Signed-off-by: Maxime Ripard Signed-off-by: Quentin Schulz --- v3: - got rid of cooling-min-level and cooling-max-level as it's not used in any code in the kernel, added in v2 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 1 + arch/arm/boot/dts/sun8i-a33.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) -- 2.9.3 diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 5e8725d..6d81a6d 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -495,6 +495,7 @@ assigned-clocks = <&ccu CLK_GPU>; assigned-clock-rates = <384000000>; + #cooling-cells = <2>; }; gic: interrupt-controller@01c81000 { diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 73552bb..a2c6077 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -188,6 +188,16 @@ trip = <&cpu_alert1>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; + + map2 { + trip = <&gpu_alert0>; + cooling-device = <&mali 1 THERMAL_NO_LIMIT>; + }; + + map3 { + trip = <&gpu_alert1>; + cooling-device = <&mali 2 THERMAL_NO_LIMIT>; + }; }; trips { @@ -198,6 +208,13 @@ type = "passive"; }; + gpu_alert0: gpu_alert0 { + /* milliCelsius */ + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_alert1: cpu_alert1 { /* milliCelsius */ temperature = <90000>; @@ -205,6 +222,13 @@ type = "hot"; }; + gpu_alert1: gpu_alert1 { + /* milliCelsius */ + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu_crit: cpu_crit { /* milliCelsius */ temperature = <110000>; From patchwork Tue Mar 21 15:36:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 95669 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1568984qgd; Tue, 21 Mar 2017 11:10:01 -0700 (PDT) X-Received: by 10.84.215.155 with SMTP id l27mr49825880pli.31.1490119801192; Tue, 21 Mar 2017 11:10:01 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s9si6711395plk.247.2017.03.21.11.10.00; Tue, 21 Mar 2017 11:10:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933664AbdCURek (ORCPT + 17 others); Tue, 21 Mar 2017 13:34:40 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:60573 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758035AbdCUPgk (ORCPT ); Tue, 21 Mar 2017 11:36:40 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id A60AC212F0; Tue, 21 Mar 2017 16:36:38 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 1D6DB207CC; Tue, 21 Mar 2017 16:36:38 +0100 (CET) From: Quentin Schulz To: dmitry.torokhov@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, lee.jones@linaro.org, linux@armlinux.org.uk, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: Quentin Schulz , thomas.petazzoni@free-electrons.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.xyz Subject: [PATCH v3 11/11] ARM: sun8i: sina33: add highest OPP of CPUs Date: Tue, 21 Mar 2017 16:36:11 +0100 Message-Id: <20170321153611.16228-12-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170321153611.16228-1-quentin.schulz@free-electrons.com> References: <20170321153611.16228-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The A33 supports 1.1GHz and 1.2GHz frequencies at 1.32V and the Sinlinx SinA33 has its cpu-supply property set in the cpu DT node. Therefore, CPUfreq knows how to handle the regulator in charge of the CPU and can adjust its voltage to match the OPP. Add these two CPU frequencies to the CPU OPP table of the Sinlinx SinA33. Signed-off-by: Quentin Schulz --- added in v3 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.9.3 diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index d84f1bd..a92dee1 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -87,6 +87,20 @@ cpu-supply = <®_dcdc3>; }; +&cpu0_opp_table { + opp@1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; +}; + &de { status = "okay"; };