From patchwork Fri Jan 19 15:42:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 125176 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp347011ljf; Fri, 19 Jan 2018 07:42:52 -0800 (PST) X-Google-Smtp-Source: ACJfBoubsEEsqzj+mfuygaE+BW8THU6GuckOxRecI3cIPDFrTZ0V31J2y/ws0unG1qpxidSGuCa3 X-Received: by 10.101.78.207 with SMTP id w15mr18581512pgq.349.1516376572372; Fri, 19 Jan 2018 07:42:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516376572; cv=none; d=google.com; s=arc-20160816; b=M5bqKDdXq/WIvZWGWc598KzLhrYYEySYwaegES7rSM5JswtZkj41b+FOqDKohIlJ3J osliZqHR3cLEQHrbhCqlS579KFGi/eYzC/kybY6MtLf/hbSlecVDhvz10ysnE7HdzYPJ 1Li5JShSua3uyfqqUJLHa1qcQssHUnMXQPviTjQHlF0VCR13Tiow/QW6+EDejejhk97e vk8Ps4JXjCR2BLjU1VPmx5cyfE6OsmV2ru2b2zRNrWUma41RckEkmfK3S9pU00qWTpaK kSLEe6bqwBBjYL4or4Z0/IHY3GflPErXUH7W/UAU2agwX3XSKc2fmoPwulkD1EX6FeCi 3JBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=HwdAGXWwh852qmDzl70V80+reOpGTIeiStglI0+NfpY=; b=MameFnYbhck4U10Wwqiz0Lx5yjS4TQXDGyFzABnitnPerw2e5hv7qLcJTT/o4XUTd3 Tr9Jul/88WqGiZofOzaBxh/+bNI8/fhHr/YyUyHLYE3Ojr0BT4CKD13dxDKsp/Vo5iU3 Dvegmc7KIvwlPE76ihni2Zb4d/kMMlN8sOXN2qYCg50dkWa5vpf4ZmtbuqGAAIFGtcGZ Max4HaGd7zop20n1XBxXEKQdAOoo06NmhxTifMkye3c00uHkky3bTlkaI7PYzNPQE8CH ju0BtjeKu6WsqqjFrwedCK4EhXy1joizR9ZUf4hPggl14iOJs+QLutiRhjjshnDYr3jN 8Q8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=uh510ZYO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u78si8263732pgb.481.2018.01.19.07.42.52; Fri, 19 Jan 2018 07:42:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=uh510ZYO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932474AbeASPmt (ORCPT + 28 others); Fri, 19 Jan 2018 10:42:49 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:39469 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932423AbeASPmk (ORCPT ); Fri, 19 Jan 2018 10:42:40 -0500 Received: by mail-wr0-f194.google.com with SMTP id z48so1956034wrz.6 for ; Fri, 19 Jan 2018 07:42:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=HwdAGXWwh852qmDzl70V80+reOpGTIeiStglI0+NfpY=; b=uh510ZYO6MeQ5FnOwLUfdQU1bU/m/bN+3eSybdVNWG4DYsN5VvVaWrGARc6mg0h5A+ Ur3yC7N8Ue/AtFuxbt7jcSpPfVLx0reUn/VHOZ60YXOhAVulJIRjIBVAtj/wNeR3bnrE YM4A8U7NmTTYTSSriVizX/r64bpiVteMK7UbvXjphNMaf+1brpxWwWcoLp4ibXu8hjYy c9qKr1jL6risfP80McfBm378qTyszbtiOhwnBZYgyxFpZs0kUT9B6YVEtGE0fFAtvxaE 4XNyIfe00MXWHzYB+y8AIPgpwHRMPj7JNfWOpKyP5ChQ6N283aix05i4e16akcdv3LMC DrFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=HwdAGXWwh852qmDzl70V80+reOpGTIeiStglI0+NfpY=; b=YfVqE2N4/GDDEyD/PxtdUtQxiBPB3EvVYRQdWzFjNcXGJaCnC9lhUei+Ey0FKCsM48 qokGywguEOw34W22hahFS0FFvZoK9b38aQtNJkJpcBSCVAFvCLj3S4NiNOdcXOBQwJRL 3RF15jNjbUFUHPsL/Dp8DyyVSxKsuKBROJnMEVnjGrSR0faiIqnL3Z1p8TOvYe1y+aW6 0fxjNwQqgebmJjAHyM8ZFthvrtDdg/Kv0j4LucQTS3oP7LJZ55JNdf4ShtYQLIAsM/FA 9cRGaLWa/TTbiC3wNO8vsb5pZbeiNryPFf153GQK4DVa5SK2GnY6NgeCFA2yr3h9qJHA lnGA== X-Gm-Message-State: AKwxyte5pWfaOszr1A6oL7ILB9PkQJVRI62/IWVTIAHy+ll7t4WX2HcY Vsdi4MxXD6tZQSkXqI15U+k6iA== X-Received: by 10.223.176.17 with SMTP id f17mr10151501wra.178.1516376559254; Fri, 19 Jan 2018 07:42:39 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id w73sm25805113wrb.34.2018.01.19.07.42.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 19 Jan 2018 07:42:38 -0800 (PST) From: Jerome Brunet To: Neil Armstrong Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Kevin Hilman , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: meson: add axg misc bit to the mpll driver Date: Fri, 19 Jan 2018 16:42:36 +0100 Message-Id: <20180119154236.9797-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On axg, the rate of the mpll is stuck as if sdm value was 4 and could not change (expect for mpll2 strangely). Looking at the vendor kernel, it turns out a new magic bit from the undocumented HHI_PLL_TOP_MISC register is required. Setting this bit solves the problem and the mpll rates are back to normal Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers") Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 20 ++++++++++++++++++++ drivers/clk/meson/clk-mpll.c | 7 +++++++ drivers/clk/meson/clkc.h | 1 + 3 files changed, 28 insertions(+) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 953e119635a2..2f2b3845c01d 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -292,6 +292,11 @@ static struct meson_clk_mpll axg_mpll0 = { .shift = 25, .width = 1, }, + .misc = { + .reg_off = HHI_PLL_TOP_MISC, + .shift = 0, + .width = 1, + }, .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll0", @@ -322,6 +327,11 @@ static struct meson_clk_mpll axg_mpll1 = { .shift = 14, .width = 1, }, + .misc = { + .reg_off = HHI_PLL_TOP_MISC, + .shift = 1, + .width = 1, + }, .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll1", @@ -352,6 +362,11 @@ static struct meson_clk_mpll axg_mpll2 = { .shift = 14, .width = 1, }, + .misc = { + .reg_off = HHI_PLL_TOP_MISC, + .shift = 2, + .width = 1, + }, .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll2", @@ -382,6 +397,11 @@ static struct meson_clk_mpll axg_mpll3 = { .shift = 0, .width = 1, }, + .misc = { + .reg_off = HHI_PLL_TOP_MISC, + .shift = 3, + .width = 1, + }, .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll3", diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index 5144360e2c80..6d79d6daadc4 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -173,6 +173,13 @@ static int mpll_set_rate(struct clk_hw *hw, reg = PARM_SET(p->width, p->shift, reg, n2); writel(reg, mpll->base + p->reg_off); + p = &mpll->misc; + if (p->width != 0) { + reg = readl(mpll->base + p->reg_off); + reg = PARM_SET(p->width, p->shift, reg, 1); + writel(reg, mpll->base + p->reg_off); + } + if (mpll->lock) spin_unlock_irqrestore(mpll->lock, flags); else diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 4acb35bda669..07aaba26a857 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -121,6 +121,7 @@ struct meson_clk_mpll { struct parm n2; struct parm en; struct parm ssen; + struct parm misc; spinlock_t *lock; };