From patchwork Tue Nov 24 04:18:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 331846 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 355B7C64E7A for ; Tue, 24 Nov 2020 04:19:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E5ABF2086A for ; Tue, 24 Nov 2020 04:19:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727138AbgKXESx (ORCPT ); Mon, 23 Nov 2020 23:18:53 -0500 Received: from mga11.intel.com ([192.55.52.93]:8580 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726158AbgKXESw (ORCPT ); Mon, 23 Nov 2020 23:18:52 -0500 IronPort-SDR: awTksB35+VmSFcRp/TlgIYNJvL8gd+FmjPhXGfhHY6CaPHv5M6PGM2VEeBkpLM/RGP+DClF1jh h3lV0R1/zurw== X-IronPort-AV: E=McAfee;i="6000,8403,9814"; a="168378654" X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="168378654" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2020 20:18:52 -0800 IronPort-SDR: xUXBDvIm1UZknpr7R2R9zdODFvqZdZH0fv+ICqO7T8LxhWheSut2XvvIcmJEDtVmjE8OEJ1elT H2rnDynyh0Bw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="343029831" Received: from sgsxdev004.isng.phoenix.local (HELO localhost) ([10.226.81.179]) by orsmga002.jf.intel.com with ESMTP; 23 Nov 2020 20:18:49 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v9 1/5] spi: cadence-quadspi: Add QSPI support for Intel LGM SoC Date: Tue, 24 Nov 2020 12:18:36 +0800 Message-Id: <20201124041840.31066-2-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Add QSPI controller support for Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/Kconfig | 2 +- drivers/spi/spi-cadence-quadspi.c | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d2c976e55b8b..926da61eee5a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -203,7 +203,7 @@ config SPI_CADENCE config SPI_CADENCE_QUADSPI tristate "Cadence Quad SPI controller" - depends on OF && (ARM || ARM64 || COMPILE_TEST) + depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST) help Enable support for the Cadence Quad SPI Flash controller. diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 40938cf3806d..d7b10c46fa70 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1401,6 +1401,9 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "ti,am654-ospi", .data = &am654_ospi, }, + { + .compatible = "intel,lgm-qspi", + }, { /* end of table */ } }; From patchwork Tue Nov 24 04:18:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 332741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 960D2C64E7C for ; Tue, 24 Nov 2020 04:19:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 480BA2085B for ; Tue, 24 Nov 2020 04:19:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727909AbgKXES4 (ORCPT ); Mon, 23 Nov 2020 23:18:56 -0500 Received: from mga11.intel.com ([192.55.52.93]:8580 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726158AbgKXES4 (ORCPT ); Mon, 23 Nov 2020 23:18:56 -0500 IronPort-SDR: 4BvLlg7braVNUGWmkUcovuW/j+8MKB6R4ckeZ/eLB/J3BvpwpnCnBZC3P6Hay/oKzns47uYl6Y FrOXcsFR6m2Q== X-IronPort-AV: E=McAfee;i="6000,8403,9814"; a="168378669" X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="168378669" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2020 20:18:56 -0800 IronPort-SDR: sBvWoYr74p3lWqqnUy+GsmydSZt6zi34vvPqv+loX2QigTV1lcwwOoglLotbf9NkFCuzUSrlK8 OWYwl0KvlQfw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="343029843" Received: from sgsxdev004.isng.phoenix.local (HELO localhost) ([10.226.81.179]) by orsmga002.jf.intel.com with ESMTP; 23 Nov 2020 20:18:53 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v9 2/5] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC Date: Tue, 24 Nov 2020 12:18:37 +0800 Message-Id: <20201124041840.31066-3-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use Direct Access Controller(DAC). This patch adds a quirk to disable the Direct Access Controller for data transfer instead it uses indirect data transfe DAC bit resets to 1 so there is no need to explicitly set it. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/spi-cadence-quadspi.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index d7b10c46fa70..d12b765e87be 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1101,10 +1101,12 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) writel(cqspi->fifo_depth * cqspi->fifo_width / 8, cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); - /* Enable Direct Access Controller */ - reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); - reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; - writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + /* Disable direct access controller */ + if (!cqspi->use_direct_mode) { + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + } cqspi_controller_enable(cqspi, 1); } @@ -1388,6 +1390,10 @@ static const struct cqspi_driver_platdata am654_ospi = { .quirks = CQSPI_NEEDS_WR_DELAY, }; +static const struct cqspi_driver_platdata intel_lgm_qspi = { + .quirks = CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1403,6 +1409,7 @@ static const struct of_device_id cqspi_dt_ids[] = { }, { .compatible = "intel,lgm-qspi", + .data = &intel_lgm_qspi, }, { /* end of table */ } }; From patchwork Tue Nov 24 04:18:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 331845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4DD1C64E7B for ; Tue, 24 Nov 2020 04:19:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9960C20857 for ; Tue, 24 Nov 2020 04:19:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728346AbgKXES7 (ORCPT ); Mon, 23 Nov 2020 23:18:59 -0500 Received: from mga11.intel.com ([192.55.52.93]:8580 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726158AbgKXES7 (ORCPT ); Mon, 23 Nov 2020 23:18:59 -0500 IronPort-SDR: c4pbWygTXxNwyl8scjUSpfgpgsjWn7auxO62hf162uhyRAYyQeWokPHcR4VxsYW0RWuHN9MS5g 6NcjBizTgQNw== X-IronPort-AV: E=McAfee;i="6000,8403,9814"; a="168378673" X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="168378673" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2020 20:18:58 -0800 IronPort-SDR: 6ex/SSKMnrVQveeLtw84HWt3BUKZ6ypuWaCotSwQO37Gb4REMrRVqU8pjgNHlWCoFfI1I8Mkn4 4puqfN97h0tQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="343029861" Received: from sgsxdev004.isng.phoenix.local (HELO localhost) ([10.226.81.179]) by orsmga002.jf.intel.com with ESMTP; 23 Nov 2020 20:18:56 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v9 3/5] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC Date: Tue, 24 Nov 2020 12:18:38 +0800 Message-Id: <20201124041840.31066-4-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Add multiple chipselect support for Intel LGM SoCs, currently QSPI-NOR and QSPI-NAND supported. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/spi-cadence-quadspi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index d12b765e87be..c7ecd6d44326 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -75,6 +75,7 @@ struct cqspi_st { bool is_decoded_cs; u32 fifo_depth; u32 fifo_width; + u32 num_chipselect; bool rclk_en; u32 trigger_address; u32 wr_delay; @@ -1070,6 +1071,9 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi) return -ENXIO; } + if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) + cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; + cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); return 0; @@ -1302,6 +1306,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->current_cs = -1; cqspi->sclk = 0; + master->num_chipselect = cqspi->num_chipselect; + ret = cqspi_setup_flash(cqspi); if (ret) { dev_err(dev, "failed to setup flash parameters %d\n", ret); From patchwork Tue Nov 24 04:18:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 331844 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, TVD_SPACE_RATIO, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4720EC64E90 for ; Tue, 24 Nov 2020 04:19:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EB3FC20BED for ; Tue, 24 Nov 2020 04:19:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728664AbgKXETD (ORCPT ); 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23 Nov 2020 20:19:00 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v9 4/5] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Date: Tue, 24 Nov 2020 12:18:39 +0800 Message-Id: <20201124041840.31066-5-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Move the Documentation/devicetree/bindings/mtd/cadence-quadspi.txt to Documentation/devicetree/bindings/spi/ Signed-off-by: Ramuthevar Vadivel Murugan Acked-by: Rob Herring --- Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt (100%) diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt similarity index 100% rename from Documentation/devicetree/bindings/mtd/cadence-quadspi.txt rename to Documentation/devicetree/bindings/spi/cadence-quadspi.txt From patchwork Tue Nov 24 04:18:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 332740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CAC0C64EBC for ; Tue, 24 Nov 2020 04:19:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5008520BED for ; Tue, 24 Nov 2020 04:19:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728711AbgKXETH (ORCPT ); Mon, 23 Nov 2020 23:19:07 -0500 Received: from mga11.intel.com ([192.55.52.93]:8580 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726158AbgKXETH (ORCPT ); Mon, 23 Nov 2020 23:19:07 -0500 IronPort-SDR: smoHwPAto5GrdLrgTVY+EwTPXqoXdUXJ/KejIXEsLSrK2Zbb332MZ7BwaD4YcOpd4+0rdH21jx C6mmCS+bYeAg== X-IronPort-AV: E=McAfee;i="6000,8403,9814"; a="168378682" X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="168378682" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2020 20:19:06 -0800 IronPort-SDR: Ap4A08/c/032HNPRRtjG1PqASnlGzsy3DnNxUuOxpCr7oUn6v3h+PrKjSyu0BI/+DfNOC6NXjZ rAnQ6QAe01bQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="343029901" Received: from sgsxdev004.isng.phoenix.local (HELO localhost) ([10.226.81.179]) by orsmga002.jf.intel.com with ESMTP; 23 Nov 2020 20:19:03 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v9 5/5] dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi Date: Tue, 24 Nov 2020 12:18:40 +0800 Message-Id: <20201124041840.31066-6-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ramuthevar Vadivel Murugan Add new vendor specific compatible string to check Intel's Lightning Mountain(LGM) QSPI features enablement in cadence-quadspi driver. Signed-off-by: Ramuthevar Vadivel Murugan Acked-by: Rob Herring --- Documentation/devicetree/bindings/spi/cadence-quadspi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt index 945be7d5b236..8ace832a2d80 100644 --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt @@ -5,6 +5,7 @@ Required properties: Generic default - "cdns,qspi-nor". For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". + For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the