From patchwork Thu Nov 19 17:04:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 328562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26200C6369E for ; Thu, 19 Nov 2020 17:04:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A375824654 for ; Thu, 19 Nov 2020 17:04:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="YWATW9BI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728062AbgKSREb (ORCPT ); Thu, 19 Nov 2020 12:04:31 -0500 Received: from esa6.microchip.iphmx.com ([216.71.154.253]:37977 "EHLO esa6.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727690AbgKSREb (ORCPT ); Thu, 19 Nov 2020 12:04:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1605805470; x=1637341470; h=from:to:cc:subject:date:message-id:mime-version; bh=vXFruGr2aeW8WhqpRz+OKo5sifRSrF1d5mIcR47IXVQ=; b=YWATW9BImYcp+l3d0WNbPQHkJwbVtRHXnGG3Y6z/xs9D0e2YmK5Xeu1A TzWynyjRmLsG8WIjyPsbO8jOXn/sDiDy4EoeSmLESGyMfNoVachSkW1ne rsq0XXtt7GtDteI2KFIP9lKO8Q3Y9qsQazpsGvn5apcNFZbdD96VuHTkB awTpvFzvceObM/Ms0KbzqR6XJoRuTfu1WPWEorpcw5JU2+9lFwe5f6ZWG KKf3Eli54hzrxssyumhXJ8hnpZld2XdXTAR/0aqmLwB9I7KBbQv0DMSR9 0aHbzopshQYqeGpHqYR4OJ6gCVQlqTUPEbhgxgvE9ZCtfO1nnMPxOxjbD A==; IronPort-SDR: AMkXjyz8d2ibjOIG7F0VpnoFYjx7m6rlDs5Aedbb/9BNxudKVzzyUKWIqWauJfPA9uj93ehevU hQtHjKjV4042RD77ybrBjG/sA/6ajIANgaO3vP2QpgC5dsMkceNj36h1+c+ZiU8PGRtNbArAkE X/2xaoMT3AHBKyqDsG1CBHFvT8HVCSNMtpiSwkvKZ/cnonLr2c6x5vih/v8J/VhSBsuoIoMChl xdGtDh5E4Ey2ah9RKvySedc6WAE0ShZzBTU2ZK4dZXf3cX+UPP1yEwXUVV25YcsQiKYZTZCSV1 Y7I= X-IronPort-AV: E=Sophos;i="5.78,353,1599548400"; d="scan'208";a="34319665" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Nov 2020 10:04:28 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 19 Nov 2020 10:04:28 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 10:04:26 -0700 From: To: , , , , , , CC: , , , , , , Conor Dooley Subject: [PATCH 2/6] soc: add polarfire soc header file Date: Thu, 19 Nov 2020 17:04:25 +0000 Message-ID: <20201119170425.18365-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add header to support the Microchip PolarFire SoC MSS system controller mailbox. Signed-off-by: Conor Dooley --- include/soc/microchip/mpfs.h | 50 ++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 include/soc/microchip/mpfs.h diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h new file mode 100644 index 000000000000..60311ab72b76 --- /dev/null +++ b/include/soc/microchip/mpfs.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Microchip MPFS mailbox + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#ifndef __SOC_MPFS_H__ +#define __SOC_MPFS_H__ + +#include +#include + +struct mpfs_sys_controller; + +struct mpfs_mss_msg { + u8 cmd_opcode; + u16 cmd_data_size; + u16 response_size; + u8 *cmd_data; + u16 mailbox_offset; + u16 response_offset; +}; + +#if IS_ENABLED(CONFIG_MPFS_SYS_CONTROLLER) + +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg, + void *response, u16 response_size_bytes); + +struct mpfs_sys_controller *mpfs_sys_controller_get(struct device_node *mailbox_node); + +#else + +static int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg, + void *response, u16 response_size_bytes) +{ + return -ENOSYS; +}; + +struct mpfs_sys_controller *mpfs_sys_controller_get(struct device_node *mailbox_node) +{ + return NULL; +} + +#endif /* IS_ENABLED(CONFIG_MPFS_SYS_CONTROLLER) */ + +#endif /* __SOC_MPFS_H__ */ From patchwork Thu Nov 19 17:04:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 328561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84FCBC63697 for ; Thu, 19 Nov 2020 17:04:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2317224655 for ; Thu, 19 Nov 2020 17:04:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ejQKLCQb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727690AbgKSREn (ORCPT ); Thu, 19 Nov 2020 12:04:43 -0500 Received: from esa6.microchip.iphmx.com ([216.71.154.253]:38016 "EHLO esa6.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727241AbgKSREn (ORCPT ); Thu, 19 Nov 2020 12:04:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1605805482; x=1637341482; h=from:to:cc:subject:date:message-id:mime-version; bh=hdKJ8AThaKsHmxLWkwQyL5C107/YEmRfruTeZIwBtm0=; b=ejQKLCQb8ce0xSfV9hWXF6xxD8Il+xyYTKqRVUT899bZeWPXog6o75ca JY4DQDe9weO/uUt2rK4DzLxO8QtKxaq1KeJ08P1Obb0CzGviA7Vjj3kZj S2XE7B0WmOxV80MCBtibNHBaJDevkbsf71bdo2wTIXDRh9bpRaHR/Dsud Kb/sYX3Tn0bH2no1WwiVE+bfsegFkduHl6ngmz3el1YYyjIbj8VwO3Wfu 1ool5A58F4NeHcEO/0bWoZiUIdFl6XZtGNBW4lIPmXRGqDDtaPOSx/46c aYkuorsDkcu3rMMW2JoAzmz5FEh40Vt4KFpsU4ycbt8/zbNdgeq6Nhy5+ A==; IronPort-SDR: Y29Wda79zUAE9jlf632nUkuVXX7TzCrF0Sk1WF4utMElhGXWHfICjKpE4MKvgzHaq4vzYnrPYO CX1FHdTPefPHQqC1V3zoQ3yV1Olf+wkjwy21eX0KNgrrVkiAq5OsiiMyd0i5ZDIlunSk5l24Ua tj6/ifDsahmJEBjoJALgI8H3BItWyjjwl+/DjMesBbO8wNAA11S6bBOSdeNIUV7oKZFvgNi+Gh WBuGtH79C9LQ2lDXZXUtkEbwC/wbAtJzbo7DnMlbB1bNxSWFKD3C4gAL8GP/qxXWvoWXQtd2uC nhU= X-IronPort-AV: E=Sophos;i="5.78,353,1599548400"; d="scan'208";a="34319743" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Nov 2020 10:04:41 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 19 Nov 2020 10:04:40 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 10:04:37 -0700 From: To: , , , , , , CC: , , , , , , Conor Dooley Subject: [PATCH 4/6] soc: add polarfire soc system controller Date: Thu, 19 Nov 2020 17:04:37 +0000 Message-ID: <20201119170437.18519-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley This driver provides an interface for other drivers to access the functions of the system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/microchip/Kconfig | 10 ++ drivers/soc/microchip/Makefile | 1 + drivers/soc/microchip/mpfs_sys_controller.c | 136 ++++++++++++++++++++ 5 files changed, 149 insertions(+) create mode 100644 drivers/soc/microchip/Kconfig create mode 100644 drivers/soc/microchip/Makefile create mode 100644 drivers/soc/microchip/mpfs_sys_controller.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 425ab6f7e375..22cb097bcbdc 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -9,6 +9,7 @@ source "drivers/soc/bcm/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" +source "drivers/soc/microchip/Kconfig" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 36452bed86ef..fb084cf2d12e 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_GEMINI) += gemini/ obj-y += imx/ obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ +obj-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip/ obj-y += mediatek/ obj-y += amlogic/ obj-y += qcom/ diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig new file mode 100644 index 000000000000..8fdba8b5eae3 --- /dev/null +++ b/drivers/soc/microchip/Kconfig @@ -0,0 +1,10 @@ +config MPFS_SYS_CONTROLLER + tristate "MPFS_SYS_CONTROLLER" + depends on MPFS_MBOX + help + This driver adds support for the Polarfire SoC system controller. + + To compile this driver as a module, choose M here. the + module will be called mpfs_system_controller. + + If unsure, say Y. diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile new file mode 100644 index 000000000000..23b1f42a37db --- /dev/null +++ b/drivers/soc/microchip/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MPFS_SYS_CONTROLLER) += mpfs_sys_controller.o diff --git a/drivers/soc/microchip/mpfs_sys_controller.c b/drivers/soc/microchip/mpfs_sys_controller.c new file mode 100644 index 000000000000..0074ae529a2e --- /dev/null +++ b/drivers/soc/microchip/mpfs_sys_controller.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip MPFS system controller driver + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_MUTEX(transaction_lock); + +struct mpfs_sys_controller { + struct mbox_client client; + struct mbox_chan *chan; + struct completion c; + u32 enabled; + void *response; + u16 response_size_bytes; +}; + +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg, + void *response, u16 response_size_bytes) +{ + int ret; + + mpfs_client->response = response; + mpfs_client->response_size_bytes = response_size_bytes; + + mutex_lock_interruptible(&transaction_lock); + + reinit_completion(&mpfs_client->c); + + ret = mbox_send_message(mpfs_client->chan, msg); + + if (ret >= 0U) { + if (wait_for_completion_timeout(&mpfs_client->c, HZ)) { + ret = 0U; + } else { + ret = -ETIMEDOUT; + WARN_ONCE(1, "MPFS sys controller transaction timeout"); + } + } else { + dev_err(mpfs_client->client.dev, + "mpfs sys controller transaction returned %d\r\n", ret); + } + + mutex_unlock(&transaction_lock); + + return ret; +} +EXPORT_SYMBOL(mpfs_blocking_transaction); + +static void rx_callback(struct mbox_client *client, void *msg) +{ + struct mpfs_sys_controller *mpfs_client = + container_of(client, struct mpfs_sys_controller, client); + + memcpy(mpfs_client->response, (u8 *)msg, + mpfs_client->response_size_bytes); + + complete(&mpfs_client->c); +} + +static int mpfs_sys_controller_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mpfs_sys_controller *mpfs_client; + + mpfs_client = devm_kzalloc(dev, sizeof(*mpfs_client), GFP_KERNEL); + if (!mpfs_client) + return -ENOMEM; + + mpfs_client->client.dev = dev; + mpfs_client->client.rx_callback = rx_callback; + mpfs_client->client.tx_block = 1U; + + mpfs_client->chan = mbox_request_channel_byname(&mpfs_client->client, + "mbox-mpfs"); + if (IS_ERR(mpfs_client->chan)) { + int ret = PTR_ERR(mpfs_client->chan); + + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get mbox channel: %d\n", ret); + return ret; + } + + init_completion(&mpfs_client->c); + + platform_set_drvdata(pdev, mpfs_client); + + dev_info(&pdev->dev, "Registered MPFS system controller driver\n"); + + return 0; +} + +struct mpfs_sys_controller * +mpfs_sys_controller_get(struct device_node *mss_node) +{ + struct platform_device *pdev = of_find_device_by_node(mss_node); + + if (!pdev) + return NULL; + + return platform_get_drvdata(pdev); +} +EXPORT_SYMBOL(mpfs_sys_controller_get); + +static const struct of_device_id mpfs_sys_controller_of_match[] = { + { + .compatible = "microchip,polarfire-soc-sys-controller", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_sys_controller_of_match); + +static struct platform_driver mpfs_sys_controller_driver = { + .driver = { + .name = "mpfs-sys-controller", + .of_match_table = mpfs_sys_controller_of_match, + }, + .probe = mpfs_sys_controller_probe, +}; +module_platform_driver(mpfs_sys_controller_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("MPFS system controller driver"); From patchwork Thu Nov 19 17:04:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 328560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5F6AC6369E for ; Thu, 19 Nov 2020 17:04:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 735AB24654 for ; Thu, 19 Nov 2020 17:04:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ZuMHVT1F" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728205AbgKSREv (ORCPT ); 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d="scan'208";a="99122009" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Nov 2020 10:04:50 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 19 Nov 2020 10:04:48 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 19 Nov 2020 10:04:46 -0700 From: To: , , , , , , CC: , , , , , , Conor Dooley Subject: [PATCH 6/6] MAINTAINERS: add microchip polarfire soc support Date: Thu, 19 Nov 2020 17:04:45 +0000 Message-ID: <20201119170445.18795-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC directory Signed-off-by: Conor Dooley --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3da6d8c154e4..2965daaa80e9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15000,6 +15000,15 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT +M: Lewis Hanly +M: Cyril Jean +L: linux-riscv@lists.infradead.org +S: Supported +F: drivers/mailbox/mailbox-mpfs.c +F: drivers/soc/microchip/ +F: include/soc/microchip/mpfs.h + RNBD BLOCK DRIVERS M: Danil Kipnis M: Jack Wang