From patchwork Wed Nov 18 08:31:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 326107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D195C63697 for ; Wed, 18 Nov 2020 08:39:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D68B424654 for ; Wed, 18 Nov 2020 08:39:00 +0000 (UTC) Authentication-Results: mail.kernel.org; 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lists.infradead.org; dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) by VI1PR04MB6990.eurprd04.prod.outlook.com (2603:10a6:803:138::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25; Wed, 18 Nov 2020 08:38:37 +0000 Received: from VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685]) by VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685%7]) with mapi id 15.20.3589.021; Wed, 18 Nov 2020 08:38:37 +0000 From: Liu Ying To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, robh+dt@kernel.org, aisheng.dong@nxp.com Subject: [PATCH 1/5] clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks Date: Wed, 18 Nov 2020 16:31:26 +0800 Message-Id: <1605688290-21805-2-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1605688290-21805-1-git-send-email-victor.liu@nxp.com> References: <1605688290-21805-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3589.17 via Frontend Transport; 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Cc: Michael Turquette Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Dong Aisheng Signed-off-by: Liu Ying --- drivers/clk/imx/clk-imx8qxp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 5b3d4ed..aeafa70 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -115,6 +115,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) clks[IMX_CONN_USB2_LPM_CLK] = imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells); /* Display controller SS */ + clks[IMX_DC0_PLL0_CLK] = imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells); + clks[IMX_DC0_PLL1_CLK] = imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells); clks[IMX_DC0_DISP0_CLK] = imx_clk_scu("dc0_disp0_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells); clks[IMX_DC0_DISP1_CLK] = imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells); 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lists.infradead.org; dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) by VI1PR04MB6990.eurprd04.prod.outlook.com (2603:10a6:803:138::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25; Wed, 18 Nov 2020 08:38:41 +0000 Received: from VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685]) by VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685%7]) with mapi id 15.20.3589.021; Wed, 18 Nov 2020 08:38:41 +0000 From: Liu Ying To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, robh+dt@kernel.org, aisheng.dong@nxp.com Subject: [PATCH 2/5] clk: imx: clk-imx8qxp-lpcg: Add display controller LPCG clocks support Date: Wed, 18 Nov 2020 16:31:27 +0800 Message-Id: <1605688290-21805-3-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1605688290-21805-1-git-send-email-victor.liu@nxp.com> References: <1605688290-21805-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3589.17 via Frontend Transport; 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Cc: Michael Turquette Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Rob Herring Cc: Dong Aisheng Signed-off-by: Liu Ying --- drivers/clk/imx/clk-imx8qxp-lpcg.c | 41 ++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8qxp-lpcg.h | 20 +++++++++++++++++ include/dt-bindings/clock/imx8-clock.h | 35 +++++++++++++++++++++++++++++ 3 files changed, 96 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c index d3e905c..176d426 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c @@ -115,6 +115,46 @@ static const struct imx8qxp_ss_lpcg imx8qxp_ss_conn = { .num_max = IMX_CONN_LPCG_CLK_END, }; +static const struct imx8qxp_lpcg_data imx8qxp_lpcg_dc[] = { + { IMX_DC0_LPCG_DISP0_CLK, "dc0_lpcg_disp0_clk", "dc0_disp0_clk", 0, DC_DISP_LPCG, 0, 0, }, + { IMX_DC0_LPCG_DISP1_CLK, "dc0_lpcg_disp1_clk", "dc0_disp1_clk", 0, DC_DISP_LPCG, 4, 0, }, + { IMX_DC0_LPCG_LIS_IPG_CLK, "dc0_lpcg_lis_ipg_clk", "dc_cfg_clk_root", 0, DC_LIS_IPG_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DISP_CTL_LINK_MST0_CLK, "dc0_lpcg_disp_ctl_link_mst0_clk", "dc_cfg_clk_root", 0, DC_DISP_CTL_LINK_MST0_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PIX_COMBINER_APB_CLK, "dc0_lpcg_pix_combiner_apb_clk", "dc_cfg_clk_root", 0, DC_PIX_COMBINER_APB_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DC_AXI_CLK, "dc0_lpcg_dc_axi_clk", "dc_axi_int_clk_root", 0, DC_AXI_CFG_LPCG, 20, 0, }, + { IMX_DC0_LPCG_DC_CFG_CLK, "dc0_lpcg_dc_cfg_clk", "dc_cfg_clk_root", 0, DC_AXI_CFG_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DPR0_APB_CLK, "dc0_lpcg_dpr0_apb_clk", "dc_cfg_clk_root", 0, DC_DPR0_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DPR0_B_CLK, "dc0_lpcg_dpr0_b_clk", "dc_axi_ext_clk_root", 0, DC_DPR0_LPCG, 20, 0, }, + { IMX_DC0_LPCG_RTRAM0_CLK, "dc0_lpcg_rtram0_clk", "dc_axi_int_clk_root", 0, DC_RTRAM0_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG0_RTRAM_CLK, "dc0_lpcg_prg0_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG0_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG0_APB_CLK, "dc0_lpcg_prg0_apb_clk", "dc_cfg_clk_root", 0, DC_PRG0_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG1_RTRAM_CLK, "dc0_lpcg_prg1_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG1_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG1_APB_CLK, "dc0_lpcg_prg1_apb_clk", "dc_cfg_clk_root", 0, DC_PRG1_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG2_RTRAM_CLK, "dc0_lpcg_prg2_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG2_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG2_APB_CLK, "dc0_lpcg_prg2_apb_clk", "dc_cfg_clk_root", 0, DC_PRG2_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DPR1_APB_CLK, "dc0_lpcg_dpr1_apb_clk", "dc_cfg_clk_root", 0, DC_DPR1_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DPR1_B_CLK, "dc0_lpcg_dpr1_b_clk", "dc_axi_ext_clk_root", 0, DC_DPR1_LPCG, 20, 0, }, + { IMX_DC0_LPCG_RTRAM1_CLK, "dc0_lpcg_rtram1_clk", "dc_axi_int_clk_root", 0, DC_RTRAM1_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG3_RTRAM_CLK, "dc0_lpcg_prg3_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG3_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG3_APB_CLK, "dc0_lpcg_prg3_apb_clk", "dc_cfg_clk_root", 0, DC_PRG3_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG4_RTRAM_CLK, "dc0_lpcg_prg4_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG4_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG4_APB_CLK, "dc0_lpcg_prg4_apb_clk", "dc_cfg_clk_root", 0, DC_PRG4_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG5_RTRAM_CLK, "dc0_lpcg_prg5_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG5_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG5_APB_CLK, "dc0_lpcg_prg5_apb_clk", "dc_cfg_clk_root", 0, DC_PRG5_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG6_RTRAM_CLK, "dc0_lpcg_prg6_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG6_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG6_APB_CLK, "dc0_lpcg_prg6_apb_clk", "dc_cfg_clk_root", 0, DC_PRG6_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG7_RTRAM_CLK, "dc0_lpcg_prg7_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG7_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG7_APB_CLK, "dc0_lpcg_prg7_apb_clk", "dc_cfg_clk_root", 0, DC_PRG7_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG8_RTRAM_CLK, "dc0_lpcg_prg8_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG8_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG8_APB_CLK, "dc0_lpcg_prg8_apb_clk", "dc_cfg_clk_root", 0, DC_PRG8_LPCG, 16, 0, }, +}; + +static const struct imx8qxp_ss_lpcg imx8qxp_ss_dc = { + .lpcg = imx8qxp_lpcg_dc, + .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_dc), + .num_max = IMX_DC0_LPCG_CLK_END, +}; + static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = { { IMX_LSIO_LPCG_PWM0_IPG_CLK, "pwm0_lpcg_ipg_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 0, 0, }, { IMX_LSIO_LPCG_PWM0_IPG_HF_CLK, "pwm0_lpcg_ipg_hf_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 4, 0, }, @@ -355,6 +395,7 @@ static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev) static const struct of_device_id imx8qxp_lpcg_match[] = { { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, }, { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, }, + { .compatible = "fsl,imx8qxp-lpcg-dc", &imx8qxp_ss_dc, }, { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, }, { .compatible = "fsl,imx8qxp-lpcg", NULL }, { /* sentinel */ } diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h index 2a37ce5..e1423a9 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.h +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h @@ -99,4 +99,24 @@ #define ADMA_FLEXCAN_1_LPCG 0x1ce0000 #define ADMA_FLEXCAN_2_LPCG 0x1cf0000 +/* Display SS */ +#define DC_DISP_LPCG 0x00 +#define DC_LIS_IPG_LPCG 0x04 +#define DC_DISP_CTL_LINK_MST0_LPCG 0x08 +#define DC_PIX_COMBINER_APB_LPCG 0x10 +#define DC_AXI_CFG_LPCG 0x14 +#define DC_DPR0_LPCG 0x18 +#define DC_RTRAM0_LPCG 0x1c +#define DC_PRG0_LPCG 0x20 +#define DC_PRG1_LPCG 0x24 +#define DC_PRG2_LPCG 0x28 +#define DC_DPR1_LPCG 0x2c +#define DC_RTRAM1_LPCG 0x30 +#define DC_PRG3_LPCG 0x34 +#define DC_PRG4_LPCG 0x38 +#define DC_PRG5_LPCG 0x3c +#define DC_PRG6_LPCG 0x40 +#define DC_PRG7_LPCG 0x44 +#define DC_PRG8_LPCG 0x48 + #endif /* _IMX8QXP_LPCG_H */ diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h index 673a8c6..c9dd0c6 100644 --- a/include/dt-bindings/clock/imx8-clock.h +++ b/include/dt-bindings/clock/imx8-clock.h @@ -290,4 +290,39 @@ #define IMX_ADMA_LPCG_CLK_END 45 +/* DC0 SS LPCG */ +#define IMX_DC0_LPCG_DISP0_CLK 0 +#define IMX_DC0_LPCG_DISP1_CLK 1 +#define IMX_DC0_LPCG_LIS_IPG_CLK 2 +#define IMX_DC0_LPCG_DISP_CTL_LINK_MST0_CLK 3 +#define IMX_DC0_LPCG_PIX_COMBINER_APB_CLK 4 +#define IMX_DC0_LPCG_DC_AXI_CLK 5 +#define IMX_DC0_LPCG_DC_CFG_CLK 6 +#define IMX_DC0_LPCG_DPR0_APB_CLK 7 +#define IMX_DC0_LPCG_DPR0_B_CLK 8 +#define IMX_DC0_LPCG_RTRAM0_CLK 9 +#define IMX_DC0_LPCG_PRG0_RTRAM_CLK 10 +#define IMX_DC0_LPCG_PRG0_APB_CLK 11 +#define IMX_DC0_LPCG_PRG1_RTRAM_CLK 12 +#define IMX_DC0_LPCG_PRG1_APB_CLK 13 +#define IMX_DC0_LPCG_PRG2_RTRAM_CLK 14 +#define IMX_DC0_LPCG_PRG2_APB_CLK 15 +#define IMX_DC0_LPCG_DPR1_APB_CLK 16 +#define IMX_DC0_LPCG_DPR1_B_CLK 17 +#define IMX_DC0_LPCG_RTRAM1_CLK 18 +#define IMX_DC0_LPCG_PRG3_RTRAM_CLK 19 +#define IMX_DC0_LPCG_PRG3_APB_CLK 20 +#define IMX_DC0_LPCG_PRG4_RTRAM_CLK 21 +#define IMX_DC0_LPCG_PRG4_APB_CLK 22 +#define IMX_DC0_LPCG_PRG5_RTRAM_CLK 23 +#define IMX_DC0_LPCG_PRG5_APB_CLK 24 +#define IMX_DC0_LPCG_PRG6_RTRAM_CLK 25 +#define IMX_DC0_LPCG_PRG6_APB_CLK 26 +#define IMX_DC0_LPCG_PRG7_RTRAM_CLK 27 +#define IMX_DC0_LPCG_PRG7_APB_CLK 28 +#define IMX_DC0_LPCG_PRG8_RTRAM_CLK 29 +#define IMX_DC0_LPCG_PRG8_APB_CLK 30 + +#define IMX_DC0_LPCG_CLK_END 31 + #endif /* __DT_BINDINGS_CLOCK_IMX_H */ From patchwork Wed Nov 18 08:31:28 2020 Content-Type: text/plain; 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Wed, 18 Nov 2020 08:38:45 +0000 From: Liu Ying To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, robh+dt@kernel.org, aisheng.dong@nxp.com Subject: [PATCH 3/5] clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems Date: Wed, 18 Nov 2020 16:31:28 +0800 Message-Id: <1605688290-21805-4-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1605688290-21805-1-git-send-email-victor.liu@nxp.com> References: <1605688290-21805-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3589.17 via Frontend Transport; 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Cc: Michael Turquette Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Dong Aisheng Signed-off-by: Liu Ying --- drivers/clk/imx/clk-imx8qxp.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index aeafa70..57aa270 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -121,8 +121,18 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) clks[IMX_DC0_DISP1_CLK] = imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells); /* MIPI-LVDS SS */ + clks[IMX_MIPI0_LVDS_PIXEL_CLK] = imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells); + clks[IMX_MIPI0_LVDS_BYPASS_CLK] = imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells); + clks[IMX_MIPI0_LVDS_PHY_CLK] = imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells); clks[IMX_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells); clks[IMX_MIPI0_I2C1_CLK] = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells); + clks[IMX_MIPI0_PWM0_CLK] = imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); + clks[IMX_MIPI1_LVDS_PIXEL_CLK] = imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells); + clks[IMX_MIPI1_LVDS_BYPASS_CLK] = imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells); + clks[IMX_MIPI1_LVDS_PHY_CLK] = imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells); + clks[IMX_MIPI1_I2C0_CLK] = imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells); + clks[IMX_MIPI1_I2C1_CLK] = imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells); + clks[IMX_MIPI1_PWM0_CLK] = imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); /* MIPI CSI SS */ clks[IMX_CSI0_CORE_CLK] = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells); From patchwork Wed Nov 18 08:31:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 326691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 281E5C64E69 for ; Wed, 18 Nov 2020 08:39:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BCC78241A5 for ; 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dkim=none (message not signed) header.d=none; lists.infradead.org; dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) by VI1PR0401MB2528.eurprd04.prod.outlook.com (2603:10a6:800:56::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.28; Wed, 18 Nov 2020 08:38:49 +0000 Received: from VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685]) by VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685%7]) with mapi id 15.20.3589.021; Wed, 18 Nov 2020 08:38:49 +0000 From: Liu Ying To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, robh+dt@kernel.org, aisheng.dong@nxp.com Subject: [PATCH 4/5] dt-bindings: clock: imx8qxp-lpcg: Add compatibles for MIPI-LVDS subsystems Date: Wed, 18 Nov 2020 16:31:29 +0800 Message-Id: <1605688290-21805-5-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1605688290-21805-1-git-send-email-victor.liu@nxp.com> References: <1605688290-21805-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3589.17 via Frontend Transport; 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SFS:(4636009)(366004)(376002)(346002)(39860400002)(136003)(396003)(2616005)(8936002)(2906002)(6506007)(83380400001)(36756003)(86362001)(6666004)(478600001)(26005)(8676002)(6512007)(186003)(7416002)(956004)(316002)(16526019)(66556008)(6486002)(69590400008)(66946007)(66476007)(4326008)(5660300002)(52116002)(32563001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: BsSISv8D7K/yxbzSaGEy7KjsYTkTqsxbw0mS6GuBvMrK/XMM4lmQ2zirlkkrVfI9WC7M+Rz8FwF8QfQFiVDipRKaLyUVpVpI+5h0V0pUD500XMagUaCq8kHsmYzSELdQxq1SOi08o1+zde5qoAt74TFxN5vMe7HOiVjJAftIDmZfguQhF95ylZ54us+Z8Lj/8hho+4+MtMNVURFb4iJ6ajy1OYP9NHOhYM4kULoq5I27ApAEl+93kFCy/j5Q+iiVhYFySXFf8S371c1LHjScXOTyBa5AuY65BdUsgqqRyYMU965Ffa68xTXyNKlqaNCLl9WbCAfisXBf/KjX84gwUPv+P17nQfD3ZYRww4ZWqdzNn6GQCNejRyML7mv585tcApE6G02tQcBhqeZcuJZIoKO6vkG005ROiIE0oxUjSgRRK/tdBWFeLk0pXPhQeUP4+M/lbGmWu3Vo4e/LgAcIDv3wte45KDil5rz1vB+vEjZ7UCZ0WEjLc4pDQzLIBn+5B9702tpK4dvh1+UYgS1jKvlDUok+9hWY5Qwaq3wY/VEG/1ffW7TUp8xCKZ2zO+VibmGtegMAV5sZRMPBotbuwWUY7o5vMWlooVYjXgtcNwuJ3fRITJIK64tGeDkAfdzFujfYczu85Hulzj1X1akTAg== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5cb3b172-1da7-4040-5838-08d88b9d5ef8 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2020 08:38:49.5873 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nZGd7Mo3im4ABys97+DdnfVZSNivNKhyS3+JkL1wDn32oP28h3TMAVlm0vRdhEAiIFgV45BrcdVbCaDfE6tlfg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2528 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds compatibles for i.MX8qxp MIPI-LVDS subsystems. Cc: Michael Turquette Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Rob Herring Cc: Dong Aisheng Signed-off-by: Liu Ying --- Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml index e709e53..868731a0 100644 --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml @@ -40,6 +40,8 @@ properties: - fsl,imx8qxp-lpcg-hsio - fsl,imx8qxp-lpcg-img - fsl,imx8qxp-lpcg-lsio + - fsl,imx8qxp-lpcg-mipi-lvds-0 + - fsl,imx8qxp-lpcg-mipi-lvds-1 - fsl,imx8qxp-lpcg-vpu deprecated: true reg: From patchwork Wed Nov 18 08:31:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 326105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89179C5519F for ; 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dkim=none (message not signed) header.d=none; lists.infradead.org; dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) by VI1PR0401MB2528.eurprd04.prod.outlook.com (2603:10a6:800:56::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.28; Wed, 18 Nov 2020 08:38:53 +0000 Received: from VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685]) by VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685%7]) with mapi id 15.20.3589.021; Wed, 18 Nov 2020 08:38:53 +0000 From: Liu Ying To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, robh+dt@kernel.org, aisheng.dong@nxp.com Subject: [PATCH 5/5] clk: imx: clk-imx8qxp-lpcg: Add some LPCG clocks support for MIPI-LVDS subsystems Date: Wed, 18 Nov 2020 16:31:30 +0800 Message-Id: <1605688290-21805-6-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1605688290-21805-1-git-send-email-victor.liu@nxp.com> References: <1605688290-21805-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR03CA0166.apcprd03.prod.outlook.com (2603:1096:4:c9::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3589.17 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: vzg3dRyhNiq6I4Jtrs3qwmZemnQYHbe7ccwdrm+BtGkJA/mbxHHTJUAkJVNGHavpLSgW9qQe1vOMA5k9QJr86mcUVGGxyQJiOYUdJLtAOni4pCS0SQ6FG/fDvuzNCFHFSyAusVZ1PSkzpaGAg6mpkQ4AeRuXSO2z2WNQFR/8+9wbm+z3MPrEeWoU4otNQCCdsMCIEVlnqkcxPHJXKreAIyF+Uw4/IEnIGD99gZ4OF1cEJ7jXjsli0ReMiKH1lWShRdFY/C3H70Vw/edMg3PN7QH/8l9+Yro3BSRDJFrO5gdSDGE32t6OXgBGHyQGMNpp4tIBYHctpn0fHzNVpaYdLEXJpvJxWlk5LeseSw08YpuDwSilNNtncjzbsSov9BHlPdCTiNEmNhdjMYygBDvHHUPXIDZd6EXEQhlRlGco1YYabTSn8WeIiHTVCB+hB7SNSZsTOjG/6Z/soyVSIMsEq98E2+AU2gCKovbSro8Oe/JdC+H4WDnOtjUsas3I8Fz5v2I24Er/hAHXZdsCJYweAFIaJltzsjxu8ffW35MUQeinABIh2yRf2cbWaN7hCOiGW4P53pesiu4qRyFc0oEUDXdlGXLsSy3QXoVV9B1XdOeMUlYZjTSTCi1aW6ZHayMjCdOhB+yos32mSlcBkjtKRw== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5305ae28-45c5-4cc6-d5b8-08d88b9d614d X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2020 08:38:53.4320 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 64kg31YRYNW7TUn2B7qOV6eOBIJyIfpLD8hugMsSaMYCwOBVrAKFwQfJC4WQWjLUduxJnHxZn4H2A64SzR1HEQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2528 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds some LPCG clocks support for i.MX8qxp MIPI-LVDS subsystems. Cc: Michael Turquette Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Rob Herring Cc: Dong Aisheng Signed-off-by: Liu Ying --- drivers/clk/imx/clk-imx8qxp-lpcg.c | 38 ++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8qxp-lpcg.h | 9 ++++++++ include/dt-bindings/clock/imx8-clock.h | 26 +++++++++++++++++++++++ 3 files changed, 73 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c index 176d426..94c3468 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c @@ -199,6 +199,42 @@ static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = { .num_max = IMX_LSIO_LPCG_CLK_END, }; +static const struct imx8qxp_lpcg_data imx8qxp_lpcg_mipi_lvds_0[] = { + { IMX_MIPI_LVDS_0_LPCG_LIS_IPG_CLK, "mipi_lvds_0_lpcg_lis_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_LIS_LPCG, 16, 0, }, + { IMX_MIPI_LVDS_0_LPCG_DI_REGS_IPG_CLK, "mipi_lvds_0_lpcg_di_regs_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_DI_REGS_LPCG, 16, 0, }, + { IMX_MIPI_LVDS_0_LPCG_GPIO_IPG_CLK, "mipi_lvds_0_lpcg_gpio_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_GPIO_LPCG, 16, 0, }, + { IMX_MIPI_LVDS_0_LPCG_PWM_IPG_MASTER_CLK, "mipi_lvds_0_lpcg_pwm_ipg_master_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_PWM_LPCG, 20, 0, }, + { IMX_MIPI_LVDS_0_LPCG_PWM_IPG_CLK, "mipi_lvds_0_lpcg_pwm_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_PWM_LPCG, 16, 0, }, + { IMX_MIPI_LVDS_0_LPCG_PWM_PER_CLK, "mipi_lvds_0_lpcg_pwm_per_clk", "mipi0_pwm0_clk", 0, MIPI_LVDS_PWM_LPCG, 0, 0, }, + { IMX_MIPI_LVDS_0_LPCG_PWM_32K_CLK, "mipi_lvds_0_lpcg_pwm_32k_clk", "xtal_32KHz", 0, MIPI_LVDS_PWM_LPCG, 4, 0, }, + { IMX_MIPI_LVDS_0_LPCG_I2C0_PER_CLK, "mipi_lvds_0_lpcg_i2c0_per_clk", "mipi0_i2c0_clk", 0, MIPI_LVDS_LPI2C0_LPCG, 0, 0, }, + { IMX_MIPI_LVDS_0_LPCG_I2C0_IPG_CLK, "mipi_lvds_0_lpcg_i2c0_ipg_clk", "mipi_ipg_root_clk", 0, MIPI_LVDS_LPI2C0_LPCG, 16, 0, }, +}; + +static const struct imx8qxp_ss_lpcg imx8qxp_ss_mipi_lvds_0 = { + .lpcg = imx8qxp_lpcg_mipi_lvds_0, + .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_mipi_lvds_0), + .num_max = IMX_MIPI_LVDS_0_LPCG_CLK_END, +}; + +static const struct imx8qxp_lpcg_data imx8qxp_lpcg_mipi_lvds_1[] = { + { IMX_MIPI_LVDS_1_LPCG_LIS_IPG_CLK, "mipi_lvds_1_lpcg_lis_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_LIS_LPCG, 16, 0, }, + { IMX_MIPI_LVDS_1_LPCG_DI_REGS_IPG_CLK, "mipi_lvds_1_lpcg_di_regs_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_DI_REGS_LPCG, 16, 0, }, + { IMX_MIPI_LVDS_1_LPCG_GPIO_IPG_CLK, "mipi_lvds_1_lpcg_gpio_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_GPIO_LPCG, 16, 0, }, + { IMX_MIPI_LVDS_1_LPCG_PWM_IPG_MASTER_CLK, "mipi_lvds_1_lpcg_pwm_ipg_master_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_PWM_LPCG, 20, 0, }, + { IMX_MIPI_LVDS_1_LPCG_PWM_IPG_CLK, "mipi_lvds_1_lpcg_pwm_ipg_clk", "mipi_ipg_clk_root", 0, MIPI_LVDS_PWM_LPCG, 16, 0, }, + { IMX_MIPI_LVDS_1_LPCG_PWM_PER_CLK, "mipi_lvds_1_lpcg_pwm_per_clk", "mipi1_pwm0_clk", 0, MIPI_LVDS_PWM_LPCG, 0, 0, }, + { IMX_MIPI_LVDS_1_LPCG_PWM_32K_CLK, "mipi_lvds_1_lpcg_pwm_32k_clk", "xtal_32KHz", 0, MIPI_LVDS_PWM_LPCG, 4, 0, }, + { IMX_MIPI_LVDS_1_LPCG_I2C0_PER_CLK, "mipi_lvds_1_lpcg_i2c0_per_clk", "mipi1_i2c0_clk", 0, MIPI_LVDS_LPI2C0_LPCG, 0, 0, }, + { IMX_MIPI_LVDS_1_LPCG_I2C0_IPG_CLK, "mipi_lvds_1_lpcg_i2c0_ipg_clk", "mipi_ipg_root_clk", 0, MIPI_LVDS_LPI2C0_LPCG, 16, 0, }, +}; + +static const struct imx8qxp_ss_lpcg imx8qxp_ss_mipi_lvds_1 = { + .lpcg = imx8qxp_lpcg_mipi_lvds_1, + .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_mipi_lvds_1), + .num_max = IMX_MIPI_LVDS_1_LPCG_CLK_END, +}; + #define IMX_LPCG_MAX_CLKS 8 static struct clk_hw *imx_lpcg_of_clk_src_get(struct of_phandle_args *clkspec, @@ -397,6 +433,8 @@ static const struct of_device_id imx8qxp_lpcg_match[] = { { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, }, { .compatible = "fsl,imx8qxp-lpcg-dc", &imx8qxp_ss_dc, }, { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, }, + { .compatible = "fsl,imx8qxp-lpcg-mipi-lvds-0", &imx8qxp_ss_mipi_lvds_0, }, + { .compatible = "fsl,imx8qxp-lpcg-mipi-lvds-1", &imx8qxp_ss_mipi_lvds_1, }, { .compatible = "fsl,imx8qxp-lpcg", NULL }, { /* sentinel */ } }; diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h index e1423a9..1505f9b 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.h +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h @@ -119,4 +119,13 @@ #define DC_PRG7_LPCG 0x44 #define DC_PRG8_LPCG 0x48 +/* MIPI-LVDS SS */ +#define MIPI_LVDS_LIS_LPCG 0x00 +#define MIPI_LVDS_DI_REGS_LPCG 0x04 +#define MIPI_LVDS_GPIO_LPCG 0x08 +#define MIPI_LVDS_PWM_LPCG 0x0c +#define MIPI_LVDS_LPI2C0_LPCG 0x10 +#define MIPI_LVDS_LPI2C1_LPCG 0x14 +#define MIPI_LVDS_MIPI_DSI_LPCG 0x18 + #endif /* _IMX8QXP_LPCG_H */ diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h index c9dd0c6..6922ea9 100644 --- a/include/dt-bindings/clock/imx8-clock.h +++ b/include/dt-bindings/clock/imx8-clock.h @@ -325,4 +325,30 @@ #define IMX_DC0_LPCG_CLK_END 31 +/* MIPI-LVDS0 SS LPCG */ +#define IMX_MIPI_LVDS_0_LPCG_LIS_IPG_CLK 0 +#define IMX_MIPI_LVDS_0_LPCG_DI_REGS_IPG_CLK 1 +#define IMX_MIPI_LVDS_0_LPCG_GPIO_IPG_CLK 2 +#define IMX_MIPI_LVDS_0_LPCG_PWM_IPG_MASTER_CLK 3 +#define IMX_MIPI_LVDS_0_LPCG_PWM_IPG_CLK 4 +#define IMX_MIPI_LVDS_0_LPCG_PWM_PER_CLK 5 +#define IMX_MIPI_LVDS_0_LPCG_PWM_32K_CLK 6 +#define IMX_MIPI_LVDS_0_LPCG_I2C0_PER_CLK 7 +#define IMX_MIPI_LVDS_0_LPCG_I2C0_IPG_CLK 8 + +#define IMX_MIPI_LVDS_0_LPCG_CLK_END 9 + +/* MIPI-LVDS1 SS LPCG */ +#define IMX_MIPI_LVDS_1_LPCG_LIS_IPG_CLK 0 +#define IMX_MIPI_LVDS_1_LPCG_DI_REGS_IPG_CLK 1 +#define IMX_MIPI_LVDS_1_LPCG_GPIO_IPG_CLK 2 +#define IMX_MIPI_LVDS_1_LPCG_PWM_IPG_MASTER_CLK 3 +#define IMX_MIPI_LVDS_1_LPCG_PWM_IPG_CLK 4 +#define IMX_MIPI_LVDS_1_LPCG_PWM_PER_CLK 5 +#define IMX_MIPI_LVDS_1_LPCG_PWM_32K_CLK 6 +#define IMX_MIPI_LVDS_1_LPCG_I2C0_PER_CLK 7 +#define IMX_MIPI_LVDS_1_LPCG_I2C0_IPG_CLK 8 + +#define IMX_MIPI_LVDS_1_LPCG_CLK_END 9 + #endif /* __DT_BINDINGS_CLOCK_IMX_H */