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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id f18sm10180099ill.22.2020.11.16.15.38.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 15:38:15 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 01/11] net: ipa: share field mask values for IPA hash registers Date: Mon, 16 Nov 2020 17:37:55 -0600 Message-Id: <20201116233805.13775-2-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116233805.13775-1-elder@linaro.org> References: <20201116233805.13775-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The IPA filter/routing hash enable register and filter/routing hash flush register each have four single-bit fields representing the four hashed tables to be enabled or flushed. The field positions are identical, so just use a single set of field masks to represent the fields for both registers. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_reg.h | 13 +++++-------- drivers/net/ipa/ipa_table.c | 4 ++-- 2 files changed, 7 insertions(+), 10 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 8eaf5f2096270..001961cd526bc 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -153,10 +153,6 @@ static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) /* The next register is present for IPA v4.2 and above */ #define IPA_REG_FILT_ROUT_HASH_EN_OFFSET 0x00000148 -#define IPV6_ROUTER_HASH_EN GENMASK(0, 0) -#define IPV6_FILTER_HASH_EN GENMASK(4, 4) -#define IPV4_ROUTER_HASH_EN GENMASK(8, 8) -#define IPV4_FILTER_HASH_EN GENMASK(12, 12) static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) { @@ -166,10 +162,11 @@ static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) return 0x000014c; } -#define IPV6_ROUTER_HASH_FLUSH GENMASK(0, 0) -#define IPV6_FILTER_HASH_FLUSH GENMASK(4, 4) -#define IPV4_ROUTER_HASH_FLUSH GENMASK(8, 8) -#define IPV4_FILTER_HASH_FLUSH GENMASK(12, 12) +/* The next four fields are used for the hash enable and flush registers */ +#define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0) +#define IPV6_FILTER_HASH_FMASK GENMASK(4, 4) +#define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) +#define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) #define IPA_REG_BCR_OFFSET 0x000001d0 #define BCR_CMDQ_L_LACK_ONE_ENTRY BIT(0) diff --git a/drivers/net/ipa/ipa_table.c b/drivers/net/ipa/ipa_table.c index b3790aa952a15..32e2d3e052d55 100644 --- a/drivers/net/ipa/ipa_table.c +++ b/drivers/net/ipa/ipa_table.c @@ -422,8 +422,8 @@ int ipa_table_hash_flush(struct ipa *ipa) return -EBUSY; } - val = IPV4_FILTER_HASH_FLUSH | IPV6_FILTER_HASH_FLUSH; - val |= IPV6_ROUTER_HASH_FLUSH | IPV4_ROUTER_HASH_FLUSH; + val = IPV4_FILTER_HASH_FMASK | IPV6_FILTER_HASH_FMASK; + val |= IPV6_ROUTER_HASH_FMASK | IPV4_ROUTER_HASH_FMASK; ipa_cmd_register_write_add(trans, offset, val, val, false); From patchwork Mon Nov 16 23:37:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 324532 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3728283ils; Mon, 16 Nov 2020 15:40:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJyDsyMaDdeuVVSmNbTr9YH8WEvs6C2wKeHb0lLKMXppvQMoVophhcgnTrvH0XbvxRAeIG2o X-Received: by 2002:a17:906:a891:: with SMTP id ha17mr16884693ejb.116.1605570043052; Mon, 16 Nov 2020 15:40:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605570043; cv=none; d=google.com; s=arc-20160816; b=pM+Qd2nSeJdJZglc3nCnxLQtocJDLUBsd0+w+JCu9CuNmccD/3ZtKxgYC3fq1GoygG 2XZ7bDJHA3Q9E4owI8JoGh8BBB7sZkC9lkoFhARroankggn+aU5AXGERpWhzOS4Bgh4o 1OJTBy6BVguCuh/JLglr2mFPg25+7MadhskL0awJQ57Nh2HxTAoSqJqEHJn17FNf8xqE pFCCHPFcmAE+OLxsZFYCR+INwVuxH6DtB0r2lqhIeuGs/9Aj7BKTVpvs7aLqt9hZVcwQ eMIM/SbgnCtvroCgS/tMAMe5nXN8AzFuFS6rKUkl3jOWK/f95gsnVIabXEkBH7Ts+kip HpbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=R/KH1Zx6pvvwlPcex+1v/rVIsHRzuMbIHzVWH/5s1mU=; b=sbblhbBdiMa2gp+Vp1rpfTZv89WQzZf5atPnbT3Y6qZ0pyPskgKbwVbwnAdMTUDcZ5 +207I9Wf8rCyqYggz3n6JcvEe8u6yJUZDY7zPnSTrR5sLkrDG1kU4H3KPDb3NIAhbE1Q ibCdvlkD7mnShGSyuRysQ5m5+I3dQ6mQzqcSkVVa445ieK2dULpgbrFfoXvJBtwPFcEB txpHrwplbzyukRb3j/etQF2AxrVUxOx2FMPNA5jIdYMAFm1oeNz0kNB9EWb1dF2uPEGm +7rx0v0qnacyjEwcOjB1eXnaH8YBjC0WvPh0Qr1KdUHT7p6xsud2qxdB6JbEghy9//H7 NUQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KwtbHymU; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id f18sm10180099ill.22.2020.11.16.15.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 15:38:16 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 02/11] net: ipa: make filter/routing hash enable register variable Date: Mon, 16 Nov 2020 17:37:56 -0600 Message-Id: <20201116233805.13775-3-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116233805.13775-1-elder@linaro.org> References: <20201116233805.13775-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org For IPA v3.5.1, the IPA filter/routing hash enable register actually does exist, but it is at offset 0x8c into the IPA register space. For newer versions of IPA it is at offset 0x148. Define a new inline function ipa_reg_filt_rout_hash_en_offset() to return the appropriate value for a given version of IPA hardware. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_main.c | 9 ++++++--- drivers/net/ipa/ipa_reg.h | 9 +++++++-- 2 files changed, 13 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index bfe95a46acaf1..a9d8597f970aa 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -339,9 +339,12 @@ static void ipa_hardware_config(struct ipa *ipa) val = u32_encode_bits(granularity, AGGR_GRANULARITY); iowrite32(val, ipa->reg_virt + IPA_REG_COUNTER_CFG_OFFSET); - /* Disable hashed IPv4 and IPv6 routing and filtering for IPA v4.2 */ - if (ipa->version == IPA_VERSION_4_2) - iowrite32(0, ipa->reg_virt + IPA_REG_FILT_ROUT_HASH_EN_OFFSET); + /* IPA v4.2 does not support hashed tables, so disable them */ + if (ipa->version == IPA_VERSION_4_2) { + u32 offset = ipa_reg_filt_rout_hash_en_offset(ipa->version); + + iowrite32(0, ipa->reg_virt + offset); + } /* Enable dynamic clock division */ ipa_hardware_dcd_config(ipa); diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 001961cd526bc..b46e60744f57f 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -151,8 +151,13 @@ static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) } /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ -/* The next register is present for IPA v4.2 and above */ -#define IPA_REG_FILT_ROUT_HASH_EN_OFFSET 0x00000148 +static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) +{ + if (version == IPA_VERSION_3_5_1) + return 0x000008c; + + return 0x0000148; +} static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) { From patchwork Mon Nov 16 23:37:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 324524 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3727148ils; Mon, 16 Nov 2020 15:38:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJzi071QQFr7QEoaMBccsqu5QwGA0BR0SDeLSTqOdmQ+5H2cf/McsKw9lXFQtR16NdE6BYO5 X-Received: by 2002:a17:906:81da:: with SMTP id e26mr16401695ejx.491.1605569922305; Mon, 16 Nov 2020 15:38:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605569922; cv=none; d=google.com; s=arc-20160816; b=WX4pOeLZ6FNNf21IMIq7/66xVpEFVvX6ByRVy8FCbeR4BIkwUmy7QIvPZiIZk0J0CO vuGN/awUdrseJ2tBIX4EZVbiA1F1tojvhPGAXMvwftmG5h8tPEZ+S1tuSrFmcqWHNM/r 3wZo8969v8V9BVa4uhUzPKW7P3UzRFVhRMZEa3xAu2M+AKpzTbHTsyddccrbTEZvSZ/9 V0zjRhN1qVGZpH1L+6TLWxPN4QCRXhN5WxY9F+7NSraFX/+NCqTh4oPfon1x4Ok68/3W Dd8HCvqkylHsgAcEPOKuN39Qzj2xUg0zI7viVECmAZqi09NexXGj7O0cgll9wdhf9rkC ZWcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ibvkktNZHObaQcpICoKzhru5nZ1s0dOfq/+z59Thq90=; b=pMEuSQ6Q1tQ+YAzIJ4UXwDSWEAMhBd2Qu8wVla5ZBtQ5IifgNJ6SpjuS175VTCFDQ4 CbiOb1h6s9BXqWeRJB3wS2+aS6VGmKAK9oHKnLV5dDYkDg+PflZssng0cQ742kKXv0Cl 4315ZJpXBhQaCwce0LEVPlOEKpqA/7FPB0XFP82k8zoIRNOohNL5TAP2zUn4nlaPtV3X ZCdo1ZQQWt2xUEVi6w47izSDlhWxt/D12NLxvsoyzhybuIRrcreAAULtOxiCyDRye2bG JZCUI/AUzY/dj4tTnCHGUeNPCg48r+otAZXgEOf5cT35FBt4rXmMNVNsw1N+1o82Ba4j eUlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PRYejMot; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id f18sm10180099ill.22.2020.11.16.15.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 15:38:18 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 03/11] net: ipa: support more versions for HOLB timer Date: Mon, 16 Nov 2020 17:37:57 -0600 Message-Id: <20201116233805.13775-4-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116233805.13775-1-elder@linaro.org> References: <20201116233805.13775-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org IPA version 3.5.1 represents the timer used in avoiding head-of-line blocking with a simple tick count. IPA v4.2 changes that, instead splitting the timer field into two parts (base and scale) to represent the ticks in the timer period. IPA v4.0 and IPA v4.1 use the same method as IPA v3.5.1. Change the test in ipa_reg_init_hol_block_timer_val() so the result is correct for those versions as well. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_endpoint.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 548121b1531b7..3c9bbe2bf81c9 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -665,8 +665,8 @@ static u32 ipa_reg_init_hol_block_timer_val(struct ipa *ipa, u32 microseconds) /* ...but we still need to fit into a 32-bit register */ WARN_ON(ticks > U32_MAX); - /* IPA v3.5.1 just records the tick count */ - if (ipa->version == IPA_VERSION_3_5_1) + /* IPA v3.5.1 through v4.1 just record the tick count */ + if (ipa->version < IPA_VERSION_4_2) return (u32)ticks; /* For IPA v4.2, the tick count is represented by base and From patchwork Mon Nov 16 23:37:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 324533 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3728296ils; Mon, 16 Nov 2020 15:40:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJz4Nu2dAXU2pI75QxUIM3QraNWPCLHT1JlruHAzD+3s8CS0nm9qlPww7RlIElzgxR/uBKxe X-Received: by 2002:a17:906:a891:: with SMTP id ha17mr16884776ejb.116.1605570044567; Mon, 16 Nov 2020 15:40:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605570044; cv=none; d=google.com; s=arc-20160816; b=fo3NsH3t7806oYcqvOm2miS8W+Rkgrh9NrGhi72EM8m8Q0tD9XJ/QmKMjZznCxZ7Ry yZXq1zI3GbbkkbpiKN/APhfbbuvKywWedslLhPJXAcLkawRX23LGQle8ZFo+U8rOZst3 6BRFp/JqwUulbYussCgC3cchutCy3qXhBmdMVQQMruQVM+Zn40qcWJVPzfa9uGyDifwN ccCQYU1rB/yX77wfmwBxoWl+kAftajAInPhCzl20JjyORgAa2xywaXM7U0X/C3tKn/SH XqI70gEKM9ibM9qYXFDk3dgmIbxjQKMRtdxcIgounrvfF4ctn9kFzFMtp5sgPTw5j76p K80w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=miGXLixORMdi7i2E2KGi5NSoYisIYv8Xp9fzXt5c7vw=; b=Okx65iwMfFyW38TPIWrKLJqE5T7ChG1Nj9I/chyHrTO9sRlvBfi6lSpUOZj0brSKc1 u9Lu+Um2JBfLEctR5piipkWpfiOBQKa+cTeYdEoDx9aVI+2/Bn7yqB4cgkeX7FfgTs6S 8rihI0IKxAV5ekVrC6ROnrsAh/7tHOHSZIpd2dUzuXuTC52oU447WY3pkkkVCkBLQAXF XiXnM5DOjZb5hnMecYR/QxoaWs+l4XoBCiUvBrv2TlkF8N4BifSXijAw8jUFguyOVIKx TAQJg5v+pCalj22gpRkRIVSM0U2Xdins5DktZ+fpTx7WHSHu/6whRB06YQyun1mtqb01 Pw8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hviPeDal; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id f18sm10180099ill.22.2020.11.16.15.38.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 15:38:19 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 04/11] net: ipa: fix two inconsistent IPA register names Date: Mon, 16 Nov 2020 17:37:58 -0600 Message-Id: <20201116233805.13775-5-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116233805.13775-1-elder@linaro.org> References: <20201116233805.13775-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Rename two suspend IRQ registers so they follow the IPA_REG_IRQ_xxx naming convention used elsewhere. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_interrupt.c | 6 +++--- drivers/net/ipa/ipa_reg.h | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/ipa_interrupt.c b/drivers/net/ipa/ipa_interrupt.c index cc1ea28f7bc2e..61dd7605bcb66 100644 --- a/drivers/net/ipa/ipa_interrupt.c +++ b/drivers/net/ipa/ipa_interrupt.c @@ -139,12 +139,12 @@ static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt, u32 val; /* assert(mask & ipa->available); */ - val = ioread32(ipa->reg_virt + IPA_REG_SUSPEND_IRQ_EN_OFFSET); + val = ioread32(ipa->reg_virt + IPA_REG_IRQ_SUSPEND_EN_OFFSET); if (enable) val |= mask; else val &= ~mask; - iowrite32(val, ipa->reg_virt + IPA_REG_SUSPEND_IRQ_EN_OFFSET); + iowrite32(val, ipa->reg_virt + IPA_REG_IRQ_SUSPEND_EN_OFFSET); } /* Enable TX_SUSPEND for an endpoint */ @@ -168,7 +168,7 @@ void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt) u32 val; val = ioread32(ipa->reg_virt + IPA_REG_IRQ_SUSPEND_INFO_OFFSET); - iowrite32(val, ipa->reg_virt + IPA_REG_SUSPEND_IRQ_CLR_OFFSET); + iowrite32(val, ipa->reg_virt + IPA_REG_IRQ_SUSPEND_CLR_OFFSET); } /* Simulate arrival of an IPA TX_SUSPEND interrupt */ diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index b46e60744f57f..e24c190665139 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -454,17 +454,17 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) (0x00003030 + 0x1000 * (ee)) /* ipa->available defines the valid bits in the SUSPEND_INFO register */ -#define IPA_REG_SUSPEND_IRQ_EN_OFFSET \ - IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) -#define IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(ee) \ +#define IPA_REG_IRQ_SUSPEND_EN_OFFSET \ + IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(GSI_EE_AP) +#define IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(ee) \ (0x00003034 + 0x1000 * (ee)) -/* ipa->available defines the valid bits in the SUSPEND_IRQ_EN register */ +/* ipa->available defines the valid bits in the IRQ_SUSPEND_EN register */ -#define IPA_REG_SUSPEND_IRQ_CLR_OFFSET \ - IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) -#define IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(ee) \ +#define IPA_REG_IRQ_SUSPEND_CLR_OFFSET \ + IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(GSI_EE_AP) +#define IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(ee) \ (0x00003038 + 0x1000 * (ee)) -/* ipa->available defines the valid bits in the SUSPEND_IRQ_CLR register */ +/* ipa->available defines the valid bits in the IRQ_SUSPEND_CLR register */ /** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ enum ipa_cs_offload_en { From patchwork Mon Nov 16 23:37:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 324525 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3727167ils; Mon, 16 Nov 2020 15:38:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJzFsVDD3TDN6TcIP7gVOWCucuqw1G3IJdP0wEAJBdhcJt70CgfpygpB8cN3Dei/vzQJo47M X-Received: by 2002:a17:906:ad8e:: with SMTP id la14mr13907821ejb.264.1605569923252; Mon, 16 Nov 2020 15:38:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605569923; cv=none; d=google.com; s=arc-20160816; b=YOO7GhsXQ14KxuWcNzxppFgX0UWx1nV4XDZflaotAhe0X3KnAPlAh5sMvcoYwew70V FFk9KtIbbNako0IqLGUOC9UpZXpCAttgclWqBnZ4rAm8/ewCn55fkOKs2M80vpuMz9tw LhLAToeNlVOcTiluWZogUYjZ4ruGltxL6nf0zcNu9nPL4F7TvnnJ40RNZRRGaNuG+JrB xAZbbakBGGjlvcIwaNprKI7gbkR5KJ57knUdYKL4u3MWTb3E2VavE790wGyyG9QLZD5q uebk2jd5gv99s+pqFlhadgkuIt7qEoEYMuVNBnX9DxiFmL1eZurAg5bijwd05Yp0z1xC /h8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ahB8Vs+/9GAyZh/jpoO8CVqISomCaLk8a4aDUbRn4HU=; b=b1K1YHXrJRGmONCr7fGXpjyq0WCTnp7+IPApHkurh99igok4kZ5NjlBP89Jo9oqKKA O3kfSMSt2YKU0ZaoWFIqQj/amOSMivgKKxLgNlv9Mwr/hJoAvecsrmngL/EPdDLAaie6 QTCxGz78NUIO8654H1jMPKJ0c1hWuZ0naKsU2StB81WrxmQ9OyGfHYU56og9D7UYYUdY I6CLcaCovrpaW2IL08hpkzN5GK0aK8RYn3lyRZkta6m45uzWceIzuV4ZBDBl+k1matUM /PgxZSnuawKwFEePhm8J5fV/8Ml6S9xMYMcB/7thfH3k8RUAbtgGyLq9KLk43TBRbANB Xhmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q+cz86dx; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id f18sm10180099ill.22.2020.11.16.15.38.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 15:38:20 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 05/11] net: ipa: use _FMASK consistently Date: Mon, 16 Nov 2020 17:37:59 -0600 Message-Id: <20201116233805.13775-6-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116233805.13775-1-elder@linaro.org> References: <20201116233805.13775-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Several IPA register field masks are defined without the "_FMASK" suffix naming convention. Rename these, so all field masks are consistently named. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_main.c | 6 +++--- drivers/net/ipa/ipa_reg.h | 24 ++++++++++++------------ 2 files changed, 15 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index a9d8597f970aa..3fb9c5d90b70e 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -325,7 +325,7 @@ static void ipa_hardware_config(struct ipa *ipa) /* Disable PA mask to allow HOLB drop (hardware workaround) */ val = ioread32(ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); - val &= ~PA_MASK_EN; + val &= ~PA_MASK_EN_FMASK; iowrite32(val, ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); } @@ -336,7 +336,7 @@ static void ipa_hardware_config(struct ipa *ipa) /* Configure aggregation granularity */ granularity = ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY); - val = u32_encode_bits(granularity, AGGR_GRANULARITY); + val = u32_encode_bits(granularity, AGGR_GRANULARITY_FMASK); iowrite32(val, ipa->reg_virt + IPA_REG_COUNTER_CFG_OFFSET); /* IPA v4.2 does not support hashed tables, so disable them */ @@ -688,7 +688,7 @@ static void ipa_validate_build(void) /* Aggregation granularity value can't be 0, and must fit */ BUILD_BUG_ON(!ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY)); BUILD_BUG_ON(ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY) > - field_max(AGGR_GRANULARITY)); + field_max(AGGR_GRANULARITY_FMASK)); #endif /* IPA_VALIDATE */ } diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index e24c190665139..9e92fe022c6f9 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -203,7 +203,7 @@ static inline u32 ipa_reg_bcr_val(enum ipa_version version) #define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 -#define AGGR_GRANULARITY GENMASK(8, 4) +#define AGGR_GRANULARITY_FMASK GENMASK(8, 4) /* Compute the value to use in the AGGR_GRANULARITY field representing the * given number of microseconds. The value is one less than the number of * timer ticks in the requested period. Zero not a valid granularity value. @@ -215,19 +215,19 @@ static inline u32 ipa_aggr_granularity_val(u32 usec) #define IPA_REG_TX_CFG_OFFSET 0x000001fc /* The first three fields are present for IPA v3.5.1 only */ -#define TX0_PREFETCH_DISABLE GENMASK(0, 0) -#define TX1_PREFETCH_DISABLE GENMASK(1, 1) -#define PREFETCH_ALMOST_EMPTY_SIZE GENMASK(4, 2) +#define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) +#define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) +#define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) /* The next fields are present for IPA v4.0 and above */ -#define PREFETCH_ALMOST_EMPTY_SIZE_TX0 GENMASK(5, 2) -#define DMAW_SCND_OUTSD_PRED_THRESHOLD GENMASK(9, 6) -#define DMAW_SCND_OUTSD_PRED_EN GENMASK(10, 10) -#define DMAW_MAX_BEATS_256_DIS GENMASK(11, 11) -#define PA_MASK_EN GENMASK(12, 12) -#define PREFETCH_ALMOST_EMPTY_SIZE_TX1 GENMASK(16, 13) +#define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) +#define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) +#define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) +#define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) +#define PA_MASK_EN_FMASK GENMASK(12, 12) +#define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) /* The last two fields are present for IPA v4.2 and above */ -#define SSPND_PA_NO_START_STATE GENMASK(18, 18) -#define SSPND_PA_NO_BQ_STATE GENMASK(19, 19) +#define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) +#define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 #define BAM_MAX_PIPES_FMASK GENMASK(4, 0) From patchwork Mon Nov 16 23:38:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 324526 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3727171ils; Mon, 16 Nov 2020 15:38:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJz+ELVQY6vCpNV5g7iiZRVXZlxhdH6L4IgnbU/yU+i2O/BBdPjPrPFRtP9xW4Inz+9bPOeX X-Received: by 2002:a17:906:f752:: with SMTP id jp18mr15933373ejb.331.1605569923604; Mon, 16 Nov 2020 15:38:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605569923; cv=none; d=google.com; s=arc-20160816; b=Po34Pfl3pgadqPHeS167lDaVHNV4G+HnScbmyi4B0I/153BbCzbByht+j0o/zO2ZXn igUFW6KboNWpn4MxFgZbxHAwjU+D0iNY0rYFJRU/VbkZvA5alHXMA2O9yPOgqKyxtoZ3 796qLfHNThMjYlIKjZ29PM2pBRoE7ecYOYk6HkY+IzCR4k/btnL+GFRffFlnxI1rR5LD R913F4xWFWYQoXeUfNKPvFWv5N5q5942868xiVnfxbWpXVonaztpDEov12bUxpgRndwj imqqHKIskUN5/4tjNr9DSoJmyFf45rFzGypXkfjFshivjr4vPlZsh4HrWGrC09VniPTK mz0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZH5sOdTOj86/wQG8Zy+0PJEx+Cikj8yoT/DUHhKt2CM=; b=kEkJ+aNDvPTc4ekZvlFmYQ+A04xc2+JNkZV6N+QkW70wGzHxSn2wtUnYkFzqfBEJZv qWY1cYqPp+5QvqeMuxeMjUmgBzt6MD1ukcB7E2K0DqFgBZcbcLLOtEmdngVQjvZsjvpd e8ahPVSxs/SkakWNZn9CHfRfh5ND9A54t6+DEgiWrJQ67nqoL+L3Ec10bK4Q/EE+4vt+ 99sRNaoyJPPN2R9KK/UsPFMOdP6ymuOXkYo3OAO2ITs0/oJIPdir0d/2vWqatxAEWIZA Pi68V956CGxzGKscUQ/uJiP7VZqvRXXpLeTcRDWeRO8NurLx+F0Q9Q4M5WYe8TXCjs3g gPZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ga5B61Hu; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id f18sm10180099ill.22.2020.11.16.15.38.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 15:38:21 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 06/11] net: ipa: fix BCR register field definitions Date: Mon, 16 Nov 2020 17:38:00 -0600 Message-Id: <20201116233805.13775-7-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116233805.13775-1-elder@linaro.org> References: <20201116233805.13775-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The backward compatibility register field masks are defined using single-bit masks defined with BIT(x) rather than GENMASK(x, x). Change this one set of definitions to follow the GENMASK() pattern used everywhere else. Add a few missing field definitions for this register as well. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_reg.h | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 9e92fe022c6f9..a05684785e577 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -174,22 +174,35 @@ static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) #define IPA_REG_BCR_OFFSET 0x000001d0 -#define BCR_CMDQ_L_LACK_ONE_ENTRY BIT(0) -#define BCR_TX_NOT_USING_BRESP BIT(1) -#define BCR_SUSPEND_L2_IRQ BIT(3) -#define BCR_HOLB_DROP_L2_IRQ BIT(4) -#define BCR_DUAL_TX BIT(5) +/* The next two fields are not present for IPA v4.2 */ +#define BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK GENMASK(0, 0) +#define BCR_TX_NOT_USING_BRESP_FMASK GENMASK(1, 1) +/* The next field is invalid for IPA v4.1 */ +#define BCR_TX_SUSPEND_IRQ_ASSERT_ONCE_FMASK GENMASK(2, 2) +/* The next two fields are not present for IPA v4.2 */ +#define BCR_SUSPEND_L2_IRQ_FMASK GENMASK(3, 3) +#define BCR_HOLB_DROP_L2_IRQ_FMASK GENMASK(4, 4) +#define BCR_DUAL_TX_FMASK GENMASK(5, 5) +#define BCR_ENABLE_FILTER_DATA_CACHE_FMASK GENMASK(6, 6) +#define BCR_NOTIF_PRIORITY_OVER_ZLT_FMASK GENMASK(7, 7) +#define BCR_FILTER_PREFETCH_EN_FMASK GENMASK(8, 8) +#define BCR_ROUTER_PREFETCH_EN_FMASK GENMASK(9, 9) /* Backward compatibility register value to use for each version */ static inline u32 ipa_reg_bcr_val(enum ipa_version version) { if (version == IPA_VERSION_3_5_1) - return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_TX_NOT_USING_BRESP | - BCR_SUSPEND_L2_IRQ | BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX; + return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | + BCR_TX_NOT_USING_BRESP_FMASK | + BCR_SUSPEND_L2_IRQ_FMASK | + BCR_HOLB_DROP_L2_IRQ_FMASK | + BCR_DUAL_TX_FMASK; if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1) - return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_SUSPEND_L2_IRQ | - BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX; + return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | + BCR_SUSPEND_L2_IRQ_FMASK | + BCR_HOLB_DROP_L2_IRQ_FMASK | + BCR_DUAL_TX_FMASK; return 0x00000000; } From patchwork Mon Nov 16 23:38:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 324528 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3727187ils; Mon, 16 Nov 2020 15:38:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJy9qbr+Of85TJ56UmlqSgF1YBuxkrIo+GGNFlFHUggUexIBIieldBCQh5oITsr+phoH2dWP X-Received: by 2002:a17:906:2b4e:: with SMTP id b14mr18103120ejg.354.1605569924704; Mon, 16 Nov 2020 15:38:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605569924; cv=none; d=google.com; s=arc-20160816; b=ZqML8DL1BK6UH25HLS/y7HaNqDyQ9Kd3LbZKxyjzs0INE6NcuFp3IyHtgcN580RKgq 0QpYlUdEeEMqmHxq3m8WjTbnM5cgA1EYjXTE6dd8LosRoe8uq8yEUvC1JIpJCxRTDK4d lpOKiyxbokK+gwpRwRi6TUJ8IUDM6qudQIO+xQVO7I3mOWQnRBN83S0cmia+V47T8rXe v7UngpFqipg1HLmUYP6RUjgBOa7DVj/t+CFiXMxrS/3n53DU398VnM6GxhgFgI5kf2bx eu8NNJjEpAK7ugmSwXrLg0qD3WC2I831KQbAqrBTenW35Y2cnbV863t3kbEmKnwDET+7 AtYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5GWeNKnEAfbeU0hlToQQvZDeaFXUCPIWMIn5c6zgFUw=; b=PofNOdTivXJGci2kh4cJdX5CSnA20Zh3zSZzVoRN3f7z3xN6FgQaHQyv8wHAqQ/NEO wAHY1IGc10Ya2lw//kNtbmoskowQNKHwnnNEb3mg1yHgAIXJ5K2a4UVeP055WEqGoKgL IL1kE1FFfv/h3Al95SHZMS/VZfZYOx6syXHIlU9dNXZd/rW9H3zt7yTaTA9nCMVVjDh0 RuPWUKpHdZni8jmhumsi5sedy7wiPbXB0ErW/nlPb9Vmd+seq7jP7cCc1iOlV5llfWPq hr6aKNWc+Z2NAktbKcBRBXqJTIUY/5PclMmTYTsymiiOCcLeDl3onCO/0FSxYkBabe7X UoQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e+pGys2Z; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id f18sm10180099ill.22.2020.11.16.15.38.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 15:38:22 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 07/11] net: ipa: define enumerated types consistently Date: Mon, 16 Nov 2020 17:38:01 -0600 Message-Id: <20201116233805.13775-8-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116233805.13775-1-elder@linaro.org> References: <20201116233805.13775-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Consistently define numeric values for enumerated type members using hexidecimal (rather than decimal) format values. Align the values assigned in the same column in each file. Only assign values where they really matter, for example don't assign IPA_ENDPOINT_AP_MODEM_TX the value 0. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.h | 20 +++++++++--------- drivers/net/ipa/gsi_reg.h | 25 ++++++++++++++++------- drivers/net/ipa/ipa_cmd.c | 6 +++--- drivers/net/ipa/ipa_cmd.h | 21 +++++++++---------- drivers/net/ipa/ipa_endpoint.h | 2 +- drivers/net/ipa/ipa_interrupt.h | 6 +++--- drivers/net/ipa/ipa_qmi_msg.h | 12 +++++------ drivers/net/ipa/ipa_reg.h | 36 ++++++++++++++++----------------- drivers/net/ipa/ipa_uc.c | 36 ++++++++++++++++----------------- 9 files changed, 87 insertions(+), 77 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/gsi.h b/drivers/net/ipa/gsi.h index 758125737c8e9..ecc784e3a8127 100644 --- a/drivers/net/ipa/gsi.h +++ b/drivers/net/ipa/gsi.h @@ -33,10 +33,10 @@ struct ipa_gsi_endpoint_data; /* Execution environment IDs */ enum gsi_ee_id { - GSI_EE_AP = 0, - GSI_EE_MODEM = 1, - GSI_EE_UC = 2, - GSI_EE_TZ = 3, + GSI_EE_AP = 0x0, + GSI_EE_MODEM = 0x1, + GSI_EE_UC = 0x2, + GSI_EE_TZ = 0x3, }; struct gsi_ring { @@ -96,12 +96,12 @@ struct gsi_trans_info { /* Hardware values signifying the state of a channel */ enum gsi_channel_state { - GSI_CHANNEL_STATE_NOT_ALLOCATED = 0x0, - GSI_CHANNEL_STATE_ALLOCATED = 0x1, - GSI_CHANNEL_STATE_STARTED = 0x2, - GSI_CHANNEL_STATE_STOPPED = 0x3, - GSI_CHANNEL_STATE_STOP_IN_PROC = 0x4, - GSI_CHANNEL_STATE_ERROR = 0xf, + GSI_CHANNEL_STATE_NOT_ALLOCATED = 0x0, + GSI_CHANNEL_STATE_ALLOCATED = 0x1, + GSI_CHANNEL_STATE_STARTED = 0x2, + GSI_CHANNEL_STATE_STOPPED = 0x3, + GSI_CHANNEL_STATE_STOP_IN_PROC = 0x4, + GSI_CHANNEL_STATE_ERROR = 0xf, }; /* We only care about channels between IPA and AP */ diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index 8e3a7ffd19479..c1799d1e8a837 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -71,6 +71,7 @@ #define ERINDEX_FMASK GENMASK(18, 14) #define CHSTATE_FMASK GENMASK(23, 20) #define ELEMENT_SIZE_FMASK GENMASK(31, 24) + /** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */ enum gsi_channel_type { GSI_CHANNEL_TYPE_MHI = 0x0, @@ -223,6 +224,7 @@ enum gsi_channel_type { (0x0001f008 + 0x4000 * (ee)) #define CH_CHID_FMASK GENMASK(7, 0) #define CH_OPCODE_FMASK GENMASK(31, 24) + /** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */ enum gsi_ch_cmd_opcode { GSI_CH_ALLOCATE = 0x0, @@ -238,6 +240,7 @@ enum gsi_ch_cmd_opcode { (0x0001f010 + 0x4000 * (ee)) #define EV_CHID_FMASK GENMASK(7, 0) #define EV_OPCODE_FMASK GENMASK(31, 24) + /** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */ enum gsi_evt_cmd_opcode { GSI_EVT_ALLOCATE = 0x0, @@ -252,6 +255,7 @@ enum gsi_evt_cmd_opcode { #define GENERIC_OPCODE_FMASK GENMASK(4, 0) #define GENERIC_CHID_FMASK GENMASK(9, 5) #define GENERIC_EE_FMASK GENMASK(13, 10) + /** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */ enum gsi_generic_cmd_opcode { GSI_GENERIC_HALT_CHANNEL = 0x1, @@ -275,6 +279,7 @@ enum gsi_generic_cmd_opcode { /* Fields below are present for IPA v4.2 and above */ #define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) #define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) + /** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */ enum gsi_iram_size { IRAM_SIZE_ONE_KB = 0x0, @@ -293,15 +298,16 @@ enum gsi_iram_size { GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ (0x0001f088 + 0x4000 * (ee)) + /* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */ enum gsi_irq_type_id { - GSI_CH_CTRL = 0, /* channel allocation, etc. */ - GSI_EV_CTRL = 1, /* event ring allocation, etc. */ - GSI_GLOB_EE = 2, /* global/general event */ - GSI_IEOB = 3, /* TRE completion */ - GSI_INTER_EE_CH_CTRL = 4, /* remote-issued stop/reset (unused) */ - GSI_INTER_EE_EV_CTRL = 5, /* remote-issued event reset (unused) */ - GSI_GENERAL = 6, /* general-purpose event */ + GSI_CH_CTRL = 0x0, /* channel allocation, etc. */ + GSI_EV_CTRL = 0x1, /* event ring allocation, etc. */ + GSI_GLOB_EE = 0x2, /* global/general event */ + GSI_IEOB = 0x3, /* TRE completion */ + GSI_INTER_EE_CH_CTRL = 0x4, /* remote-issued stop/reset (unused) */ + GSI_INTER_EE_EV_CTRL = 0x5, /* remote-issued event reset (unused) */ + GSI_GENERAL = 0x6, /* general-purpose event */ }; #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ @@ -406,6 +412,7 @@ enum gsi_general_id { #define ERR_VIRT_IDX_FMASK GENMASK(23, 19) #define ERR_TYPE_FMASK GENMASK(27, 24) #define ERR_EE_FMASK GENMASK(31, 28) + /** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */ enum gsi_err_code { GSI_INVALID_TRE = 0x1, @@ -417,6 +424,7 @@ enum gsi_err_code { /* 7 is not assigned */ GSI_HWO_1 = 0x8, }; + /** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */ enum gsi_err_type { GSI_ERR_TYPE_GLOB = 0x1, @@ -435,6 +443,8 @@ enum gsi_err_type { (0x0001f400 + 0x4000 * (ee)) #define INTER_EE_RESULT_FMASK GENMASK(2, 0) #define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) + +/** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */ enum gsi_generic_ee_result { GENERIC_EE_SUCCESS = 0x1, GENERIC_EE_CHANNEL_NOT_RUNNING = 0x2, @@ -444,6 +454,7 @@ enum gsi_generic_ee_result { GENERIC_EE_RETRY = 0x6, GENERIC_EE_NO_RESOURCES = 0x7, }; + #define USB_MAX_PACKET_FMASK GENMASK(15, 15) /* 0: HS; 1: SS */ #define MHI_BASE_CHANNEL_FMASK GENMASK(31, 24) diff --git a/drivers/net/ipa/ipa_cmd.c b/drivers/net/ipa/ipa_cmd.c index d92dd3f09b735..002e514485100 100644 --- a/drivers/net/ipa/ipa_cmd.c +++ b/drivers/net/ipa/ipa_cmd.c @@ -38,9 +38,9 @@ /* Some commands can wait until indicated pipeline stages are clear */ enum pipeline_clear_options { - pipeline_clear_hps = 0, - pipeline_clear_src_grp = 1, - pipeline_clear_full = 2, + pipeline_clear_hps = 0x0, + pipeline_clear_src_grp = 0x1, + pipeline_clear_full = 0x2, }; /* IPA_CMD_IP_V{4,6}_{FILTER,ROUTING}_INIT */ diff --git a/drivers/net/ipa/ipa_cmd.h b/drivers/net/ipa/ipa_cmd.h index f7e6f87facf79..4ed09c486abc1 100644 --- a/drivers/net/ipa/ipa_cmd.h +++ b/drivers/net/ipa/ipa_cmd.h @@ -27,16 +27,16 @@ struct gsi_channel; * a request is *not* an immediate command. */ enum ipa_cmd_opcode { - IPA_CMD_NONE = 0, - IPA_CMD_IP_V4_FILTER_INIT = 3, - IPA_CMD_IP_V6_FILTER_INIT = 4, - IPA_CMD_IP_V4_ROUTING_INIT = 7, - IPA_CMD_IP_V6_ROUTING_INIT = 8, - IPA_CMD_HDR_INIT_LOCAL = 9, - IPA_CMD_REGISTER_WRITE = 12, - IPA_CMD_IP_PACKET_INIT = 16, - IPA_CMD_DMA_SHARED_MEM = 19, - IPA_CMD_IP_PACKET_TAG_STATUS = 20, + IPA_CMD_NONE = 0x0, + IPA_CMD_IP_V4_FILTER_INIT = 0x3, + IPA_CMD_IP_V6_FILTER_INIT = 0x4, + IPA_CMD_IP_V4_ROUTING_INIT = 0x7, + IPA_CMD_IP_V6_ROUTING_INIT = 0x8, + IPA_CMD_HDR_INIT_LOCAL = 0x9, + IPA_CMD_REGISTER_WRITE = 0xc, + IPA_CMD_IP_PACKET_INIT = 0x10, + IPA_CMD_DMA_SHARED_MEM = 0x13, + IPA_CMD_IP_PACKET_TAG_STATUS = 0x14, }; /** @@ -50,7 +50,6 @@ struct ipa_cmd_info { enum dma_data_direction direction; }; - #ifdef IPA_VALIDATE /** diff --git a/drivers/net/ipa/ipa_endpoint.h b/drivers/net/ipa/ipa_endpoint.h index 58a245de488e8..881ecc27bd6e3 100644 --- a/drivers/net/ipa/ipa_endpoint.h +++ b/drivers/net/ipa/ipa_endpoint.h @@ -25,7 +25,7 @@ struct ipa_gsi_endpoint_data; #define IPA_MTU ETH_DATA_LEN enum ipa_endpoint_name { - IPA_ENDPOINT_AP_MODEM_TX = 0, + IPA_ENDPOINT_AP_MODEM_TX, IPA_ENDPOINT_MODEM_LAN_TX, IPA_ENDPOINT_MODEM_COMMAND_TX, IPA_ENDPOINT_AP_COMMAND_TX, diff --git a/drivers/net/ipa/ipa_interrupt.h b/drivers/net/ipa/ipa_interrupt.h index 727e9c5044d1e..b59e03a9f8e7f 100644 --- a/drivers/net/ipa/ipa_interrupt.h +++ b/drivers/net/ipa/ipa_interrupt.h @@ -22,9 +22,9 @@ struct ipa_interrupt; * for an AP RX endpoint whose underlying GSI channel is suspended/stopped. */ enum ipa_irq_id { - IPA_IRQ_UC_0 = 2, - IPA_IRQ_UC_1 = 3, - IPA_IRQ_TX_SUSPEND = 14, + IPA_IRQ_UC_0 = 0x2, + IPA_IRQ_UC_1 = 0x3, + IPA_IRQ_TX_SUSPEND = 0xe, IPA_IRQ_COUNT, /* Number of interrupt types (not an index) */ }; diff --git a/drivers/net/ipa/ipa_qmi_msg.h b/drivers/net/ipa/ipa_qmi_msg.h index cfac456cea0ca..12b6621f4b0e6 100644 --- a/drivers/net/ipa/ipa_qmi_msg.h +++ b/drivers/net/ipa/ipa_qmi_msg.h @@ -74,12 +74,12 @@ struct ipa_init_complete_ind { /* The AP tells the modem its platform type. We assume Android. */ enum ipa_platform_type { - IPA_QMI_PLATFORM_TYPE_INVALID = 0, /* Invalid */ - IPA_QMI_PLATFORM_TYPE_TN = 1, /* Data card */ - IPA_QMI_PLATFORM_TYPE_LE = 2, /* Data router */ - IPA_QMI_PLATFORM_TYPE_MSM_ANDROID = 3, /* Android MSM */ - IPA_QMI_PLATFORM_TYPE_MSM_WINDOWS = 4, /* Windows MSM */ - IPA_QMI_PLATFORM_TYPE_MSM_QNX_V01 = 5, /* QNX MSM */ + IPA_QMI_PLATFORM_TYPE_INVALID = 0x0, /* Invalid */ + IPA_QMI_PLATFORM_TYPE_TN = 0x1, /* Data card */ + IPA_QMI_PLATFORM_TYPE_LE = 0x2, /* Data router */ + IPA_QMI_PLATFORM_TYPE_MSM_ANDROID = 0x3, /* Android MSM */ + IPA_QMI_PLATFORM_TYPE_MSM_WINDOWS = 0x4, /* Windows MSM */ + IPA_QMI_PLATFORM_TYPE_MSM_QNX_V01 = 0x5, /* QNX MSM */ }; /* This defines the start and end offset of a range of memory. Both diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index a05684785e577..4bc00d30ff774 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -481,36 +481,36 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) /** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ enum ipa_cs_offload_en { - IPA_CS_OFFLOAD_NONE = 0, - IPA_CS_OFFLOAD_UL = 1, - IPA_CS_OFFLOAD_DL = 2, - IPA_CS_RSVD + IPA_CS_OFFLOAD_NONE = 0x0, + IPA_CS_OFFLOAD_UL = 0x1, + IPA_CS_OFFLOAD_DL = 0x2, + IPA_CS_RSVD = 0x3, }; /** enum ipa_aggr_en - aggregation enable field in ENDP_INIT_AGGR_N */ enum ipa_aggr_en { - IPA_BYPASS_AGGR = 0, - IPA_ENABLE_AGGR = 1, - IPA_ENABLE_DEAGGR = 2, + IPA_BYPASS_AGGR = 0x0, + IPA_ENABLE_AGGR = 0x1, + IPA_ENABLE_DEAGGR = 0x2, }; /** enum ipa_aggr_type - aggregation type field in in_ENDP_INIT_AGGR_N */ enum ipa_aggr_type { - IPA_MBIM_16 = 0, - IPA_HDLC = 1, - IPA_TLP = 2, - IPA_RNDIS = 3, - IPA_GENERIC = 4, - IPA_COALESCE = 5, - IPA_QCMAP = 6, + IPA_MBIM_16 = 0x0, + IPA_HDLC = 0x1, + IPA_TLP = 0x2, + IPA_RNDIS = 0x3, + IPA_GENERIC = 0x4, + IPA_COALESCE = 0x5, + IPA_QCMAP = 0x6, }; /** enum ipa_mode - mode field in ENDP_INIT_MODE_N */ enum ipa_mode { - IPA_BASIC = 0, - IPA_ENABLE_FRAMING_HDLC = 1, - IPA_ENABLE_DEFRAMING_HDLC = 2, - IPA_DMA = 3, + IPA_BASIC = 0x0, + IPA_ENABLE_FRAMING_HDLC = 0x1, + IPA_ENABLE_DEFRAMING_HDLC = 0x2, + IPA_DMA = 0x3, }; /** diff --git a/drivers/net/ipa/ipa_uc.c b/drivers/net/ipa/ipa_uc.c index 15bb357f3cfb1..be55f8a192d16 100644 --- a/drivers/net/ipa/ipa_uc.c +++ b/drivers/net/ipa/ipa_uc.c @@ -86,32 +86,32 @@ struct ipa_uc_mem_area { /** enum ipa_uc_command - commands from the AP to the microcontroller */ enum ipa_uc_command { - IPA_UC_COMMAND_NO_OP = 0, - IPA_UC_COMMAND_UPDATE_FLAGS = 1, - IPA_UC_COMMAND_DEBUG_RUN_TEST = 2, - IPA_UC_COMMAND_DEBUG_GET_INFO = 3, - IPA_UC_COMMAND_ERR_FATAL = 4, - IPA_UC_COMMAND_CLK_GATE = 5, - IPA_UC_COMMAND_CLK_UNGATE = 6, - IPA_UC_COMMAND_MEMCPY = 7, - IPA_UC_COMMAND_RESET_PIPE = 8, - IPA_UC_COMMAND_REG_WRITE = 9, - IPA_UC_COMMAND_GSI_CH_EMPTY = 10, + IPA_UC_COMMAND_NO_OP = 0x0, + IPA_UC_COMMAND_UPDATE_FLAGS = 0x1, + IPA_UC_COMMAND_DEBUG_RUN_TEST = 0x2, + IPA_UC_COMMAND_DEBUG_GET_INFO = 0x3, + IPA_UC_COMMAND_ERR_FATAL = 0x4, + IPA_UC_COMMAND_CLK_GATE = 0x5, + IPA_UC_COMMAND_CLK_UNGATE = 0x6, + IPA_UC_COMMAND_MEMCPY = 0x7, + IPA_UC_COMMAND_RESET_PIPE = 0x8, + IPA_UC_COMMAND_REG_WRITE = 0x9, + IPA_UC_COMMAND_GSI_CH_EMPTY = 0xa, }; /** enum ipa_uc_response - microcontroller response codes */ enum ipa_uc_response { - IPA_UC_RESPONSE_NO_OP = 0, - IPA_UC_RESPONSE_INIT_COMPLETED = 1, - IPA_UC_RESPONSE_CMD_COMPLETED = 2, - IPA_UC_RESPONSE_DEBUG_GET_INFO = 3, + IPA_UC_RESPONSE_NO_OP = 0x0, + IPA_UC_RESPONSE_INIT_COMPLETED = 0x1, + IPA_UC_RESPONSE_CMD_COMPLETED = 0x2, + IPA_UC_RESPONSE_DEBUG_GET_INFO = 0x3, }; /** enum ipa_uc_event - common cpu events reported by the microcontroller */ enum ipa_uc_event { - IPA_UC_EVENT_NO_OP = 0, - IPA_UC_EVENT_ERROR = 1, - IPA_UC_EVENT_LOG_INFO = 2, + IPA_UC_EVENT_NO_OP = 0x0, + IPA_UC_EVENT_ERROR = 0x1, + IPA_UC_EVENT_LOG_INFO = 0x2, }; static struct ipa_uc_mem_area *ipa_uc_shared(struct ipa *ipa) From patchwork Mon Nov 16 23:38:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 324531 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3727228ils; Mon, 16 Nov 2020 15:38:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJzpyNA1r3MWzm7NgEmGnL8TTXwXeTd33ebfCuB1btk6jYmpgXHVHqjvNkpaXdZvlaUUT6ow X-Received: by 2002:a17:906:3a17:: with SMTP id z23mr8836963eje.332.1605569928541; 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id f18sm10180099ill.22.2020.11.16.15.38.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 15:38:23 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 08/11] net: ipa: fix up IPA register comments Date: Mon, 16 Nov 2020 17:38:02 -0600 Message-Id: <20201116233805.13775-9-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116233805.13775-1-elder@linaro.org> References: <20201116233805.13775-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Revise or add comments in "ipa_reg.h" for to provide more information, and to improve clarity and consistency. - Always provide a comment to define when a register or field is supported (or not) for certain versions of IPA hardware. - Try to be specific about *which* or *how many* definitions a comment refers to. - Move comments stating that ipa->available defines the valid bits in various registers *above* the register offset definition, to avoid some checkpatch.pl warnings. No code is changed by this patch. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_reg.h | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 4bc00d30ff774..08473e513477f 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -67,12 +67,14 @@ struct ipa; #define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038 +/* The next field is not supported for IPA v4.1 */ #define IPA_REG_COMP_CFG_OFFSET 0x0000003c #define ENABLE_FMASK GENMASK(0, 0) #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) +/* The remaining fields are not present for IPA v3.5.1 */ #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) @@ -110,6 +112,7 @@ struct ipa; #define TX_0_FMASK GENMASK(19, 19) #define TX_1_FMASK GENMASK(20, 20) #define FNR_FMASK GENMASK(21, 21) +/* The remaining fields are not present for IPA v3.5.1 */ #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) #define AGGR_WRAPPER_FMASK GENMASK(23, 23) #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) @@ -138,10 +141,11 @@ struct ipa; #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) -/* The next two fields are present for IPA v4.0 and above */ +/* The next two fields are not present for IPA v3.5.1 */ #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) +/* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) { if (version == IPA_VERSION_3_5_1) @@ -149,7 +153,6 @@ static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) return 0x000000b4; } -/* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) { @@ -207,10 +210,11 @@ static inline u32 ipa_reg_bcr_val(enum ipa_version version) return 0x00000000; } +/* The value of the next register must be a multiple of 8 */ #define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8 -#define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ +#define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec /* The internal inactivity timer clock is used for the aggregation timer */ #define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ @@ -231,14 +235,14 @@ static inline u32 ipa_aggr_granularity_val(u32 usec) #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) -/* The next fields are present for IPA v4.0 and above */ +/* The next six fields are present for IPA v4.0 and above */ #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) #define PA_MASK_EN_FMASK GENMASK(12, 12) #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) -/* The last two fields are present for IPA v4.2 and above */ +/* The next two fields are present for IPA v4.2 only */ #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) @@ -308,13 +312,16 @@ static inline u32 ipa_resource_group_dst_count(enum ipa_version version) (0x00000504 + 0x0020 * (rt)) #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ (0x00000508 + 0x0020 * (rt)) +/* The next four fields are used for all resource group registers */ #define X_MIN_LIM_FMASK GENMASK(5, 0) #define X_MAX_LIM_FMASK GENMASK(13, 8) +/* The next two fields are not always present (if resource count is odd) */ #define Y_MIN_LIM_FMASK GENMASK(21, 16) #define Y_MAX_LIM_FMASK GENMASK(29, 24) #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ (0x00000800 + 0x0070 * (ep)) +/* The next field should only used for IPA v3.5.1 */ #define ENDP_SUSPEND_FMASK GENMASK(0, 0) #define ENDP_DELAY_FMASK GENMASK(1, 1) @@ -379,7 +386,7 @@ static inline u32 ipa_resource_group_dst_count(enum ipa_version version) /* Valid only for RX (IPA producer) endpoints */ #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ (0x00000830 + 0x0070 * (rxep)) -/* The next fields are present for IPA v4.2 only */ +/* The next two fields are present for IPA v4.2 only */ #define BASE_VALUE_FMASK GENMASK(4, 0) #define SCALE_FMASK GENMASK(12, 8) @@ -417,10 +424,10 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) #define STATUS_EN_FMASK GENMASK(0, 0) #define STATUS_ENDP_FMASK GENMASK(5, 1) #define STATUS_LOCATION_FMASK GENMASK(8, 8) -/* The next field is present for IPA v4.0 and above */ +/* The next field is not present for IPA v3.5.1 */ #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) -/* "er" is either an endpoint ID (for filters) or a route ID (for routes) */ +/* The next register is only present for IPA versions that support hashing */ #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ (0x0000085c + 0x0070 * (er)) #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) @@ -461,23 +468,23 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) #define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \ (0x0000301c + 0x1000 * (ee)) +/* ipa->available defines the valid bits in the SUSPEND_INFO register */ #define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \ IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP) #define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \ (0x00003030 + 0x1000 * (ee)) -/* ipa->available defines the valid bits in the SUSPEND_INFO register */ +/* ipa->available defines the valid bits in the IRQ_SUSPEND_EN register */ #define IPA_REG_IRQ_SUSPEND_EN_OFFSET \ IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(GSI_EE_AP) #define IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(ee) \ (0x00003034 + 0x1000 * (ee)) -/* ipa->available defines the valid bits in the IRQ_SUSPEND_EN register */ +/* ipa->available defines the valid bits in the IRQ_SUSPEND_CLR register */ #define IPA_REG_IRQ_SUSPEND_CLR_OFFSET \ IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(GSI_EE_AP) #define IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(ee) \ (0x00003038 + 0x1000 * (ee)) -/* ipa->available defines the valid bits in the IRQ_SUSPEND_CLR register */ /** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ enum ipa_cs_offload_en { From patchwork Mon Nov 16 23:38:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 324527 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3727192ils; Mon, 16 Nov 2020 15:38:45 -0800 (PST) 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id f18sm10180099ill.22.2020.11.16.15.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 15:38:24 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 09/11] net: ipa: rearrange a few IPA register definitions Date: Mon, 16 Nov 2020 17:38:03 -0600 Message-Id: <20201116233805.13775-10-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116233805.13775-1-elder@linaro.org> References: <20201116233805.13775-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Move a few things around in "ipa_reg.h": - Move the definition of ipa_reg_state_aggr_active_offset() down a bit in the file so definitions are ordered by offset (for the lowest supported IPA version) like all other definitions. - Move the definition TIMER_FREQUENCY to be immediately above the definition of ipa_aggr_granularity_val() where it's used. - Move each register field value enumerated type definition to immediately follow the definitions of the register and field it is associated with. No code functionality is modified by this patch. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_reg.h | 147 +++++++++++++++++++------------------- 1 file changed, 74 insertions(+), 73 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 08473e513477f..94b54b2f660f6 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -145,15 +145,6 @@ struct ipa; #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) -/* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ -static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) -{ - if (version == IPA_VERSION_3_5_1) - return 0x0000010c; - - return 0x000000b4; -} - static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) { if (version == IPA_VERSION_3_5_1) @@ -176,6 +167,15 @@ static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) +/* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ +static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) +{ + if (version == IPA_VERSION_3_5_1) + return 0x0000010c; + + return 0x000000b4; +} + #define IPA_REG_BCR_OFFSET 0x000001d0 /* The next two fields are not present for IPA v4.2 */ #define BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK GENMASK(0, 0) @@ -216,14 +216,15 @@ static inline u32 ipa_reg_bcr_val(enum ipa_version version) /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec -/* The internal inactivity timer clock is used for the aggregation timer */ -#define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ - #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) + +/* The internal inactivity timer clock is used for the aggregation timer */ +#define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ + /* Compute the value to use in the AGGR_GRANULARITY field representing the * given number of microseconds. The value is one less than the number of - * timer ticks in the requested period. Zero not a valid granularity value. + * timer ticks in the requested period. 0 not a valid granularity value. */ static inline u32 ipa_aggr_granularity_val(u32 usec) { @@ -332,6 +333,14 @@ static inline u32 ipa_resource_group_dst_count(enum ipa_version version) #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) +/** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ +enum ipa_cs_offload_en { + IPA_CS_OFFLOAD_NONE = 0x0, + IPA_CS_OFFLOAD_UL = 0x1, + IPA_CS_OFFLOAD_DL = 0x2, + IPA_CS_RSVD = 0x3, +}; + #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ (0x00000810 + 0x0070 * (ep)) #define HDR_LEN_FMASK GENMASK(5, 0) @@ -367,6 +376,14 @@ static inline u32 ipa_resource_group_dst_count(enum ipa_version version) #define PAD_EN_FMASK GENMASK(29, 29) #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) +/** enum ipa_mode - mode field in ENDP_INIT_MODE_N */ +enum ipa_mode { + IPA_BASIC = 0x0, + IPA_ENABLE_FRAMING_HDLC = 0x1, + IPA_ENABLE_DEFRAMING_HDLC = 0x2, + IPA_DMA = 0x3, +}; + #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ (0x00000824 + 0x0070 * (ep)) #define AGGR_EN_FMASK GENMASK(1, 0) @@ -378,6 +395,24 @@ static inline u32 ipa_resource_group_dst_count(enum ipa_version version) #define AGGR_FORCE_CLOSE_FMASK GENMASK(22, 22) #define AGGR_HARD_BYTE_LIMIT_ENABLE_FMASK GENMASK(24, 24) +/** enum ipa_aggr_en - aggregation enable field in ENDP_INIT_AGGR_N */ +enum ipa_aggr_en { + IPA_BYPASS_AGGR = 0x0, + IPA_ENABLE_AGGR = 0x1, + IPA_ENABLE_DEAGGR = 0x2, +}; + +/** enum ipa_aggr_type - aggregation type field in ENDP_INIT_AGGR_N */ +enum ipa_aggr_type { + IPA_MBIM_16 = 0x0, + IPA_HDLC = 0x1, + IPA_TLP = 0x2, + IPA_RNDIS = 0x3, + IPA_GENERIC = 0x4, + IPA_COALESCE = 0x5, + IPA_QCMAP = 0x6, +}; + /* Valid only for RX (IPA producer) endpoints */ #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ (0x0000082c + 0x0070 * (rxep)) @@ -419,6 +454,32 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) #define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8) #define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12) +/** + * enum ipa_seq_type - HPS and DPS sequencer type fields in ENDP_INIT_SEQ_N + * @IPA_SEQ_DMA_ONLY: only DMA is performed + * @IPA_SEQ_PKT_PROCESS_NO_DEC_UCP: + * packet processing + no decipher + microcontroller (Ethernet Bridging) + * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP: + * second packet processing pass + no decipher + microcontroller + * @IPA_SEQ_DMA_DEC: DMA + cipher/decipher + * @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression + * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: + * packet processing + no decipher + no uCP + HPS REP DMA parser + * @IPA_SEQ_INVALID: invalid sequencer type + * + * The values defined here are broken into 4-bit nibbles that are written + * into fields of the INIT_SEQ_N endpoint registers. + */ +enum ipa_seq_type { + IPA_SEQ_DMA_ONLY = 0x0000, + IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002, + IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004, + IPA_SEQ_DMA_DEC = 0x0011, + IPA_SEQ_DMA_COMP_DECOMP = 0x0020, + IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806, + IPA_SEQ_INVALID = 0xffff, +}; + #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ (0x00000840 + 0x0070 * (ep)) #define STATUS_EN_FMASK GENMASK(0, 0) @@ -486,66 +547,6 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) #define IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(ee) \ (0x00003038 + 0x1000 * (ee)) -/** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ -enum ipa_cs_offload_en { - IPA_CS_OFFLOAD_NONE = 0x0, - IPA_CS_OFFLOAD_UL = 0x1, - IPA_CS_OFFLOAD_DL = 0x2, - IPA_CS_RSVD = 0x3, -}; - -/** enum ipa_aggr_en - aggregation enable field in ENDP_INIT_AGGR_N */ -enum ipa_aggr_en { - IPA_BYPASS_AGGR = 0x0, - IPA_ENABLE_AGGR = 0x1, - IPA_ENABLE_DEAGGR = 0x2, -}; - -/** enum ipa_aggr_type - aggregation type field in in_ENDP_INIT_AGGR_N */ -enum ipa_aggr_type { - IPA_MBIM_16 = 0x0, - IPA_HDLC = 0x1, - IPA_TLP = 0x2, - IPA_RNDIS = 0x3, - IPA_GENERIC = 0x4, - IPA_COALESCE = 0x5, - IPA_QCMAP = 0x6, -}; - -/** enum ipa_mode - mode field in ENDP_INIT_MODE_N */ -enum ipa_mode { - IPA_BASIC = 0x0, - IPA_ENABLE_FRAMING_HDLC = 0x1, - IPA_ENABLE_DEFRAMING_HDLC = 0x2, - IPA_DMA = 0x3, -}; - -/** - * enum ipa_seq_type - HPS and DPS sequencer type fields in in ENDP_INIT_SEQ_N - * @IPA_SEQ_DMA_ONLY: only DMA is performed - * @IPA_SEQ_PKT_PROCESS_NO_DEC_UCP: - * packet processing + no decipher + microcontroller (Ethernet Bridging) - * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP: - * second packet processing pass + no decipher + microcontroller - * @IPA_SEQ_DMA_DEC: DMA + cipher/decipher - * @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression - * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: - * packet processing + no decipher + no uCP + HPS REP DMA parser - * @IPA_SEQ_INVALID: invalid sequencer type - * - * The values defined here are broken into 4-bit nibbles that are written - * into fields of the INIT_SEQ_N endpoint registers. - */ -enum ipa_seq_type { - IPA_SEQ_DMA_ONLY = 0x0000, - IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002, - IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004, - IPA_SEQ_DMA_DEC = 0x0011, - IPA_SEQ_DMA_COMP_DECOMP = 0x0020, - IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806, - IPA_SEQ_INVALID = 0xffff, -}; - int ipa_reg_init(struct ipa *ipa); void ipa_reg_exit(struct ipa *ipa); From patchwork Mon Nov 16 23:38:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 324530 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3727231ils; Mon, 16 Nov 2020 15:38:49 -0800 (PST) X-Google-Smtp-Source: ABdhPJwuvTYKxC9KVFUe4Nq+7QMdkzJXKa7LebpksFHJHyYvg43bezGM05VGgn6jPknQ9yLXQ1Ig X-Received: by 2002:a17:906:1c87:: with SMTP id g7mr12620765ejh.37.1605569928956; Mon, 16 Nov 2020 15:38:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605569928; cv=none; d=google.com; s=arc-20160816; b=h7YT3Rb0gBmT63Yv+fAgN9iChhTusDnqC1mjTJ1smWsOhTm0ClcB/lTmucwhnJVrRX h6upnv8XWNiW0hKBnsbFIZ6ZiwPijHpboNqsinvGeIJYBqXoOTonASls1jO+DOjtq08+ Q8m2sXD7n+4R6tjVIlVg0D0uo/v4KOiXq5ABzzhQ4j6JjpGLP9YykhK9NGORdg2JmoYH erOYKHxb2pX5GBPFS/tso4myy/0M8ZK8XDzhsPx+pu6BFaFoTzS4a90KRarOvrQNSqf9 oiU0Aw3y9fS9p5+163Gpy0MiDa17cCDU82JAWHpJpsQfE2RGuEXsC9SmAMjMTr8Q/uWo f/MQ== ARC-Message-Signature: i=1; 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id f18sm10180099ill.22.2020.11.16.15.38.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 15:38:25 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 10/11] net: ipa: move definition of enum ipa_irq_id Date: Mon, 16 Nov 2020 17:38:04 -0600 Message-Id: <20201116233805.13775-11-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116233805.13775-1-elder@linaro.org> References: <20201116233805.13775-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Move the definition of the ipa_irq_id enumerated type out of "ipa_interrupt.h" and into "ipa_reg.h", and flesh out its set of defined values. Each interrupt id indicates a particular type of IPA interrupt that can be signaled. Their numeric values define bit positions in the IPA_IRQ_* registers, so should their definitions should accompany the definition of those register offsets. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_interrupt.h | 16 -------------- drivers/net/ipa/ipa_reg.h | 37 +++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 16 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/ipa_interrupt.h b/drivers/net/ipa/ipa_interrupt.h index b59e03a9f8e7f..b5d63a0cd19e4 100644 --- a/drivers/net/ipa/ipa_interrupt.h +++ b/drivers/net/ipa/ipa_interrupt.h @@ -12,22 +12,6 @@ struct ipa; struct ipa_interrupt; -/** - * enum ipa_irq_id - IPA interrupt type - * @IPA_IRQ_UC_0: Microcontroller event interrupt - * @IPA_IRQ_UC_1: Microcontroller response interrupt - * @IPA_IRQ_TX_SUSPEND: Data ready interrupt - * - * The data ready interrupt is signaled if data has arrived that is destined - * for an AP RX endpoint whose underlying GSI channel is suspended/stopped. - */ -enum ipa_irq_id { - IPA_IRQ_UC_0 = 0x2, - IPA_IRQ_UC_1 = 0x3, - IPA_IRQ_TX_SUSPEND = 0xe, - IPA_IRQ_COUNT, /* Number of interrupt types (not an index) */ -}; - /** * typedef ipa_irq_handler_t - IPA interrupt handler function type * @ipa: IPA pointer diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 94b54b2f660f6..a3c1300b680bb 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -523,6 +523,43 @@ enum ipa_seq_type { IPA_REG_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) #define IPA_REG_IRQ_CLR_EE_N_OFFSET(ee) \ (0x00003010 + 0x1000 * (ee)) +/** + * enum ipa_irq_id - Bit positions representing type of IPA IRQ + * @IPA_IRQ_UC_0: Microcontroller event interrupt + * @IPA_IRQ_UC_1: Microcontroller response interrupt + * @IPA_IRQ_TX_SUSPEND: Data ready interrupt + * + * IRQ types not described above are not currently used. + */ +enum ipa_irq_id { + IPA_IRQ_BAD_SNOC_ACCESS = 0x0, + /* Type (bit) 0x1 is not defined */ + IPA_IRQ_UC_0 = 0x2, + IPA_IRQ_UC_1 = 0x3, + IPA_IRQ_UC_2 = 0x4, + IPA_IRQ_UC_3 = 0x5, + IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, + IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, + IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, + IPA_IRQ_RX_ERR = 0x9, + IPA_IRQ_DEAGGR_ERR = 0xa, + IPA_IRQ_TX_ERR = 0xb, + IPA_IRQ_STEP_MODE = 0xc, + IPA_IRQ_PROC_ERR = 0xd, + IPA_IRQ_TX_SUSPEND = 0xe, + IPA_IRQ_TX_HOLB_DROP = 0xf, + IPA_IRQ_BAM_GSI_IDLE = 0x10, + IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, + IPA_IRQ_PIPE_RED_BELOW = 0x12, + IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, + IPA_IRQ_PIPE_RED_ABOVE = 0x14, + IPA_IRQ_UCP = 0x15, + IPA_IRQ_DCMP = 0x16, + IPA_IRQ_GSI_EE = 0x17, + IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, + IPA_IRQ_GSI_UC = 0x19, + IPA_IRQ_COUNT, /* Last; not an id */ +}; #define IPA_REG_IRQ_UC_OFFSET \ IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP) From patchwork Mon Nov 16 23:38:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 324529 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3727199ils; Mon, 16 Nov 2020 15:38:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJzNENr3mf4RTU+l5ZXXaXd9cp6lNJW7V05RTVq6c9HB6CRvYwc6lNHGSiO16FnmipGa36zB X-Received: by 2002:a17:906:f0d4:: with SMTP id dk20mr16341222ejb.180.1605569925751; Mon, 16 Nov 2020 15:38:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605569925; cv=none; d=google.com; s=arc-20160816; b=v4N31B/Y5RAFrL+H6BgATpNarhWdwO7cWB6lnadDK7XaZk8l1G8Jk4FiFg8nNkKToo iqZJXexli2Ettly0u/g1joYcQk26QIOUyiyfGqaOVt+6rkuccFMftVI4PonFt7nlbhLk Bhh1KaE0VmHFRCZY/oNgKxnGBF8CoZ8z/S1gu0s7H7LMow5nr0Y+W2uyDhBffvBqFrl9 CnQbWNdGhtKYuYBKFB3PpYOztBentFdh5DHfYH4qup2Fks486mGEwe6e2VsfvTVig5la sgEQNDJZZPwmVlPyOgepaqxHwZwJjK5v7jlR7dRKSRO0r+NVopVQHNB4qQc1gCHBgwXN Ejqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gPSHm2IegGABhxbsjS6ulWC/OyRLSfppgHa9K5huxaw=; b=0y1Uf774M5vbo9v1fDf89xVNJYHHMUdCrge83GaJ3ZIX6dRngtz9B6vgshBh2AbHK3 3qYq2JgZbMOIs32PnJKoiEshc7vDbjKQKqXxrZVJLCgSbKQtCDAXSKmvHVqB68r1MQ// 3Wm/9oQBhR5aD9t209wtYQHd3WYNaipEdlDbhufvxkYeJM1gcKmL/cVaLdFWV69K2OZk j5lwPgJ773y1cVMyy6GYoUbOGfzwwiwY9/OVkd7AuBWNA2ZfrJFPOoUCSGSams1PeHLk YHOYKdO/KHGLEy+ar0+E0GzZjd8RhuG5QhF2Q3SKHCcd/HJ4P1ScLeMP5GaJDokuLSHT a+kQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qx7o6o1X; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id f18sm10180099ill.22.2020.11.16.15.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 15:38:26 -0800 (PST) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 11/11] net: ipa: a few last IPA register cleanups Date: Mon, 16 Nov 2020 17:38:05 -0600 Message-Id: <20201116233805.13775-12-elder@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116233805.13775-1-elder@linaro.org> References: <20201116233805.13775-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Some last cleanups for the existing IPA register definitions: - Remove the definition of IPA_REG_ENABLED_PIPES_OFFSET, because it is not used. - Use "IPA_" instead of "BAM_" as the prefix on fields associated with the FLAVOR_0 register. We use GSI (not BAM), but the fields apply to both GSI and BAM. - Get rid of the definition of IPA_CS_RSVD; it is never used. - Add two missing field mask definitions for the INIT_DEAGGR endpoint register. - Eliminate a few of the defined sequencer types, because they are unused. We can add them back when needed. - Add a field mask to indicate which bit causes an interrupt on the microcontroller. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_endpoint.c | 6 +++--- drivers/net/ipa/ipa_reg.h | 21 +++++++-------------- drivers/net/ipa/ipa_uc.c | 7 ++++++- 3 files changed, 16 insertions(+), 18 deletions(-) -- 2.20.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 3c9bbe2bf81c9..9707300457517 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -1545,8 +1545,8 @@ int ipa_endpoint_config(struct ipa *ipa) val = ioread32(ipa->reg_virt + IPA_REG_FLAVOR_0_OFFSET); /* Our RX is an IPA producer */ - rx_base = u32_get_bits(val, BAM_PROD_LOWEST_FMASK); - max = rx_base + u32_get_bits(val, BAM_MAX_PROD_PIPES_FMASK); + rx_base = u32_get_bits(val, IPA_PROD_LOWEST_FMASK); + max = rx_base + u32_get_bits(val, IPA_MAX_PROD_PIPES_FMASK); if (max > IPA_ENDPOINT_MAX) { dev_err(dev, "too many endpoints (%u > %u)\n", max, IPA_ENDPOINT_MAX); @@ -1555,7 +1555,7 @@ int ipa_endpoint_config(struct ipa *ipa) rx_mask = GENMASK(max - 1, rx_base); /* Our TX is an IPA consumer */ - max = u32_get_bits(val, BAM_MAX_CONS_PIPES_FMASK); + max = u32_get_bits(val, IPA_MAX_CONS_PIPES_FMASK); tx_mask = GENMASK(max - 1, 0); ipa->available = rx_mask | tx_mask; diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index a3c1300b680bb..d02e7ecc6fc01 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -65,8 +65,6 @@ struct ipa; * of valid bits for the register. */ -#define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038 - /* The next field is not supported for IPA v4.1 */ #define IPA_REG_COMP_CFG_OFFSET 0x0000003c #define ENABLE_FMASK GENMASK(0, 0) @@ -248,10 +246,10 @@ static inline u32 ipa_aggr_granularity_val(u32 usec) #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 -#define BAM_MAX_PIPES_FMASK GENMASK(4, 0) -#define BAM_MAX_CONS_PIPES_FMASK GENMASK(12, 8) -#define BAM_MAX_PROD_PIPES_FMASK GENMASK(20, 16) -#define BAM_PROD_LOWEST_FMASK GENMASK(27, 24) +#define IPA_MAX_PIPES_FMASK GENMASK(3, 0) +#define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8) +#define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16) +#define IPA_PROD_LOWEST_FMASK GENMASK(27, 24) static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) { @@ -338,7 +336,6 @@ enum ipa_cs_offload_en { IPA_CS_OFFLOAD_NONE = 0x0, IPA_CS_OFFLOAD_UL = 0x1, IPA_CS_OFFLOAD_DL = 0x2, - IPA_CS_RSVD = 0x3, }; #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ @@ -429,8 +426,10 @@ enum ipa_aggr_type { #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ (0x00000834 + 0x0070 * (txep)) #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) +#define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6) #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) +#define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14) #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ @@ -457,12 +456,8 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) /** * enum ipa_seq_type - HPS and DPS sequencer type fields in ENDP_INIT_SEQ_N * @IPA_SEQ_DMA_ONLY: only DMA is performed - * @IPA_SEQ_PKT_PROCESS_NO_DEC_UCP: - * packet processing + no decipher + microcontroller (Ethernet Bridging) * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP: * second packet processing pass + no decipher + microcontroller - * @IPA_SEQ_DMA_DEC: DMA + cipher/decipher - * @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: * packet processing + no decipher + no uCP + HPS REP DMA parser * @IPA_SEQ_INVALID: invalid sequencer type @@ -472,10 +467,7 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) */ enum ipa_seq_type { IPA_SEQ_DMA_ONLY = 0x0000, - IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002, IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004, - IPA_SEQ_DMA_DEC = 0x0011, - IPA_SEQ_DMA_COMP_DECOMP = 0x0020, IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806, IPA_SEQ_INVALID = 0xffff, }; @@ -565,6 +557,7 @@ enum ipa_irq_id { IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP) #define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \ (0x0000301c + 0x1000 * (ee)) +#define UC_INTR_FMASK GENMASK(0, 0) /* ipa->available defines the valid bits in the SUSPEND_INFO register */ #define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \ diff --git a/drivers/net/ipa/ipa_uc.c b/drivers/net/ipa/ipa_uc.c index be55f8a192d16..dee58a6596d41 100644 --- a/drivers/net/ipa/ipa_uc.c +++ b/drivers/net/ipa/ipa_uc.c @@ -192,14 +192,19 @@ void ipa_uc_teardown(struct ipa *ipa) static void send_uc_command(struct ipa *ipa, u32 command, u32 command_param) { struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa); + u32 val; + /* Fill in the command data */ shared->command = command; shared->command_param = cpu_to_le32(command_param); shared->command_param_hi = 0; shared->response = 0; shared->response_param = 0; - iowrite32(1, ipa->reg_virt + IPA_REG_IRQ_UC_OFFSET); + /* Use an interrupt to tell the microcontroller the command is ready */ + val = u32_encode_bits(1, UC_INTR_FMASK); + + iowrite32(val, ipa->reg_virt + IPA_REG_IRQ_UC_OFFSET); } /* Tell the microcontroller the AP is shutting down */