From patchwork Mon Nov 16 17:31:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 324428 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3500457ils; Mon, 16 Nov 2020 09:33:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJzX2r3W9yG4UzvE5EhNSO8/qKQGdVCKovQkle5TVs+XG+k6vxtRzEo6t2FJ5CXZg0ipxfjv X-Received: by 2002:a17:906:2490:: with SMTP id e16mr15646096ejb.17.1605548024816; Mon, 16 Nov 2020 09:33:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605548024; cv=none; d=google.com; s=arc-20160816; b=Y8Go730q2hgXXp4U/LTEVQRyFor+9nn1ytBO0oD3sBThlhh5XLQijM8FOPEDVDGAZ7 GKoNfH0Fw5acQY7WXz+Ve20MB2Xbl69HfNfjsei9ajq4meKY8Lf9fme//L+YjruzLgOT 5DcxLS+6HdF2Qex8b9F7ZZMx7QyqqAQGShJuQcYmTwE2Suv50cMfjpLYnGWp3gWKp8GS X/4C48lwsifWV0zGa0Qf82HOafMeMi3+YaGS++xsFoMCOEFrf5SF4C++Rgxv37YEDypk MD5fKffVDccWsYnpC/yB6X7eDXyvpXS6jgceePTDY8aHmROIB5BY44ExFDS0CBMXH8/Q 7zLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=GZExXsRLvqMiQlQNpytBoDxxK38wVDimWDB7JTCI/Bk=; b=lh8P7YI7LzF5kjC1P1KQ4g5fW6RHCZq71u4J9i4MT7NQ3nkunv0+gvLZL2KiY0bMld pLs02xfC2MI1T1yw5KvYV/0MkcuEOWQV0izNX93yxJsBHx+X4H0Zqxa8HEkR6uu4+jK8 n1sNtJAT8mOGaTZyKkHc8e9MkQjjQ5DS6X7aDDKvSqRgOnYD0xYUUl31AOoTLy7su8IY j1q6jYxZ+thEQFTGVWzxUylduhuKhREnVJDGBf5n/sZ62qjJJGq0wwFQMx/FIzcnkh0V Gm4N74fGHYY0G1RRktY7JCXhqntdmFipo9I5zDbStcZDcHcS2Wf4LctHA5h82q6h6n8V 1BAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wKO8KmS6; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e20si11928278eja.480.2020.11.16.09.33.44; Mon, 16 Nov 2020 09:33:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wKO8KmS6; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733054AbgKPRcP (ORCPT + 3 others); Mon, 16 Nov 2020 12:32:15 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:44200 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733056AbgKPRcO (ORCPT ); Mon, 16 Nov 2020 12:32:14 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0AGHW5EF011992; Mon, 16 Nov 2020 11:32:05 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1605547925; bh=GZExXsRLvqMiQlQNpytBoDxxK38wVDimWDB7JTCI/Bk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wKO8KmS6Zo3PsOlHtnYz0/Ky5j0cQGQJlhYVhNqZPbJzaeIF5CY3apunk/Y+b7bdQ EHCbn69vckc75T3LiD3mtNRaECFHjCeGDxUe9iQiRgNHsi+tW4aD+3GEkcgeRWAwXJ Z3VVX9iBC0qCcBca/0hU65GIfMJ4CLyLN7DlbWYU= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0AGHW4w3002064 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Nov 2020 11:32:05 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 16 Nov 2020 11:32:04 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 16 Nov 2020 11:32:04 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0AGHVgJH030552; Mon, 16 Nov 2020 11:32:00 -0600 From: Kishon Vijay Abraham I To: Tero Kristo , Nishanth Menon , Rob Herring , Tom Joseph , Lorenzo Pieralisi , Bjorn Helgaas CC: , Kishon Vijay Abraham I , , , , Subject: [PATCH 2/3] PCI: j721e: Get offset within "syscon" from "ti, syscon-pcie-ctrl" phandle arg Date: Mon, 16 Nov 2020 23:01:40 +0530 Message-ID: <20201116173141.31873-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201116173141.31873-1-kishon@ti.com> References: <20201116173141.31873-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Get "syscon" pcie_ctrl offset from the argument of "ti,syscon-pcie-ctrl" phandle. Previously a subnode to "syscon" node was added which has the exact memory mapped address of pcie_ctrl but now the offset of pcie_ctrl within "syscon" is now being passed as argument to "ti,syscon-pcie-ctrl" phandle. Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pci-j721e.c | 28 +++++++++++++++------- 1 file changed, 19 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 586b9d69fa5e..d615e6313252 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -153,7 +154,8 @@ static const struct cdns_pcie_ops j721e_pcie_ops = { .link_up = j721e_pcie_link_up, }; -static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) +static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, + unsigned int offset) { struct device *dev = pcie->dev; u32 mask = J721E_MODE_RC; @@ -164,7 +166,7 @@ static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) if (mode == PCI_MODE_RC) val = J721E_MODE_RC; - ret = regmap_update_bits(syscon, 0, mask, val); + ret = regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set pcie mode\n"); @@ -172,7 +174,7 @@ static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) } static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, - struct regmap *syscon) + struct regmap *syscon, unsigned int offset) { struct device *dev = pcie->dev; struct device_node *np = dev->of_node; @@ -185,7 +187,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, link_speed = 2; val = link_speed - 1; - ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val); + ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); if (ret) dev_err(dev, "failed to set link speed\n"); @@ -193,7 +195,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, } static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, - struct regmap *syscon) + struct regmap *syscon, unsigned int offset) { struct device *dev = pcie->dev; u32 lanes = pcie->num_lanes; @@ -201,7 +203,7 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, int ret; val = LANE_COUNT(lanes - 1); - ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val); + ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); if (ret) dev_err(dev, "failed to set link count\n"); @@ -212,6 +214,7 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) { struct device *dev = pcie->dev; struct device_node *node = dev->of_node; + struct of_phandle_args args; struct regmap *syscon; int ret; @@ -221,19 +224,26 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) return PTR_ERR(syscon); } - ret = j721e_pcie_set_mode(pcie, syscon); + ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, + 0, &args); + if (ret) { + dev_err(dev, "failed to parse ti,syscon-pcie-ctrl\n"); + return ret; + } + + ret = j721e_pcie_set_mode(pcie, syscon, args.args[0]); if (ret < 0) { dev_err(dev, "Failed to set pci mode\n"); return ret; } - ret = j721e_pcie_set_link_speed(pcie, syscon); + ret = j721e_pcie_set_link_speed(pcie, syscon, args.args[0]); if (ret < 0) { dev_err(dev, "Failed to set link speed\n"); return ret; } - ret = j721e_pcie_set_lane_count(pcie, syscon); + ret = j721e_pcie_set_lane_count(pcie, syscon, args.args[0]); if (ret < 0) { dev_err(dev, "Failed to set num-lanes\n"); return ret; From patchwork Mon Nov 16 17:31:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 324429 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3500495ils; Mon, 16 Nov 2020 09:33:46 -0800 (PST) X-Google-Smtp-Source: ABdhPJwkK/0Z5kYyPOctgCvjaA6VZmmEKdSooQDLOCrV0u6fst/2JlML8OnSlZII9PnJzGTMev5P X-Received: by 2002:a17:906:3daa:: with SMTP id y10mr15197244ejh.23.1605548026684; Mon, 16 Nov 2020 09:33:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605548026; cv=none; d=google.com; s=arc-20160816; b=RBwz0LJ25hQMDIXTlchFnnr1RQSRBuJuVGFF/VpEUEBuJJyG8f6r5yRe75i4vRnNPC Llw4jdQ7gIffqPnYXXz7s28bmHtYOwDZosvDlniCy+MRrZqYkdnIbJTy6ZNI+QvVQmFi nH+V8O0Rr5B0bt3TU16XfyvYWd1tJ78fqzSIMJl1FNRF4TPxjh1u1yJNdwWoBv2UFdE8 K7FQqElipUByD83zTZlKjyKTP2GPOfGM6H83y8ikEEKfd0+iqjZccCPjX/jU4d3BO36O FhYaLerawqxmdmQlA+vR+OzjEm7DN/t2oXyQPwzoOkPeG+bAW+77kGExIzg9QKvyybPY lLbQ== ARC-Message-Signature: i=1; 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Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 48 ++++------------------- 1 file changed, 8 insertions(+), 40 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 620e69e42974..23a0024dda79 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -28,38 +28,6 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - pcie0_ctrl: syscon@4070 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004070 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4070 0x4070 0x4>; - }; - - pcie1_ctrl: syscon@4074 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004074 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4074 0x4074 0x4>; - }; - - pcie2_ctrl: syscon@4078 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004078 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4078 0x4078 0x4>; - }; - - pcie3_ctrl: syscon@407c { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x0000407c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x407c 0x407c 0x4>; - }; - serdes_ln_ctrl: mux@4080 { compatible = "mmio-mux"; reg = <0x00004080 0x50>; @@ -619,7 +587,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -646,7 +614,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -668,7 +636,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -695,7 +663,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -717,7 +685,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -744,7 +712,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie2_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -766,7 +734,7 @@ interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; @@ -793,7 +761,7 @@ reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&pcie3_ctrl>; + ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;