From patchwork Sun Nov 8 18:51:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 321302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81809C56202 for ; Sun, 8 Nov 2020 18:52:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 47B472076E for ; Sun, 8 Nov 2020 18:52:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=walle.cc header.i=@walle.cc header.b="RO01Jkhd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728783AbgKHSv1 (ORCPT ); Sun, 8 Nov 2020 13:51:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728770AbgKHSv1 (ORCPT ); Sun, 8 Nov 2020 13:51:27 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A15DEC0613CF; Sun, 8 Nov 2020 10:51:26 -0800 (PST) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 6B30D23E55; Sun, 8 Nov 2020 19:51:24 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1604861484; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rQFbSNbCC4d8HsUblJnVNTAfkx/7jXh2YNcs4HFInSI=; b=RO01JkhdETuFgEcI3uS2fKcUslY/N+zmEN3k6N/CHKSI8XwRJ9EZRzX5DZEHAKKOWC3qdR 1mLjJjjytZXCU81x/NXwrn+28ioIHFGOOGsxYY1304Axsa1TaaMvSnKb72PKx3RPXfPoA/ QJ71NQGuh8BsuuLxdd5UgujoT9xmiS4= From: Michael Walle To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Li Yang , "Y . b . Lu" , Xiaowei Bao , Ashish Kumar , Vladimir Oltean , Michael Walle Subject: [PATCH v3 1/9] arm64: dts: ls1028a: fix ENETC PTP clock input Date: Sun, 8 Nov 2020 19:51:05 +0100 Message-Id: <20201108185113.31377-2-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201108185113.31377-1-michael@walle.cc> References: <20201108185113.31377-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On the LS1028A the ENETC reference clock is connected to 4th HWA output, see Figure 7 "Clock subsystem block diagram". The PHC may run with a wrong frequency. ptp_qoriq_auto_config() will read the clock speed of the clock given in the device tree. It is likely that, on the reference board this wasn't noticed because both clocks have the same frequency. But this must not be always the case. Fix it. Fixes: 49401003e260 ("arm64: dts: fsl: ls1028a: add ENETC 1588 timer node") Signed-off-by: Michael Walle --- Changes since v2: - new patch arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 2c831d814572..e22f29aa4658 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -961,7 +961,7 @@ ethernet@0,4 { compatible = "fsl,enetc-ptp"; reg = <0x000400 0 0 0 0>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen 2 3>; little-endian; fsl,extts-fifo; }; From patchwork Sun Nov 8 18:51:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 321303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84AA8C55ABD for ; Sun, 8 Nov 2020 18:51:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4C6FE20773 for ; Sun, 8 Nov 2020 18:51:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=walle.cc header.i=@walle.cc header.b="e75+iNV6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728879AbgKHSvs (ORCPT ); Sun, 8 Nov 2020 13:51:48 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:46625 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728854AbgKHSva (ORCPT ); Sun, 8 Nov 2020 13:51:30 -0500 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 6CD6D23E6F; Sun, 8 Nov 2020 19:51:27 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1604861487; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vO5z6bNFh8p9WfUjnOgafQ0jJFzSGzWQXf8Tg6kwf5I=; b=e75+iNV6f4tZTiHklhGdR2andvnC8WcUf34rOoCFej83KVD/DP9wn5qmbay6Jv23h19slX ME5/G1DhMZ2fHnknL2BqY7iv7AbSDJYx2NdB7VIqJNmaodh235gPRv4E7t+Ltm3EcMKTAG eb8cYvcroo/b51yTyEGDa17xNXogckg= From: Michael Walle To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Li Yang , "Y . b . Lu" , Xiaowei Bao , Ashish Kumar , Vladimir Oltean , Michael Walle , Rob Herring Subject: [PATCH v3 6/9] dt-bindings: clock: document the fsl-flexspi-clk driver Date: Sun, 8 Nov 2020 19:51:10 +0100 Message-Id: <20201108185113.31377-7-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201108185113.31377-1-michael@walle.cc> References: <20201108185113.31377-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Michael Walle Reviewed-by: Rob Herring --- Changes since v2: - none Changes since v1: - new patch .../bindings/clock/fsl,flexspi-clock.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml new file mode 100644 index 000000000000..1fa390ee7b9b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,flexspi-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale FlexSPI clock driver for Layerscape SoCs + +maintainers: + - Michael Walle + +description: + The Freescale Layerscape SoCs have a special FlexSPI clock which is + derived from the platform PLL. + +properties: + compatible: + enum: + - fsl,ls1028a-flexspi-clk + - fsl,lx2160a-flexspi-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + dcfg { + #address-cells = <1>; + #size-cells = <1>; + + fspi_clk: clock-controller@900 { + compatible = "fsl,ls1028a-flexspi-clk"; + reg = <0x900 0x4>; + #clock-cells = <0>; + clocks = <&parentclk>; + clock-output-names = "fspi_clk"; + }; + }; From patchwork Sun Nov 8 18:51:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 321304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DBCEC56202 for ; Sun, 8 Nov 2020 18:51:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D7F1221D40 for ; Sun, 8 Nov 2020 18:51:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=walle.cc header.i=@walle.cc header.b="Ho1OkZVY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728947AbgKHSvn (ORCPT ); Sun, 8 Nov 2020 13:51:43 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:55223 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728879AbgKHSvb (ORCPT ); Sun, 8 Nov 2020 13:51:31 -0500 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 8BD6F23E5B; Sun, 8 Nov 2020 19:51:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1604861488; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dNkpy43+hIFFCsfsdbjxvE/UUo6ri9ye43CWs2O33dI=; b=Ho1OkZVY1TDTA3IHM1wUrhm6k1lQj54AHB/5XEHJmirNCfyZH3rA6jqfGhipVd4Nnz1HU/ 07sC5w4e15qRfjaNkpBFhQKpg49wAsptfIPw/Y628xDX1xk9MLC2eyWn/ivfpZfQPDOcxx 2cpL9jyT/igrQkZZaGM5c8tOFKjblls= From: Michael Walle To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Li Yang , "Y . b . Lu" , Xiaowei Bao , Ashish Kumar , Vladimir Oltean , Michael Walle Subject: [PATCH v3 8/9] arm64: dts: ls1028a: fix FlexSPI clock Date: Sun, 8 Nov 2020 19:51:12 +0100 Message-Id: <20201108185113.31377-9-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201108185113.31377-1-michael@walle.cc> References: <20201108185113.31377-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that we have a proper driver for the FlexSPI interface use it. This will fix SCK frequency switching on Layerscape SoCs. This was tested on the Kontron sl28 board. Signed-off-by: Michael Walle --- Changes since v2: - use device tree constants for clockgen - also use &fspi_clk for fspi_en clock Changes since v1: - none arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 055da2c710c3..8f2f2e2ab87d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -207,9 +207,20 @@ }; dcfg: syscon@1e00000 { - compatible = "fsl,ls1028a-dcfg", "syscon"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; reg = <0x0 0x1e00000 0x0 0x10000>; + ranges = <0x0 0x0 0x1e00000 0x10000>; little-endian; + + fspi_clk: clock-controller@900 { + compatible = "fsl,ls1028a-flexspi-clk"; + reg = <0x900 0x4>; + #clock-cells = <0>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; + clock-output-names = "fspi_clk"; + }; }; rst: syscon@1e60000 { @@ -327,8 +338,7 @@ <0x0 0x20000000 0x0 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; interrupts = ; - clocks = <&clockgen QORIQ_CLK_HWACCEL 0>, - <&clockgen QORIQ_CLK_HWACCEL 0>; + clocks = <&fspi_clk>, <&fspi_clk>; clock-names = "fspi_en", "fspi"; status = "disabled"; }; From patchwork Sun Nov 8 18:51:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 321305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73949C4742C for ; Sun, 8 Nov 2020 18:51:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 37ADC2076E for ; Sun, 8 Nov 2020 18:51:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=walle.cc header.i=@walle.cc header.b="meQsPxlb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728939AbgKHSve (ORCPT ); Sun, 8 Nov 2020 13:51:34 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:54145 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728904AbgKHSvc (ORCPT ); Sun, 8 Nov 2020 13:51:32 -0500 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 22C7C23E63; Sun, 8 Nov 2020 19:51:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1604861489; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JH5gvZvLtD+T6J5gJa7u72Ihh3TsKWgIHzRE/YcUp4c=; b=meQsPxlbtXajdgdWxX06jAMgrkn06oDTGxMF5rh19gKHlrAlSlqSWQxIb9KY9RyBMdkS01 m41g+wFvildS8iADOqXtkiyAXkCMKaktUlBael4xagTXeHfVIKrIvrL2dr1c5k+oaew006 I1uupI6t7kGO60VbX5nkSWbjvP9OBtU= From: Michael Walle To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Li Yang , "Y . b . Lu" , Xiaowei Bao , Ashish Kumar , Vladimir Oltean , Michael Walle Subject: [RFC PATCH v3 9/9] arm64: dts: lx2160a: fix FlexSPI clock Date: Sun, 8 Nov 2020 19:51:13 +0100 Message-Id: <20201108185113.31377-10-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201108185113.31377-1-michael@walle.cc> References: <20201108185113.31377-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now that we have a proper driver for the FlexSPI interface use it. This will fix SCK frequency switching on Layerscape SoCs. Signed-off-by: Michael Walle --- Thanks to Vladimir Oltean, this was partially tested on a LX2160A RDB. But this patch is marked as RFC nonetheless, because there is too much difference in the clock tree between LS1028A and LX2160A. It would be nice if someone could test it and add a Tested-by. Changes since v2: - none Changes since v1: - none arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 0a54a54ec770..130de5f7ff5e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -661,9 +661,20 @@ }; dcfg: syscon@1e00000 { - compatible = "fsl,lx2160a-dcfg", "syscon"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,lx2160a-dcfg", "syscon", "simple-mfd"; reg = <0x0 0x1e00000 0x0 0x10000>; + ranges = <0x0 0x0 0x1e00000 0x10000>; little-endian; + + fspi_clk: clock-controller@900 { + compatible = "fsl,lx2160a-flexspi-clk"; + reg = <0x900 0x4>; + #clock-cells = <0>; + clocks = <&clockgen 4 0>; + clock-output-names = "fspi_clk"; + }; }; tmu: tmu@1f80000 { @@ -778,7 +789,7 @@ <0x0 0x20000000 0x0 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; interrupts = ; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen 4 3>, <&fspi_clk>; clock-names = "fspi_en", "fspi"; status = "disabled"; };