From patchwork Mon Nov 9 17:04:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320934 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp1896434ilc; Mon, 9 Nov 2020 09:04:27 -0800 (PST) X-Google-Smtp-Source: ABdhPJxEc6SbxtJKeKaxPg0TJPNihwFNny3UIBv3iwpEM7lkgbE9nnDMnJ09p6eNS3vZHJ/YAvuR X-Received: by 2002:aa7:de01:: with SMTP id h1mr16293042edv.269.1604941467293; Mon, 09 Nov 2020 09:04:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604941467; cv=none; d=google.com; s=arc-20160816; b=KnvnQe7eI3A61ABf15ay2kAFbWca7jBJJCEqetgLkNBMTFlVKpgMfPWsKO3vOtxA1c qsBYm+6r+twEqfQ94vjFzwHEaaWM0TEUVBOIhV4pVqwyTRKyQpgTsmpywfAJ8wdlCUcs Z8vuFSoUWfsTR2mA2Wb+F3bqAT8vg3B6Nz6ZHtxqXakNWnTPKFQSnpXYaLxFnbNWP+IK F4yKqPFoTHLXywi62HHOb7b6VvHa6KP+VC3envILIHD+dK6BUNbrgerBJCMXXDJVeF2h jkyf9IBUjx1js7qebkUvRVmoJkYESN0ZSNFLevXzo9+tcYiIJBQ5G2Wy1M9N6aHg9Ix+ V27A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=rez2nNITrchwUV9a5zJYzK2/jqQ1anb/jEJKp6emraU=; b=jlN6d4tGxAK4hw6RNbUoOjapOCNTJviwB9dtBVtyi1bHhJFx3z/zxDJMe0kY9OgE3N XgsFGUV/YvYbUo5XYyUlaEv8q61jBc/ODMS3GiN8yQUySVzYL1XwRVHv4Sq4Kc9OgtIt TrZNzelTEiJexkBe+9l7Y282Jl4Yfa29hf6FwFtPCVypGnXqbJ97cmQpREDgwY5UeZ2R +/2TOEpt7uw0L5W1qyn9pcMcBW21G2qQa31Y/3plwHxaJ9hEtYgku3Flfv63eJWAOawC mL0Ie5p9UjkfoK+TsBl1rqcr9MBhaFeRVfYRjqOsHdWmwyiWKbT+Rv0vpQY+96DDqz6R JguQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wAvAQE03; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id pg11si7258347ejb.92.2020.11.09.09.04.27; Mon, 09 Nov 2020 09:04:27 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wAvAQE03; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730914AbgKIREZ (ORCPT + 6 others); Mon, 9 Nov 2020 12:04:25 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:45148 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726410AbgKIREY (ORCPT ); Mon, 9 Nov 2020 12:04:24 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A9H4JB4001539; Mon, 9 Nov 2020 11:04:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604941459; bh=rez2nNITrchwUV9a5zJYzK2/jqQ1anb/jEJKp6emraU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wAvAQE03fagBZdOGkqc3piNGnac0dMPgukPrSG7LG6ifYns6SuhgrXy6WbXVzGBJH b4W0NPesHDeCAQNy+Th+XZNf2KRzJV768XDn/AnbLPx28mG2vktl5p2zBLfwCiSM90 wJO/mYdWPHP6xYe4ayFWoUbOyoAssQPjtV4Wz7BM= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A9H4J5f096259 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Nov 2020 11:04:19 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 9 Nov 2020 11:04:18 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 9 Nov 2020 11:04:18 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A9H4AwU036684; Mon, 9 Nov 2020 11:04:15 -0600 From: Kishon Vijay Abraham I To: Tero Kristo , Nishanth Menon , Rob Herring , Roger Quadros , Lee Jones CC: Kishon Vijay Abraham I , , , Bjorn Helgaas , , Subject: [PATCH v2 1/7] dt-bindings: mfd: ti, j721e-system-controller.yaml: Document "syscon" Date: Mon, 9 Nov 2020 22:34:03 +0530 Message-ID: <20201109170409.4498-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201109170409.4498-1-kishon@ti.com> References: <20201109170409.4498-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding documentation for "syscon" which should be a subnode of the system controller (scm-conf). Signed-off-by: Kishon Vijay Abraham I --- .../mfd/ti,j721e-system-controller.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml index 19fcf59fd2fe..0b115b707ab2 100644 --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml @@ -50,6 +50,38 @@ patternProperties: specified in Documentation/devicetree/bindings/mux/reg-mux.txt + "^syscon@[0-9a-f]+$": + type: object + description: | + This is the system controller configuration required to configure PCIe + mode, lane width and speed. + + properties: + compatible: + items: + - enum: + - ti,j721e-system-controller + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + required: - compatible - reg @@ -72,5 +104,13 @@ examples: compatible = "mmio-mux"; reg = <0x00004080 0x50>; }; + + pcie1_ctrl: syscon@4074 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004074 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4074 0x4074 0x4>; + }; }; ... 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Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../bindings/pci/ti,j721e-pci-host.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index ee7a8eade3f6..ecec36c02883 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -15,8 +15,14 @@ allOf: properties: compatible: - enum: - - ti,j721e-pcie-host + oneOf: + - description: PCIe controller in J7200 + items: + - const: ti,j7200-pcie-host + - const: ti,j721e-pcie-host + - description: PCIe controller in J721E + items: + - const: ti,j721e-pcie-host reg: maxItems: 4 @@ -48,7 +54,11 @@ properties: const: 0x104c device-id: - const: 0xb00d + oneOf: + - items: + - const: 0xb00d + - items: + - const: 0xb00f msi-map: true From patchwork Mon Nov 9 17:04:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320936 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp1896621ilc; Mon, 9 Nov 2020 09:04:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJyjBNnUA7tIV+WSgoOz+QYKY8TwutgRTpM2/JzMfP+Jzem7i3vP4P4ptiN45o3OSZa4dVmX X-Received: by 2002:a17:906:5a97:: with SMTP id l23mr15616937ejq.232.1604941479896; Mon, 09 Nov 2020 09:04:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604941479; cv=none; d=google.com; s=arc-20160816; b=SGpElKuy8u1F1ap10t1BqcSmPJUYL0uSFsqmhXs4uq8A1mDOiA872b63asZyKRThb1 vGPn/s2+or3qPrkavEkWM9xtkwzLEGdI6NkPbKC/5JIFz+CzBwg1lkr7qOjfQIu762i6 GTFqaYq4L1tahRtKxdsqa59TFMndXZXBllif/wNFXxrYftRpWetkDZq7EG7igJNTkkDP F1HSTrdpNVxkeANWZhP66jDRz2oCDhM3iBQW+V9COsJ3USFYk5Hq23zT/SrgpoXdcW4b AKhKxNMrSs7A0TflqXZ8yixR8VsjbJxz7QQVkHjXCGdOg/IvIjQdr45c+g2DgaPY0AWd prGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=FZ6tzg3tQDmmfBsqprfpFisT1FjAStoGzjl9svcH6R4=; b=yAxTTfPQ8LTBoSR86qE/Xucryztbz5jbUsgNIjYKKrzvnEUICdKbNl772t+Tb9GIR7 g8nJhCtIyQEMCN9rARN61GFnFiZdeOqDLzKynyv+qwbYFEFUG8lvARboHTHG2+TQ05FY BtK2GG3h9dm15JiwnWdMjM+0Ygmc7wldSPICC3TH11YPJBTLueOicTixLyzO9G4CzMzg VcHqFxz+LjZqB3q2Ez5ui0A8RQcubKm83EfH6J5LJBq3vchZcLBHygp8OOGdZXC+pBGt PTq4QItxBUwBNXE454V7h0FojEKQUOeZ5WSesbXGY7QjKICsv4zI9bFLQzAilXh62Hoa cmeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VZQ972EY; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 3ae3e1a2d4b0..da8c5b892104 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -15,8 +15,14 @@ allOf: properties: compatible: - enum: - - ti,j721e-pcie-ep + oneOf: + - description: PCIe EP controller in J7200 + items: + - const: ti,j7200-pcie-ep + - const: ti,j721e-pcie-ep + - description: PCIe EP controller in J721E + items: + - const: ti,j721e-pcie-ep reg: maxItems: 4 From patchwork Mon Nov 9 17:04:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320937 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp1896683ilc; Mon, 9 Nov 2020 09:04:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJxEMFLiUevB/wkUZho92D9YmjOgEGSv4n85h/cRxwUAtevL3h7wXgV93DtVCfvapQszHSnv X-Received: by 2002:a17:906:2e08:: with SMTP id n8mr16596050eji.440.1604941484812; Mon, 09 Nov 2020 09:04:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604941484; cv=none; d=google.com; s=arc-20160816; b=kEgEl5rIh8il5rZBuj/1MiqiDj0WvYHLJb2RrwswVlHy7gGtuOLxdpBlIzlJPs6S+w lCr7j7OmCmMIPSrQ8eg0q+w9fk0QosPpk3zRVpPuIUprU6+hZG5b3ZfUj+GIeGYbu/Wv D619odY0hQGp4B6WYeWdnUyOWZb8U0IGx49WSsS2Ir5+zvBpodMKNgDatXrpCwnVVwBP rh3pfpbIoo4VC7w4mXx4eZr7NJ2cX/UtmWR+hejkZRWOsX9i1DYG+iIrg2wGjtJaTwQM BH4vvf1WaPblUwCpagLn5li9sISBXd8WiixLaX06bfF9EM7Y5WZNNMaOynmQLug2/caL NciQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=yXkEa7Q+nG4lbV+xXUuIkCvfRCO63DcaQ86Sm5PsyrY=; b=C2kY+EYpTVZvGFMzr0H9RevC/ncpIFGQVF7DlU/1CJkJg8D6v8aA+lK4Jk6gNhfoUF nam/fVexS0BST0umCrCO3CuJb5v3ulWpozom2YZDACTpXuOKGmr1pnowYPrmTe0fhySB +jaTIiUxqyEOI93sckfuRU4oeOY5FFtxZyTB3G1S+FWzX3tlmSeg1ITqqiEtBC63MxPz bRhyLv2PPSLFe0Rry1xnjSAm0LTSYuNa8VfrGvw8008AngVlX6Ij2yA2zXpTTP512Eev BvAQLMjg/Tiuh87gMgXBsQ20VZPMQHl0I4dyUBozDgFGL4GG43B4vvDqTe1JVO89is/e Jdlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hsz9qO3W; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 61 +++++++++++++++++++++++ 1 file changed, 61 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 72d6496e88dd..7668404c178b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -417,6 +417,67 @@ dma-coherent; }; + serdes_refclk: serdes_refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + serdes_wiz0: wiz@5060000 { + compatible = "ti,j721e-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks = <&k3_clks 292 85>; + assigned-clock-parents = <&k3_clks 292 89>; + + wiz0_pll0_refclk: pll0-refclk { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_pll0_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll0_refclk>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_pll1_refclk: pll1-refclk { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_pll1_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_refclk_dig: refclk-dig { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_refclk_dig"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { + clocks = <&wiz0_refclk_dig>; + #clock-cells = <0>; + }; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&wiz0_pll0_refclk>; + clock-names = "refclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; From patchwork Mon Nov 9 17:04:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320938 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp1896832ilc; Mon, 9 Nov 2020 09:04:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJyhnX07rBCzWSlvb38n6TTzrcGONELLcXBUL88zPoRFXw0b2dqCws761bf6yvf67qn9V5vx X-Received: by 2002:a05:6402:1206:: with SMTP id c6mr15999049edw.2.1604941494637; Mon, 09 Nov 2020 09:04:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604941494; cv=none; d=google.com; s=arc-20160816; b=kANFejQ5vaN/Jx3fxutFFwoG01EctZhx1LwYb/sJkcirgxFLxzQsZJplEgu5DpBRV+ E+zSDEASasxuKS6PoN4zQXA+vp3mrieH2V7pxT4PAjXH4fjKsvb266uPuLeWMNT2kx7y KoKPREmQ3k5oeM9pTBYIO2C9m17+ua9RRCKbIr5hro7/+M24nbv2p4wEBOPsPUhw6Crm Shhba64AYE4KI4elvNjLkU5mg42QXJoH6uOvI7ir0juEDx1OEyMHE3Lpv/aB9yhhlfUi lXVHQnTssiz32XoWSgSdbP2TQIwLhYaQ8jvNqiri7N5nU+JA2YzIrSxAxsep1/xz5uA/ nsag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=skXucqkVEo4ozqaLzJQ4k3uek1jMkHvx/RLeYB5uGzg=; b=jxQQtN0ztowK33j43J0/wj8uzKrRgCkp2/z+9nzoqKSbFQGKNHyfTP5ygtsiw6uXdH KKa50IiqQVRT/ORCxp7byfIa8kqodtUW1EOeS2tEpSlwq/rvAWMdejUuwTX6T5+yYM2l u8ODgfN/zHRwqC7g0I3bcVbbOPGwLp2iaMPhvCXBY7MMDc5l+igmqBpXgnFTa0Zz4HV2 8wgbqAOQbejZnbjikx6cBr67ufk4iZL+J15ROFW8mNEMfByTETir9k5fMGHLROYHZLMA QHV4UJclb46LXzlcY/1F1d+2ANvvrJ6EXv/aGQPbBtiGsGfq7yHbP37c0z+CzqR76pUF Prng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DUhtlkVa; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 57 +++++++++++++++++++++++ 1 file changed, 57 insertions(+) -- 2.17.1 Reviewed-by: Vignesh Raghavendra diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 7668404c178b..38dff212615d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -25,6 +25,14 @@ #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + pcie1_ctrl: syscon@4074 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004074 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4074 0x4074 0x4>; + }; + serdes_ln_ctrl: serdes-ln-ctrl@4080 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -478,6 +486,55 @@ }; }; + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + cdns,no-bar-match-nbits = <64>; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00f>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + cdns,max-outbound-regions = <32>; + max-functions = /bits/ 8 <6>; + dma-coherent; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; From patchwork Mon Nov 9 17:04:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320939 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp1896883ilc; Mon, 9 Nov 2020 09:04:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJzILRdBB4tjrn8DyYAeRJOUTb9D9PVOx2YdWUG0bXqGDoyUkK4sHgsZje8Mreuzu8tTfmBZ X-Received: by 2002:a5d:474f:: with SMTP id o15mr18478568wrs.377.1604941498003; Mon, 09 Nov 2020 09:04:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604941497; cv=none; d=google.com; s=arc-20160816; b=rMSvTAf/c3y0u2dKSc59UNffEVwanBsmcEHv1mCtWpTvxtOCdgZtiYsN7O7m26Xz7l ZgjlP4UH7lB3ZrBj/N82uWWOxt+nA+WEcOwCxXXiDrzQUofS3Rl6IeYFSLT+04LTGrJ0 yweO30qofV/JVRCzHOc5CnJZkNQG7uXGIgOTw4/k/fPxYumMgrPjJO39+G0W1FJFS1up 2tt389GEevXoDp/fAjh0JYCtH1EWzd4EClurKW9Yf4AuGETYObAeW3jupk1XXf6McNiv eHU3qUZRAR+DZM+5AJCWfdpLB1jCn9PeT19+6ar8kYdnoKHjc5ThYuFg6ScLfTYhrCmJ 727g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=GYtAOEut/0FFiR6xZ9eTzNKBNpdk6Wpn5qkaz83y1S8=; b=ezlKcGRcImxVg5HtrbfT4vbTM9O6z/jv1PTu1sUpg0kNd31BI0zXEgcSxvhfNGBOCs bY2rqP9d38PYUM+36lfyd2Jz4WGggNz1VCLNrH2DyaLdBP76gSksgzxNpzgQr2MGW/vx CQ7stbIQjKgYuqTBirmHJgbGkPe8hz22LJ7PERoSIEybeVqHm85Zsp1Eh5Ff3/b35XKS l2MMKAPdWpYSh6kp+vEH0fMDclqI/5ki18LpLJHG6ULFr8VOdiPhTuCj4/ta4A2+D3DF /NeRw/HmBwIrTTXq8F98QSB6QT8QGdIg1ivzXsCKLHxQcwjfW3xBEwz7CCFxX4VQ+Fx3 53Rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="TonV/vJK"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j7200-common-proc-board.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index ef03e7636b66..65a2e5aeb050 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -8,6 +8,7 @@ #include "k3-j7200-som-p0.dtsi" #include #include +#include / { chosen { @@ -213,3 +214,25 @@ dr_mode = "otg"; maximum-speed = "high-speed"; }; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_qsgmii_link: phy@1 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 3>; + }; +}; From patchwork Mon Nov 9 17:04:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320940 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp1896985ilc; Mon, 9 Nov 2020 09:05:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJzbJkFEubIOSmCMxP6PNnwn5yO8Q3E17d23MHG4P//r9if1PCQ3lP7FLJU0mbRfi2wcrqjK X-Received: by 2002:a05:6402:1813:: with SMTP id g19mr16606203edy.105.1604941503562; Mon, 09 Nov 2020 09:05:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604941503; cv=none; d=google.com; s=arc-20160816; b=BH8Idp2QzI5gzEX8A1tWyIGoIy66LQ01xM0YXKtneeB0iQF60qYxW51NiTuWl/C/VR B5ehSIFUJL/9U9ONL2nVP8Q93hRG2FgZ69o8TObNySpuYez0RkuV5k+T7F2gh10fb69S fle9Cpz4HOtGMlnGCcaE0ICfYj9TcDZSBJ55r7DG9Lz3u1Byrn2N+IJR/Xfdy+tqPATv cPDxPQbeLaD2+bNtO4f8HnTV6J+JcEbf5svE4RcRQKW+43gWYmcCBYph7f5i6tJCv8np yx8eHFxykEYLUK7bbYsQOAPOQ46ydiMlds0nHzl/5Al0LwdqO/GYXaWDD6oIJFXd1fjx mXUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=IpwM0VYjFst7O7GZPtDw/QKWR6xLDCT8pa2h5EbOyBs=; b=rzdewOjed/efAhWR3iX+Apxg52Yv8MxmEnN0qZ/2Oxjwt4CbrPssF8nLyRhhf5xmW4 T/BP1QilaQ8+3C/AquZDSl4Cd7oB7DVh9W0kr3ZJA+YXdV8iWgZyR7yjlzzG1K4uzchz KwIr42AOS6mMF9uekR+idxE84BRXiUHd9gtDYh1azfxwQYGuUX3PsYP8fqqDX9WDRT1P xsTqZHtWkYeJAzV7sXtixRyuvo0ieL+Ym7EfI+su0yM2mKRMJ+6aEAnkLq7U5ygG2v6t MkLvISRaDdGGjOfWL+vLfmXWpfwfg3sktGhERDVCzOwpIPbAekjaHlcXOjHgqINOKj79 5hbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tfqw9T8T; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Add PCIe DT node in common processor board to reflect the same. Signed-off-by: Kishon Vijay Abraham I --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.17.1 Reviewed-by: Vignesh Raghavendra diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 65a2e5aeb050..174a55a18522 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include #include #include #include @@ -236,3 +237,17 @@ resets = <&serdes_wiz0 3>; }; }; + +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie1_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +};