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[61.216.91.114]) by smtp.gmail.com with ESMTPSA id k80sm14337459pfh.30.2018.01.05.08.16.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 05 Jan 2018 08:17:00 -0800 (PST) From: Jun Nie To: jagannadh.teki@gmail.com, wens@csie.org, maxime.ripard@free-electrons.com, hdegoede@redhat.com Date: Sat, 6 Jan 2018 00:15:58 +0800 Message-Id: <1515168960-18960-7-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1515168960-18960-1-git-send-email-jun.nie@linaro.org> References: <1515168960-18960-1-git-send-email-jun.nie@linaro.org> Cc: u-boot@lists.denx.de Subject: [U-Boot] [[PATCH v2] 6/8] sunxi: usb_phy: Clear PHYCTL register before writing X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" PHYCTL register offset at 0x10 need to be cleared before it's written. Ported from below Linux patch. d699c1d phy: sun4i-usb: change PHYCTL register clearing code Signed-off-by: Jun Nie --- arch/arm/mach-sunxi/usb_phy.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 2f1cad1..bcf5f15 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -156,9 +156,15 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) { #if defined CONFIG_MACH_SUNXI_H3_H5 - if (phy->id == 0) + if (phy->id == 0) { +#ifdef CONFIG_USB_MUSB_GADGET + setbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); + writel(0, SUNXI_USB0_BASE + SUNXI_USB_CSR); +#else clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); #endif + } +#endif clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); } #elif defined CONFIG_MACH_SUN8I_A83T