From patchwork Wed Nov 4 23:43:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BCB3C4741F for ; Wed, 4 Nov 2020 23:50:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 13DBC20825 for ; Wed, 4 Nov 2020 23:50:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lVcUqzf4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387509AbgKDXuq (ORCPT ); Wed, 4 Nov 2020 18:50:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732671AbgKDXpA (ORCPT ); Wed, 4 Nov 2020 18:45:00 -0500 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E64CCC0613CF; Wed, 4 Nov 2020 15:44:58 -0800 (PST) Received: by mail-lj1-x241.google.com with SMTP id v19so310919lji.5; Wed, 04 Nov 2020 15:44:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YM5IiBSxM0x10e+Au9qpNGPC4fBnjpf0BFdkUuSd19o=; b=lVcUqzf4bACnjosNBHshwKvloxF1mXmh47Jx+tv5SOw3pbcF5MewYXF2PB/avaGI70 vQJq32tRmP2XPmPN+x69w89RTcvLM305K0t5/8gnq90BjT7LO494irREBwHTquD1oSOp MR5CN4fovrz4pzkyzp0PaspM5y8oMZxNFeB8gslG+P+IZgNjFaL4yf1zeIhqoK+5owom LKXVk/rIA3l92z9ZoOn/8SQ+nc3Up9VpkX9oU+cQ2Ho8ccmdajqKcqIPL9LaPxQguChN UxuOOhhmNyTW8RnPu0w3dFY1qJ71LnPOFHgjMdZmODW6bZUq1ow8R47S8wm2f/wv7rkQ 4nSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YM5IiBSxM0x10e+Au9qpNGPC4fBnjpf0BFdkUuSd19o=; b=d9G7uCb1QAShnsO0T+9wTGvMMRgv+VAgVh7bL8lz2WQ5nvxGJkoTTwMs+mnjVbj6P6 cW2zyvLJ0d+oixksh+nNh/06AwVPKI1BkthZRmIF79pSO2ITPKzNzcW/liTDAN7o/KRe i/29MVFR8ZEpa+h5GbV75lUSUH35dSIMN0EV/inCI6sWmP/8ifM2KXP43k2KgJZsv17Y FMSHPEEfR59ckD68op/7sBD8Iyjn5QDHovRv01kdWAgzT6xz8DZe5u079/QeoubjEKWN FT8O+Ya7qy2lcQh3mdaqQ4Un5j8ULBHKHdNaY14bDAaH9m6nEoZ3mMAumduGmZKO5ZOQ SbXw== X-Gm-Message-State: AOAM531ddC49S8SYFTdhv656Z7XmFsH0TPpdaU9icUyncjl7gUlqzyGO Tdj1ffxEUu6jA9N/Hs8D0a8= X-Google-Smtp-Source: ABdhPJwmfo2F3w3VqauMbdw79G3wwAW+IEPO2zeUaLvIq9m5Iy9Czxc99+HDdNQyXZjk5AradNM/vg== X-Received: by 2002:a2e:9a98:: with SMTP id p24mr132196lji.418.1604533497375; Wed, 04 Nov 2020 15:44:57 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.44.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:44:56 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 01/30] dt-bindings: host1x: Document OPP and voltage regulator properties Date: Thu, 5 Nov 2020 02:43:58 +0300 Message-Id: <20201104234427.26477-2-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Document new DVFS OPP table and voltage regulator properties of the Host1x bus and devices sitting on the bus. Signed-off-by: Dmitry Osipenko --- .../display/tegra/nvidia,tegra20-host1x.txt | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 34d993338453..0593c8df70bb 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,18 @@ Required properties: - reset-names: Must include the following entries: - host1x +Optional properties: +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- core-supply: Phandle of voltage regulator of the SoC "core" power domain. + +For each opp entry in 'operating-points-v2' table of host1x and its modules: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled. + Each host1x client module having to perform DMA through the Memory Controller should have the interconnect endpoints set to the Memory Client and External Memory respectively. @@ -45,6 +57,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. + - operating-points-v2: See ../bindings/opp/opp.txt for details. - vi: video input @@ -128,6 +142,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. - epp: encoder pre-processor @@ -147,6 +163,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. - isp: image signal processor @@ -166,6 +184,7 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. - gr2d: 2D graphics engine @@ -185,6 +204,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. - gr3d: 3D graphics engine @@ -209,6 +230,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. - dc: display controller @@ -241,6 +264,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. - hdmi: High Definition Multimedia Interface @@ -267,6 +292,8 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. - tvo: TV encoder output @@ -277,6 +304,10 @@ of the following host1x client modules: - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. + Optional properties: + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. + - dsi: display serial interface Required properties: @@ -305,6 +336,8 @@ of the following host1x client modules: - nvidia,panel: phandle of a display panel - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang up with in order to support up to 8 data lanes + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. - sor: serial output resource @@ -394,6 +427,7 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. Example: @@ -408,6 +442,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_HOST1X>; resets = <&tegra_car 28>; reset-names = "host1x"; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; #address-cells = <1>; #size-cells = <1>; @@ -421,6 +457,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; }; vi@54080000 { @@ -429,6 +467,8 @@ Example: interrupts = ; assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; clocks = <&tegra_car TEGRA210_CLK_VI>; power-domains = <&pd_venc>; @@ -510,6 +550,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; }; isp { @@ -528,6 +570,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; }; gr3d { @@ -536,6 +580,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; }; dc@54200000 { @@ -547,6 +593,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, <&mc TEGRA20_MC_DISPLAY0B &emc>, @@ -571,6 +619,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, <&mc TEGRA20_MC_DISPLAY0BB &emc>, @@ -596,6 +646,8 @@ Example: resets = <&tegra_car 51>; reset-names = "hdmi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; }; tvo { @@ -604,6 +656,8 @@ Example: interrupts = <0 76 0x04>; clocks = <&tegra_car TEGRA20_CLK_TVO>; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; }; dsi { @@ -615,6 +669,8 @@ Example: resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; }; }; From patchwork Wed Nov 4 23:43:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6820AC2D0A3 for ; Wed, 4 Nov 2020 23:50:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0F04220825 for ; Wed, 4 Nov 2020 23:50:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="njurvPV7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387783AbgKDXtx (ORCPT ); Wed, 4 Nov 2020 18:49:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733030AbgKDXpA (ORCPT ); Wed, 4 Nov 2020 18:45:00 -0500 Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E114C0613CF; Wed, 4 Nov 2020 15:45:00 -0800 (PST) Received: by mail-lj1-x244.google.com with SMTP id 23so300100ljv.7; Wed, 04 Nov 2020 15:45:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xyl6mwFdE15+t57cfnIytHG3Se38ipqIkKmYax6Z3Mg=; b=njurvPV7mYqVLXzLgzJMnQSBEnKE98oQKN4wK2dwEEIUDD7c6TRaSrw/9vciyz9XTc r0YOhwlcgm49SWqw8X9FydGAuWL+Unq90UFrxUtioI7SBGMjW3CXqGJug3RcWkA/s5yn XXyOv3T/tJxeU3RYP1xk3msgeJ/bxdzuK7URw+UQfBWoEZNEc1GTjxs+RSNpBzQz9Vvx T+BIa1HbzcDoiEXmaykCEP46kmiCL7189E89By+ope+D0L/TnKptWT+CPx5PYg+3BvjO jCwwYbCrTJce2YM5Px34gOTd06YKcy1A+u5agSc+RfC46gLInyC/nzLICGe4dtLWb3l0 byVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xyl6mwFdE15+t57cfnIytHG3Se38ipqIkKmYax6Z3Mg=; b=RzysN0s9ME/zA6hTQla/4rO8FwCMzOhza2uSoSA9LdnIUtIwP7iN85mCHDOOX/pnt0 4h9I92IuTSsX1xjtjVvDd4Yuc6TJJ0tWyN7x0XVpBLVU9YUfw0uuCd/BMbgTVlMW3LaM Bjogw4MHZevLIgNiuhv+MfWaAF+14VU8QPGHRrPx662TiUXdc27fiYsszhNrN35o1HGA dDgsDNW7BW8+DycpyPKgOU2iKTnJWFrP8aVB47Pe4fcd8UZs+PCribOl5lxL1QVd3Rmc bp94irvAhosD5Pbcg+cwnk+Jv5/SLw1eOnTA2cUMiQnNpodiK0oyEd5W9qn9JjxHUwAk lCKg== X-Gm-Message-State: AOAM532Uqfavlo+SX4sl6S5flL4bNM/WRzYOLpNntABJFoVvKR6Z90Vm qrOibD3NKaLvEACyB7tqjus= X-Google-Smtp-Source: ABdhPJxyfUR5ytzjzRHO8KNVIYAL6OAR8JGEl8Y8hPTg36jXTHsV0rP3oD6HDz+Wf6BvR5Q/lM5EBw== X-Received: by 2002:a2e:9909:: with SMTP id v9mr136172lji.429.1604533498850; Wed, 04 Nov 2020 15:44:58 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.44.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:44:58 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 02/30] dt-bindings: mmc: tegra: Document OPP and voltage regulator properties Date: Thu, 5 Nov 2020 02:43:59 +0300 Message-Id: <20201104234427.26477-3-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Document new DVFS OPP table and voltage regulator properties of the SDHCI controller. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring --- .../devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index 96c0b1440c9c..1beb0416ae5f 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -31,6 +31,16 @@ Required properties: Optional properties: - power-gpios : Specify GPIOs for power control +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- core-supply: Phandle of voltage regulator of the SoC "core" power domain. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled. Example: @@ -45,6 +55,8 @@ sdhci@c8000200 { wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ bus-width = <8>; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; }; Optional properties for Tegra210, Tegra186 and Tegra194: From patchwork Wed Nov 4 23:44:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 137B0C388F7 for ; Wed, 4 Nov 2020 23:49:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A816D20825 for ; Wed, 4 Nov 2020 23:49:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nqm2X6ZZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387804AbgKDXt4 (ORCPT ); Wed, 4 Nov 2020 18:49:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733037AbgKDXpF (ORCPT ); Wed, 4 Nov 2020 18:45:05 -0500 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F61AC0613CF; Wed, 4 Nov 2020 15:45:04 -0800 (PST) Received: by mail-lj1-x241.google.com with SMTP id v19so311101lji.5; Wed, 04 Nov 2020 15:45:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A6xeyw6ZqKT/K4JMygz/BmuhCT9ICHlbp1KBA4DEr4A=; b=nqm2X6ZZJuj9sZgSTybdOUi83IBwYn9f7Zvfx06NhWRHbQaEo61dn0AWICDKuDsAzX WcnvRncZgz7BZ9/CebWWEjbmvtTisywn31eZ4pmGs2UNS0RRtZfCOBhiTwow/n6mPe9r 7agAHRD0R2EELNcElIqennHlgH8OGOPHoFL2PRl+Ja/SdoRvkx4BsTmnP2gpWNQvarxG SjryQPM6YqWLBzOv3L/jKhwY2mKEYxloqIA7EIeYrN+YlKNWbDi4sdhMPjwR1DWYKbqi vxBJYm1aGkZ0x3sS+0lBKRX7ZCwqw3mmTLFKmuBg1cW60xhkD71EveU4NYFDyWJAnfX8 8m1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A6xeyw6ZqKT/K4JMygz/BmuhCT9ICHlbp1KBA4DEr4A=; b=Y4b+7OImCnBVlJ+Z663vsf/jYtMe9v/tOiwVp/RD907m/yEFEWjdwzcBvHOkKU6qUr Qot8d90Bbt2sOH5rwtQLsqT49Hnlxj91zjWMKcLoraAzq/B4zDYInGcVO6qXbzDeY9ts 6UnmHpBAMcjF58JUg8II3ztnwhBAi5kXTgtXpwnDcb4YfiwvoZ1c9uy+CSDWZObRivQb 64P+S62TUDlYsaEw54JuCT6Aa8B+MEod5JzoSzhKFzCPwdjxB/lW10IxDniLYC4MMkTW ads0Luv84kxEsVdb2cPOyokOsJbbGzRCZKyoYyCdHU4QPn/XDPB2TAehaSYr85M+HH62 etnA== X-Gm-Message-State: AOAM533/xtgzEhIAy07fa3Ds9wgK+ykUHzPZ1a28X44zvkliEo2QOMxP aoflnOj8SFUyMJKjQ2rlh/A= X-Google-Smtp-Source: ABdhPJzDTd1dZ6QvpxBBESnqfpznl55p7ubyewQPaYA9itl922HIytqPgmIH/zsQSw8jZFmiQ9g1kA== X-Received: by 2002:a2e:b619:: with SMTP id r25mr134978ljn.465.1604533503104; Wed, 04 Nov 2020 15:45:03 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:02 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 05/30] dt-binding: usb: ci-hdrc-usb2: Document OPP and voltage regulator properties Date: Thu, 5 Nov 2020 02:44:02 +0300 Message-Id: <20201104234427.26477-6-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Document new OPP table and NVIDIA Tegra-specific voltage regulator properties. Signed-off-by: Dmitry Osipenko --- Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index a5c5db6a0b2d..f02a98201062 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -90,6 +90,7 @@ Optional properties: case, the "idle" state needs to pull down the data and strobe pin and the "active" state needs to pull up the strobe pin. - pinctrl-n: alternate pin modes +- operating-points-v2: See ../bindings/opp/opp.txt for details. i.mx specific properties - fsl,usbmisc: phandler of non-core register device, with one @@ -110,6 +111,9 @@ i.mx specific properties The range is from 0x0 to 0xf, the default value is 0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1. +Tegra specific properties +- core-supply: phandle of voltage regulator of the SoC "core" power domain + Example: usb@f7ed0000 { From patchwork Wed Nov 4 23:44:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 282DDC388F7 for ; Wed, 4 Nov 2020 23:50:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C35F420825 for ; Wed, 4 Nov 2020 23:50:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ERKSO83J" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732814AbgKDXt5 (ORCPT ); Wed, 4 Nov 2020 18:49:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733075AbgKDXpG (ORCPT ); Wed, 4 Nov 2020 18:45:06 -0500 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFAB2C0613CF; Wed, 4 Nov 2020 15:45:05 -0800 (PST) Received: by mail-lj1-x241.google.com with SMTP id m16so307120ljo.6; Wed, 04 Nov 2020 15:45:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yQimpkIRWNQnMpbdhCpUPNBZvo/GpufqvOqt4z0qAwA=; b=ERKSO83J6tv0QUdt8vnWSOE1GpIwg7mIR1JUrs4PyfgPVzV1mH7mEpyAJOsSR12xY3 rsldAI/5QE2rxBoNdwYh3hxk/wzRAkSsKIoHuD22P4lN8jkkBxNCFgbBpKfwYVwMtiZk hY1Z1gChPo7sDA1p9MxN+Mx1EdAo2nz8TwGsz+e38nVaIbWMWUcpVKqUAWxqflyFUc2z zmVkx897k9/dL5uXgyLRVGwDyjmwfMJMHjINdfH3z7T1O6RmI6/62I+J/f3RaDIG1/F3 b5/NryfWaEyEXi653d2wn4BVQldGJhyt9pi+F4OHBx7bGp4zD1BVXptYQfB0SIoKU8RY hraA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yQimpkIRWNQnMpbdhCpUPNBZvo/GpufqvOqt4z0qAwA=; b=IwgLlblmv4oEz0X8GFhXSi1NawTXzJBOmCqbT24O4Z/uou33FoZn6A2xIc686i6Byy AWVsI2bhBn7Q/PVQNox+kKh0hMina6igFUtwQ5LKa/9OqXHXELDeY96PqtfLJuBrXlfX /uT+cS+5VkPufQ/D/cZGygUyH6brjSCD4tJiXvT8r7hX3jF3bgrVkDKbI9dOvv1FoqO3 44CpLq6KkynYXK2O4VybELiyhEqowTyMvGSQyv4/t4g3e3Hen2E6FWTLO2Ajm6WO+Dko 42DnU+/W4fcUKeHOQNrwSOJbrjd52FAmyRKVHE0StPaOZAb6w+FecGuzjpKU9NrDOnZg p4kg== X-Gm-Message-State: AOAM531/WLVHSJg+Vgvx261wVKzzp4y+FyLZ1ASQl80C8tPaM8o8UP2y 2P0EvjAdgGRCLg5a/hkTs18= X-Google-Smtp-Source: ABdhPJzqZV2lUSiNvg9T7GHr724oG0dGwDbtok/GVt9MVRYZxSxIwkdsf2v5hnfIaDwbq85V2zwywA== X-Received: by 2002:a2e:b169:: with SMTP id a9mr156579ljm.84.1604533504504; Wed, 04 Nov 2020 15:45:04 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:04 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 06/30] dt-bindings: usb: tegra-ehci: Document OPP and voltage regulator properties Date: Thu, 5 Nov 2020 02:44:03 +0300 Message-Id: <20201104234427.26477-7-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Document new DVFS OPP table and voltage regulator properties of the Tegra EHCI controller. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt index f60785f73d3d..e4070ae21fd9 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt @@ -21,3 +21,5 @@ Required properties : Optional properties: - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20 USB ports, which need reset twice due to hardware issues. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. From patchwork Wed Nov 4 23:44:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 243EBC388F7 for ; Wed, 4 Nov 2020 23:49:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C6DAF20825 for ; Wed, 4 Nov 2020 23:49:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qCfnEwxe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387708AbgKDXtQ (ORCPT ); Wed, 4 Nov 2020 18:49:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733094AbgKDXpK (ORCPT ); Wed, 4 Nov 2020 18:45:10 -0500 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D81FC0613CF; Wed, 4 Nov 2020 15:45:10 -0800 (PST) Received: by mail-lf1-x143.google.com with SMTP id e27so160756lfn.7; Wed, 04 Nov 2020 15:45:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XFGG01cA595FrKS40PcuSC81ebTEtiTSpfS/ywMG7UI=; b=qCfnEwxe9a5udeJa2CYrqVZ5I2a9hmgiqZ2QaqEHjaKRgf2VXGvsewyVcIb28yZDc0 NJtW1jYdxYxihEwtJ1JhHLt9GCrLEFLun5Srgpe/bZELevxRnAmujiK304OirJi3UZ0h OezhThzvVvw8gpQg9av4VU+hB8LuL1lQEpkLkPSBAJ44qZcPhCH6IpgDnyi1uDWq2TP8 RYuqmPWz/JIvDnAxVgHW78wUUMZny2+47MlJ+gq2nxNa+CFz2O475KuV1N/UI1JeRY6C ieR4nU66wpG5FBdE1CzoaJ8S3Cn+p4XlpoQHf4l3Z7bAPbdtXXraV7xxJFeb1rAmopbi NZug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XFGG01cA595FrKS40PcuSC81ebTEtiTSpfS/ywMG7UI=; b=bKDygx+mdm4k4btO5Hsi/u/V6m6qm4Fdwh7V9FGyHeOm9WPxEjx1h42s4qhfgfbLCx /33b9LgrpOyv/QMeNyIqGvzpkldfrT4rOscwkP8lpq//ejTbHSCeiuZezRzxITXXWsBK Jsd6kmZ4UH4OTscpYxogiQmuh78FCVDoI/55UimxgOltNZyClQqsEQ++U6gyYKJog/93 onXzsoHI5Or1pzCVuThq2j6Y6S8BUhdINO+O4dmnlWdXwnXSNmdNYigHKte/EjdVIXY+ 5IC4fLETYizg9SVoB0YnEZy5Y2gJDIYaY4aLmyOehZV1/MA/CMWdMTATgkCZazSkbKAP SA+g== X-Gm-Message-State: AOAM530t5lvImsbld2HUQBoXjhloBs5UbhzuEfOTiZZBEJgnyqKrNZk8 yumQJSmyAhUV20Ur9v0jQxM= X-Google-Smtp-Source: ABdhPJxQAtS5/q5gEZTmOVMhIUSEXN1Ufp90D/WwdUezL1q7/08kLqzAjVTVWhHK+ZA/8JqkDwT3GQ== X-Received: by 2002:a19:c55:: with SMTP id 82mr55638lfm.84.1604533508654; Wed, 04 Nov 2020 15:45:08 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:08 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 09/30] soc/tegra: regulators: Fix lockup when voltage-spread is out of range Date: Thu, 5 Nov 2020 02:44:06 +0300 Message-Id: <20201104234427.26477-10-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Fix voltage coupler lockup which happens when voltage-spread is out of range due to a bug in the code. The max-spread requirement shall be accounted when CPU regulator doesn't have consumers. This problem is observed on Tegra30 Ouya game console once system-wide DVFS is enabled in a device-tree. Fixes: 783807436f36 ("soc/tegra: regulators: Add regulators coupler for Tegra30") Cc: stable@vger.kernel.org Tested-by: Peter Geis Reported-by: Peter Geis Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/regulators-tegra30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c index f7a5260edffe..fcf824f73131 100644 --- a/drivers/soc/tegra/regulators-tegra30.c +++ b/drivers/soc/tegra/regulators-tegra30.c @@ -198,7 +198,7 @@ static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, * survive the voltage drop if it's running on a higher frequency. */ if (!cpu_min_uV_consumers) - cpu_min_uV = cpu_uV; + cpu_min_uV = max(cpu_uV, cpu_min_uV); /* * Bootloader shall set up voltages correctly, but if it From patchwork Wed Nov 4 23:44:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDB14C388F7 for ; Wed, 4 Nov 2020 23:49:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 95C6620825 for ; Wed, 4 Nov 2020 23:49:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Q/1ZQqq3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387682AbgKDXtB (ORCPT ); Wed, 4 Nov 2020 18:49:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733102AbgKDXpN (ORCPT ); Wed, 4 Nov 2020 18:45:13 -0500 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7555C0613CF; Wed, 4 Nov 2020 15:45:12 -0800 (PST) Received: by mail-lj1-x242.google.com with SMTP id p15so298005ljj.8; Wed, 04 Nov 2020 15:45:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wBjgIW7F68X1tjrcRLYGZvVGEJ77+b3TQ2Y5Po7YsD8=; b=Q/1ZQqq3UoVYq2tNoAZWz35b4cHyQDxKVAsJPzTE66rN/1B9Yl7BGayadd4BCoYYME YWNWFOJRFNL5GYtjYJRhqjzWExwSk4SqqPcY+yWq+tz23T/eRedD9g4gnFSa5M49tsOu 0kZi9xyv/VllERNv3M0/B4Dnw7FsfRh81ZVcQnSfVrsxs4KIBXOq8WSvFIH3K1v07Xcp jYxgPjWeFytLCm9V8/8dxHrvpfcuqKra/CR2t8lYLpHSH9FI1iyUBE/cj/ZznRO7+bBh jBtD8rXOVqTZt+Q6T9meCd47iiSOSbySoeaVGuIJ8KomJYGa0xCqGpfNMhS6xqEDw60x +R1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wBjgIW7F68X1tjrcRLYGZvVGEJ77+b3TQ2Y5Po7YsD8=; b=iTVzyDu3gxPGXBrhnal5V2PtqVimVwiS5evfxhKvBJJLcW3va1qDAI5WtCTREGbagU jOj7l2ffihEhjYe6rZrvGnJFPsRNLtpZFbedSuuJgN/AF8KiRQkL2RBnFJ+I5t+Ar6S4 4jHbUEKSzGnKC7jS4QRrXFosQfXeEkYx4uH2LjvQkG/xNFW75WiN6tXgCc7WchwO8hCm Y9oOrh7awUn4nFBAsGys1pbJU4Oo1q7RHoXnR/ivZblMpBjQeIDkFOjYgh+yhPPKn5Zl XSXdfQ8wlrVORp2QySmRcGCGeEbQQ8mX14FBb7kpoGVd6Hxz4DIvPwY8Du1q0V68Jy1L o9oA== X-Gm-Message-State: AOAM533tMyWrxzHNShQ8YIBDUHNFTtUtxSP394qfnnctTZ6xnzl1bVFT tNh2G9wFNUei0HWbytnPxNA= X-Google-Smtp-Source: ABdhPJz+kchjM0+Y+caAORBcP4bOCiZCk8hlvojmXePkcpBlA3X9hi+1uLRIu4Pe1taJjSKn5phlcg== X-Received: by 2002:a2e:5016:: with SMTP id e22mr137752ljb.301.1604533511420; Wed, 04 Nov 2020 15:45:11 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:10 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 11/30] drm/tegra: dc: Support OPP and SoC core voltage scaling Date: Thu, 5 Nov 2020 02:44:08 +0300 Message-Id: <20201104234427.26477-12-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add OPP and SoC core voltage scaling support to the display controller driver. This is required for enabling system-wide DVFS on older Tegra SoCs. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/Kconfig | 1 + drivers/gpu/drm/tegra/dc.c | 138 +++++++++++++++++++++++++++++++++- drivers/gpu/drm/tegra/dc.h | 5 ++ 3 files changed, 143 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig index 1650a448eabd..9eec4c3fbd3b 100644 --- a/drivers/gpu/drm/tegra/Kconfig +++ b/drivers/gpu/drm/tegra/Kconfig @@ -12,6 +12,7 @@ config DRM_TEGRA select INTERCONNECT select IOMMU_IOVA select CEC_CORE if CEC_NOTIFIER + select PM_OPP help Choose this option if you have an NVIDIA Tegra SoC. diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index fd7c8828652d..babcb66a335b 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -11,9 +11,13 @@ #include #include #include +#include #include +#include #include +#include +#include #include #include @@ -1699,6 +1703,55 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc, return 0; } +static void tegra_dc_update_voltage_state(struct tegra_dc *dc, + struct tegra_dc_state *state) +{ + struct dev_pm_opp *opp; + unsigned long rate; + int err, min_uV; + + /* OPP usage is optional */ + if (!dc->opp_table) + return; + + /* calculate actual pixel clock rate which depends on internal divider */ + rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); + + /* find suitable OPP for the rate */ + opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); + + if (opp == ERR_PTR(-ERANGE)) + opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); + + if (IS_ERR(opp)) { + dev_err(dc->dev, "failed to find OPP for %lu Hz: %ld\n", + rate, PTR_ERR(opp)); + return; + } + + min_uV = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + /* + * Voltage scaling is optional and trying to set voltage for a dummy + * regulator will error out. + */ + if (!device_property_present(dc->dev, "core-supply")) + return; + + /* + * Note that the minimum core voltage depends on the pixel clock + * rate (which depends on internal clock divider of CRTC) and not on + * the rate of the display controller clock. This is why we're not + * using dev_pm_opp_set_rate() API and instead are managing the + * voltage by ourselves. + */ + err = regulator_set_voltage(dc->core_reg, min_uV, INT_MAX); + if (err) + dev_err(dc->dev, "failed to set CORE voltage to %duV: %d\n", + min_uV, err); +} + static void tegra_dc_commit_state(struct tegra_dc *dc, struct tegra_dc_state *state) { @@ -1738,6 +1791,8 @@ static void tegra_dc_commit_state(struct tegra_dc *dc, if (err < 0) dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", dc->clk, state->pclk, err); + + tegra_dc_update_voltage_state(dc, state); } static void tegra_dc_stop(struct tegra_dc *dc) @@ -2521,6 +2576,7 @@ static int tegra_dc_runtime_suspend(struct host1x_client *client) clk_disable_unprepare(dc->clk); pm_runtime_put_sync(dev); + regulator_disable(dc->core_reg); return 0; } @@ -2531,10 +2587,16 @@ static int tegra_dc_runtime_resume(struct host1x_client *client) struct device *dev = client->dev; int err; + err = regulator_enable(dc->core_reg); + if (err < 0) { + dev_err(dev, "failed to enable CORE regulator: %d\n", err); + return err; + } + err = pm_runtime_get_sync(dev); if (err < 0) { dev_err(dev, "failed to get runtime PM: %d\n", err); - return err; + goto disable_regulator; } if (dc->soc->has_powergate) { @@ -2564,6 +2626,9 @@ static int tegra_dc_runtime_resume(struct host1x_client *client) clk_disable_unprepare(dc->clk); put_rpm: pm_runtime_put_sync(dev); +disable_regulator: + regulator_disable(dc->core_reg); + return err; } @@ -2879,6 +2944,72 @@ static int tegra_dc_couple(struct tegra_dc *dc) return 0; } +static void tegra_dc_deinit_opp_table(void *data) +{ + struct tegra_dc *dc = data; + + dev_pm_opp_of_remove_table(dc->dev); + dev_pm_opp_put_supported_hw(dc->opp_table); + dev_pm_opp_put_regulators(dc->opp_table); +} + +static int devm_tegra_dc_opp_table_init(struct tegra_dc *dc) +{ + struct opp_table *hw_opp_table; + u32 hw_version; + int err; + + /* voltage scaling is optional */ + dc->core_reg = devm_regulator_get(dc->dev, "core"); + if (IS_ERR(dc->core_reg)) + return dev_err_probe(dc->dev, PTR_ERR(dc->core_reg), + "failed to get CORE regulator\n"); + + /* legacy device-trees don't have OPP table */ + if (!device_property_present(dc->dev, "operating-points-v2")) + return 0; + + dc->opp_table = dev_pm_opp_get_opp_table(dc->dev); + if (IS_ERR(dc->opp_table)) + return dev_err_probe(dc->dev, PTR_ERR(dc->opp_table), + "failed to prepare OPP table\n"); + + if (of_machine_is_compatible("nvidia,tegra20")) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + hw_opp_table = dev_pm_opp_set_supported_hw(dc->dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(hw_opp_table); + if (err) { + dev_err(dc->dev, "failed to set supported HW: %d\n", err); + goto put_table; + } + + err = dev_pm_opp_of_add_table(dc->dev); + if (err) { + dev_err(dc->dev, "failed to add OPP table: %d\n", err); + goto put_hw; + } + + err = devm_add_action(dc->dev, tegra_dc_deinit_opp_table, dc); + if (err) + goto remove_table; + + dev_info(dc->dev, "OPP HW ver. 0x%x\n", hw_version); + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(dc->dev); +put_hw: + dev_pm_opp_put_supported_hw(dc->opp_table); +put_table: + dev_pm_opp_put_opp_table(dc->opp_table); + + return err; +} + static int tegra_dc_probe(struct platform_device *pdev) { struct tegra_dc *dc; @@ -2937,6 +3068,10 @@ static int tegra_dc_probe(struct platform_device *pdev) tegra_powergate_power_off(dc->powergate); } + err = devm_tegra_dc_opp_table_init(dc); + if (err < 0) + return err; + dc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(dc->regs)) return PTR_ERR(dc->regs); @@ -3007,6 +3142,7 @@ struct platform_driver tegra_dc_driver = { .driver = { .name = "tegra-dc", .of_match_table = tegra_dc_of_match, + .sync_state = tegra_soc_device_sync_state, }, .probe = tegra_dc_probe, .remove = tegra_dc_remove, diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index ba4ed35139fb..fd774fc5c2e4 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -13,6 +13,8 @@ #include "drm.h" +struct opp_table; +struct regulator; struct tegra_output; #define TEGRA_DC_LEGACY_PLANES_NUM 6 @@ -107,6 +109,9 @@ struct tegra_dc { struct drm_info_list *debugfs_files; const struct tegra_dc_soc_info *soc; + + struct opp_table *opp_table; + struct regulator *core_reg; }; static inline struct tegra_dc * From patchwork Wed Nov 4 23:44:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1353C6369E for ; Wed, 4 Nov 2020 23:48:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ACC2420BED for ; Wed, 4 Nov 2020 23:48:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ghbtZSME" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728918AbgKDXsN (ORCPT ); Wed, 4 Nov 2020 18:48:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733117AbgKDXpQ (ORCPT ); Wed, 4 Nov 2020 18:45:16 -0500 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8606C0613D2; Wed, 4 Nov 2020 15:45:15 -0800 (PST) Received: by mail-lj1-x242.google.com with SMTP id 23so300630ljv.7; Wed, 04 Nov 2020 15:45:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DgpC9O7p/OAbvh12N5zLQDhJcy20uIqx4wfuP8pHu74=; b=ghbtZSMEyXcmLVB3hLpNnX5/udQFezvG/2hSl1wmkaCE3ebcGcvcSojmt2uCoR5gkT nXNSJesVEBCqcR7j9rDF/7IRD5BXGLxC6r6i0a9/l9IoCV78c6W9ahrYAQQaDq8AUKQ8 mSAA1G0RputJJmFKqqHTKOKFlyCGOx6zK5kcZehKi8tGvx87G59fw9no+H91R0P+WOsS Dxg9Mm5ZtB9BVHzsE0hjR4RUN0Kuxjyu1hia/dVcDBx7jbnDgbEpVnXmLHTlHg5FKNED zbXuhDkgiic8O6NBhvHxVT0SaHnKF/Jg6AcW9fYaOyOYtj6g2kx1C/d23xvmU2TogHgj Psyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DgpC9O7p/OAbvh12N5zLQDhJcy20uIqx4wfuP8pHu74=; b=b2Q/ECb/4RERQBea8P7D7oTz8ozLjo1mSLjPTrOeSOu93LMvpovIKJDCoLt2j1JDe+ 66RKCYSLDFc0VMmBObmjbFEd/Wa01SEHdTvJfDm7z+kBSvtK7WhwblPIQs7w0Xgsp57T ENDHhwMNm+BDb408r31kBUYtl5HRsqX+l4xyf3mIpBXXwS2D+ambZ4tuLiXlgh1JiZTc PJFzIIPBt6Mx/aX61+vW1OPTKnIwFFWAPjABD9wuWwpYuKz3HFtlLhSFl6xb64J158LS OcBTnDNAEXqD5gd6sManJ/JTvxy+EzT5iwvBWB8Cz7pXaxWTNxREPnL6P9+nB9GAe2sC 20Pw== X-Gm-Message-State: AOAM531SoYwslfNiaDqHyWGtFwyKqEyYsHylGjpOP/xkj8xPE4SQsGe3 VMPf6xc+JkTFsw/kpWavRsF+i0wZw7I= X-Google-Smtp-Source: ABdhPJy08/f9Nhc8TmMhOuQfKj8d3M/5mqEeMTx5szZf2O3+2Ayf51uokSeK1yXKThLP7IivwNirNA== X-Received: by 2002:a2e:9a10:: with SMTP id o16mr126990lji.67.1604533514181; Wed, 04 Nov 2020 15:45:14 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:13 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 13/30] drm/tegra: gr2d: Support OPP and SoC core voltage scaling Date: Thu, 5 Nov 2020 02:44:10 +0300 Message-Id: <20201104234427.26477-14-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add OPP and SoC core voltage scaling support to the GR2D driver. This is required for enabling system-wide DVFS on Tegra SoCs. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/gr2d.c | 136 +++++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c index f30aa86e4c9f..6d8f9419d908 100644 --- a/drivers/gpu/drm/tegra/gr2d.c +++ b/drivers/gpu/drm/tegra/gr2d.c @@ -7,6 +7,9 @@ #include #include #include +#include + +#include #include "drm.h" #include "gem.h" @@ -185,6 +188,135 @@ static const u32 gr2d_addr_regs[] = { GR2D_VA_BASE_ADDR_SB, }; +static int gr2d_init_opp_state(struct device *dev, struct gr2d *gr2d) +{ + struct dev_pm_opp *opp; + unsigned long rate; + int err; + + /* + * If voltage regulator presents, then we could select the fastest + * clock rate, but driver doesn't support power management and + * frequency scaling yet, hence the top freq OPP will vote for a + * very high voltage that will produce lot's of heat. Let's select + * OPP for the current/default rate for now. + * + * Clock rate should be pre-initialized (i.e. it's non-zero) either + * by clock driver or by assigned clocks in a device-tree. + */ + rate = clk_get_rate(gr2d->clk); + + /* find suitable OPP for the clock rate supportable by SoC speedo ID */ + opp = dev_pm_opp_find_freq_ceil(dev, &rate); + + /* + * dev_pm_opp_set_rate() doesn't search for a floor clock rate and it + * will error out if default clock rate is too high, i.e. unsupported + * by a SoC hardware version. Hence will find floor rate by ourselves. + */ + if (opp == ERR_PTR(-ERANGE)) + opp = dev_pm_opp_find_freq_floor(dev, &rate); + + err = PTR_ERR_OR_ZERO(opp); + if (err) { + dev_err(dev, "failed to get OPP for %ld Hz: %d\n", + rate, err); + return err; + } + + dev_pm_opp_put(opp); + + /* + * First dummy rate-set initializes voltage vote by setting voltage + * in accordance to the clock rate. We need to do this because GR2D + * currently doesn't support power management and clock is permanently + * enabled. + */ + err = dev_pm_opp_set_rate(dev, rate); + if (err) { + dev_err(dev, "failed to initialize OPP clock: %d\n", err); + return err; + } + + return 0; +} + +static void gr2d_deinit_opp_table(void *data) +{ + struct device *dev = data; + struct opp_table *opp_table; + + opp_table = dev_pm_opp_get_opp_table(dev); + dev_pm_opp_of_remove_table(dev); + dev_pm_opp_put_supported_hw(opp_table); + dev_pm_opp_put_regulators(opp_table); + dev_pm_opp_put_opp_table(opp_table); +} + +static int devm_gr2d_init_opp_table(struct device *dev, struct gr2d *gr2d) +{ + struct opp_table *opp_table, *hw_opp_table; + const char *rname = "core"; + u32 hw_version; + int err; + + /* voltage scaling is optional */ + if (device_property_present(dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + if (gr2d->soc->version == 0x20) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + hw_opp_table = dev_pm_opp_set_supported_hw(dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(hw_opp_table); + if (err) { + dev_err(dev, "failed to set supported HW: %d\n", err); + goto put_table; + } + + /* + * OPP table presence is optional and we want the set_rate() of OPP + * API to work similarly to clk_set_rate() if table is missing in a + * device-tree. The add_table() errors out if OPP is missing in DT. + */ + if (device_property_present(dev, "operating-points-v2")) { + err = dev_pm_opp_of_add_table(dev); + if (err) { + dev_err(dev, "failed to add OPP table: %d\n", err); + goto put_hw; + } + + err = gr2d_init_opp_state(dev, gr2d); + if (err) + goto remove_table; + } + + err = devm_add_action(dev, gr2d_deinit_opp_table, dev); + if (err) + goto remove_table; + + dev_info(dev, "OPP HW ver. 0x%x\n", hw_version); + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(dev); +put_hw: + dev_pm_opp_put_supported_hw(opp_table); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int gr2d_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -209,6 +341,10 @@ static int gr2d_probe(struct platform_device *pdev) return PTR_ERR(gr2d->clk); } + err = devm_gr2d_init_opp_table(dev, gr2d); + if (err) + return dev_err_probe(dev, err, "failed to initialize OPP\n"); + err = clk_prepare_enable(gr2d->clk); if (err) { dev_err(dev, "cannot turn on clock\n"); From patchwork Wed Nov 4 23:44:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FC38C5DF9D for ; Wed, 4 Nov 2020 23:48:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 30B7920825 for ; Wed, 4 Nov 2020 23:48:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KXuUE5At" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387594AbgKDXsP (ORCPT ); Wed, 4 Nov 2020 18:48:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733130AbgKDXpU (ORCPT ); Wed, 4 Nov 2020 18:45:20 -0500 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D060C0613CF; Wed, 4 Nov 2020 15:45:18 -0800 (PST) Received: by mail-lf1-x142.google.com with SMTP id 74so174021lfo.5; Wed, 04 Nov 2020 15:45:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y282nJfAvr8vVLZChpZFCfyyX/0tuj7y7Sv22IVncUE=; b=KXuUE5AtEQQwD5Ono7VTFez03/G1JD8vBervS34kptx+rvhr1VPOJKtT7+tZonOL0D LYiql4lEs4GqTEMjuWMjwLYpFTuzD7peQA5Vfi9aqIs9BSwW3kmudaZudkIjvD3GG/19 35ZO/3Ss9TqW3Pu9IqRkKZAi9/OgCAGJSxlUFuLZ1vwjqCl6LSiIk6U8zGc3Rpst7ZBU tSb27R9TT1BfZzPv4RaCODS/OrnSceZlO7o7PafTCOUpsPYAQYjH7YwoeCSVAvnna70u UMigQgwIBHl5gUp2Vf4C9Cl2fch5QY2p74zsV8dYlmESyGtGEyNrKFOuJIfx0oI4pYyz 6omQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y282nJfAvr8vVLZChpZFCfyyX/0tuj7y7Sv22IVncUE=; b=jzwKErXFAH8BB4czzdZ1aIQy2NNfBiPzuJIJQbEkyekWSISckZ6czGLrXo7NfpTUPY 7BXU6UCDpI16VJvq00C1Sm1X19XeGbDcms98uNVtwnkDegufPspCM/HZkeaPgYRWKGeL S8bpswk6dJOI+3YlkRCaTURc7vK3l6L3Q3xI9TVohRAHooLucfulN6Ke4xArfe0L2Rh1 4qIRMuzJrAOR7Jm1Vlf8M+JlKnb5spTj8DPJx4NQzzatbzZgFRG2JHxFtArkfKBtgbSm 38tizOsSB6SiTQxSHmjoLSfobTvePiw60SVMS+ALnhCGZ6YQngcddfT3nopG4pS+NU6q kZaA== X-Gm-Message-State: AOAM532t2QGlqGmS6/IlSrJakmyDqQTY6tyIQYTN/QIBpU5oIgxBpfJy 16U07qKjCCMCgz3EjpZKDwY= X-Google-Smtp-Source: ABdhPJzT6zVFairbLiWCVf6U5lDlOHXMBLgiZgoTQaSae/l2568qpJolj1IwCGuZV8j/fEZhdbtdpA== X-Received: by 2002:a19:c6cc:: with SMTP id w195mr60492lff.24.1604533516983; Wed, 04 Nov 2020 15:45:16 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:16 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 15/30] drm/tegra: hdmi: Support OPP and SoC core voltage scaling Date: Thu, 5 Nov 2020 02:44:12 +0300 Message-Id: <20201104234427.26477-16-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add OPP and SoC core voltage scaling support to the HDMI driver. This is required for enabling system-wide DVFS on older Tegra SoCs. Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/hdmi.c | 63 +++++++++++++++++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index d09a24931c87..92e96990854b 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -1195,7 +1196,7 @@ static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder) h_back_porch = mode->htotal - mode->hsync_end; h_front_porch = mode->hsync_start - mode->hdisplay; - err = clk_set_rate(hdmi->clk, hdmi->pixel_clock); + err = dev_pm_opp_set_rate(hdmi->dev, hdmi->pixel_clock); if (err < 0) { dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n", err); @@ -1499,6 +1500,7 @@ static int tegra_hdmi_runtime_suspend(struct host1x_client *client) usleep_range(1000, 2000); clk_disable_unprepare(hdmi->clk); + dev_pm_opp_set_rate(hdmi->dev, 0); pm_runtime_put_sync(dev); return 0; @@ -1633,6 +1635,60 @@ static irqreturn_t tegra_hdmi_irq(int irq, void *data) return IRQ_HANDLED; } +static void tegra_hdmi_deinit_opp_table(void *data) +{ + struct device *dev = data; + struct opp_table *opp_table; + + opp_table = dev_pm_opp_get_opp_table(dev); + dev_pm_opp_of_remove_table(dev); + dev_pm_opp_put_regulators(opp_table); + dev_pm_opp_put_opp_table(opp_table); +} + +static int devm_tegra_hdmi_init_opp_table(struct device *dev) +{ + struct opp_table *opp_table; + const char *rname = "core"; + int err; + + /* voltage scaling is optional */ + if (device_property_present(dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + /* + * OPP table presence is optional and we want the set_rate() of OPP + * API to work similarly to clk_set_rate() if table is missing in a + * device-tree. The add_table() errors out if OPP is missing in DT. + */ + if (device_property_present(dev, "operating-points-v2")) { + err = dev_pm_opp_of_add_table(dev); + if (err) { + dev_err(dev, "failed to add OPP table: %d\n", err); + goto put_table; + } + } + + err = devm_add_action(dev, tegra_hdmi_deinit_opp_table, dev); + if (err) + goto remove_table; + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(dev); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int tegra_hdmi_probe(struct platform_device *pdev) { const char *level = KERN_ERR; @@ -1667,6 +1723,11 @@ static int tegra_hdmi_probe(struct platform_device *pdev) if (IS_ERR(hdmi->clk_parent)) return PTR_ERR(hdmi->clk_parent); + err = devm_tegra_hdmi_init_opp_table(&pdev->dev); + if (err) + return dev_err_probe(&pdev->dev, err, + "failed to initialize OPP\n"); + err = clk_set_parent(hdmi->clk, hdmi->clk_parent); if (err < 0) { dev_err(&pdev->dev, "failed to setup clocks: %d\n", err); From patchwork Wed Nov 4 23:44:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10D82C56201 for ; Wed, 4 Nov 2020 23:48:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BED4620867 for ; Wed, 4 Nov 2020 23:48:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nVoWtTN3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387604AbgKDXsP (ORCPT ); Wed, 4 Nov 2020 18:48:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733121AbgKDXpU (ORCPT ); Wed, 4 Nov 2020 18:45:20 -0500 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE12EC0613D2; Wed, 4 Nov 2020 15:45:19 -0800 (PST) Received: by mail-lf1-x143.google.com with SMTP id 74so174090lfo.5; Wed, 04 Nov 2020 15:45:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qlwfzgS9XHjSWBbs0HLllCSVTbcvFduzW2+0sVnum3s=; b=nVoWtTN3E27fw+e2vYrYyoK2YFjA4ez2wyReXTpMCOK05zlNCZYH9KU8VNTCldyh6L KogjTtU+Km/dOlpcLQn2ooEhWlItxvclTz3HXEsbh7EjdGrc5RhyR37hDLuFw1JSc7eO Gc9Or7OWnvqYLnm7WFCPqGQfanr0jdG2BVtlZFwMmXO6jmpVr4PrHyQblINNnM/kF/9n iJXxQ5iCJkFHRBwC70e9LmMyCg0QAvq7vlcIeqMZec23TAjDiY/YN/8hNhXMopCsDLmq tjpvSmY0HFn2Oiz+REgzPtZI/kle/4pnt7QEqGaWM6GRy0/oyF1peq7zQp8mGKIThoWY QV+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qlwfzgS9XHjSWBbs0HLllCSVTbcvFduzW2+0sVnum3s=; b=D/wfT5s62ftH1eJCZVwWF2VTifuEUh/J9ulCYaGuJ8fWNUjLzPs0OWsxzyM1Bf2CqI HTDGez2AzzAFtjoaVa3E0wx5wDiW2P/l9f4e/sgOIKmI4AXFPUGJMUMWPHqf3NNDyetr TNVEVoD3J5aNfmllFZD32lFRmtYxRFHsQRWgVvLm1b4hn61dke3Rz6p3V0l0sTHH5Pcw iziLllMa5WN64ltnDOCPI2xh3/0k0puHq9dCSaGqluVD26lbwQsZYH5XdZ0p/ROwNQ7U 2ASNyuS+ctgnJh1s03a0TPU8CuFFa1+jTXBJ94vqtpo9tLF4/Zve2DW9WONwgbC0QIsu x58A== X-Gm-Message-State: AOAM533uVtH45VEGMESm+ibHy+cRdUFKyGR+DMhtZEu9N+aGfOjIo6q8 OT9sBD674MhVbjpX+VkWGVc= X-Google-Smtp-Source: ABdhPJww/mH4JeZkOxyy6unI/bkZQkh23ChejAdpe/msVcgoHNZ7EjqsxaweoWsZLgt1vQhkJ6Bujw== X-Received: by 2002:a05:6512:32a1:: with SMTP id q1mr42540lfe.561.1604533518413; Wed, 04 Nov 2020 15:45:18 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:17 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 16/30] gpu: host1x: Support OPP and SoC core voltage scaling Date: Thu, 5 Nov 2020 02:44:13 +0300 Message-Id: <20201104234427.26477-17-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add initial OPP and SoC core voltage scaling support to the Host1x driver. This is required for enabling system-wide DVFS on older Tegra SoCs. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/gpu/host1x/Kconfig | 1 + drivers/gpu/host1x/dev.c | 87 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/drivers/gpu/host1x/Kconfig b/drivers/gpu/host1x/Kconfig index 6dab94adf25e..fba4207c35a4 100644 --- a/drivers/gpu/host1x/Kconfig +++ b/drivers/gpu/host1x/Kconfig @@ -3,6 +3,7 @@ config TEGRA_HOST1X tristate "NVIDIA Tegra host1x driver" depends on ARCH_TEGRA || (ARM && COMPILE_TEST) select IOMMU_IOVA + select PM_OPP help Driver for the NVIDIA Tegra host1x hardware. diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index d0ebb70e2fdd..06e65dc1ab19 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c @@ -13,6 +13,9 @@ #include #include #include +#include + +#include #define CREATE_TRACE_POINTS #include @@ -341,6 +344,85 @@ static void host1x_iommu_exit(struct host1x *host) } } +static void host1x_deinit_opp_table(void *data) +{ + struct device *dev = data; + struct opp_table *opp_table; + + opp_table = dev_pm_opp_get_opp_table(dev); + dev_pm_opp_of_remove_table(dev); + dev_pm_opp_put_supported_hw(opp_table); + dev_pm_opp_put_regulators(opp_table); + dev_pm_opp_put_opp_table(opp_table); +} + +static int devm_host1x_init_opp_table(struct host1x *host) +{ + struct opp_table *opp_table, *hw_opp_table; + const char *rname = "core"; + u32 hw_version; + int err; + + /* voltage scaling is optional */ + if (device_property_present(host->dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(host->dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(host->dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(host->dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + if (of_machine_is_compatible("nvidia,tegra20")) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + hw_opp_table = dev_pm_opp_set_supported_hw(host->dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(hw_opp_table); + if (err) { + dev_err(host->dev, "failed to set supported HW: %d\n", err); + goto put_table; + } + + /* + * OPP table presence is optional and we want the set_rate() of OPP + * API to work similarly to clk_set_rate() if table is missing in a + * device-tree. The add_table() errors out if OPP is missing in DT. + */ + if (device_property_present(host->dev, "operating-points-v2")) { + err = dev_pm_opp_of_add_table(host->dev); + if (err) { + dev_err(host->dev, "failed to add OPP table: %d\n", err); + goto put_hw; + } + } + + /* first dummy rate-set initializes voltage vote */ + err = dev_pm_opp_set_rate(host->dev, clk_get_rate(host->clk)); + if (err) { + dev_err(host->dev, "failed to initialize OPP clock: %d\n", err); + goto remove_table; + } + + err = devm_add_action(host->dev, host1x_deinit_opp_table, host->dev); + if (err) + goto remove_table; + + dev_info(host->dev, "OPP HW ver. 0x%x\n", hw_version); + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(host->dev); +put_hw: + dev_pm_opp_put_supported_hw(opp_table); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int host1x_probe(struct platform_device *pdev) { struct host1x *host; @@ -424,6 +506,11 @@ static int host1x_probe(struct platform_device *pdev) return err; } + err = devm_host1x_init_opp_table(host); + if (err < 0) + return dev_err_probe(&pdev->dev, err, + "failed to initialize OPP\n"); + err = host1x_iommu_init(host); if (err < 0) { dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err); From patchwork Wed Nov 4 23:44:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB982C388F7 for ; Wed, 4 Nov 2020 23:48:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A94C521527 for ; Wed, 4 Nov 2020 23:48:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cTrA1BoD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387505AbgKDXrz (ORCPT ); Wed, 4 Nov 2020 18:47:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733134AbgKDXpX (ORCPT ); Wed, 4 Nov 2020 18:45:23 -0500 Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B225FC0613D2; Wed, 4 Nov 2020 15:45:22 -0800 (PST) Received: by mail-lj1-x244.google.com with SMTP id v19so311699lji.5; Wed, 04 Nov 2020 15:45:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tYmWkaHosByI64aAoFLlLhjUXs+kckBxEWCVl+oFpnc=; b=cTrA1BoDRRykWx9zrvi5obCOxdvzunJb1sNBzUS/mcjrUtEa0+OzONd+O15pGvdZ0z zBeH778gsYKpZq7LRWlM5Vt1qWg20PxNUNt+/Lo6XsZZ6IkpZ4J/oi07gvnEN5zw0V2g hDv6oetsgS1Flk+b2d7xMVPsKRtN0xrZ0ZbREvLURa2UCDa0InHRAL3btrYjlBHrQf9x kab0o7jG9XmfeqisiGfq9zO8Eku/FIApF0E/cp6z/UTnE9ZCvjpmwu7ZmMdmC2/OcSts FLwsPBTrlhfC/v/RcZ5Aw9Wvv9Fbo9xc4HLrPGRT6zaGcrg2jicEtdmO54vZ7kS60J68 bqOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tYmWkaHosByI64aAoFLlLhjUXs+kckBxEWCVl+oFpnc=; b=IJme3UIKMyh25YJLkNVherXAbCjp4V8k/OIbKChGPkzYULh+YFRhHAi5X0whAQqHFn 0GYn6apHDN7ha4dQ0y8/LO/JXQfLBhaJX2IvzRM56HlcYIUZSvdiYLXiLxVU3UiShlHW R+ZEEYyOI/pY9ZxMCNG+PZQj//GbmmxRGmn/xBrtN2k3jtTVfwB5jARCWXaDWiOcpVjt TFIqSrZXrKcNliGQzNCqafRDQNgvksRBmdQTk3sRSQKxhVMFtrqI3rcLEH7aHyzEu2UH ryHZMNb+6czkMn2+ziVBdQtQRh6k+tvxbEdDfn4i32qi5QdnUbdCpVSMAS6p6n6DLWQX PmcA== X-Gm-Message-State: AOAM5308y4cIkGoUd2zv1hDn4G1HeOnYk1k3OBaFZ7WqKFjTqPcxrsbi eM1c67U+t8HBkCUQAoo0NkE= X-Google-Smtp-Source: ABdhPJzB7OlTS2WBx4RcVvxyMeKXhRQqSie6w2ltFjOQXHq4Xe9ynHa2INELgNdxnVC+IqPTlugvxQ== X-Received: by 2002:a2e:7018:: with SMTP id l24mr134995ljc.313.1604533521220; Wed, 04 Nov 2020 15:45:21 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:20 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 18/30] pwm: tegra: Support OPP and core voltage scaling Date: Thu, 5 Nov 2020 02:44:15 +0300 Message-Id: <20201104234427.26477-19-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add OPP and SoC core voltage scaling support to the Tegra PWM driver. This is required for enabling system-wide DVFS on older Tegra SoCs. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/pwm/Kconfig | 1 + drivers/pwm/pwm-tegra.c | 84 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 82 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 63be5362fd3a..61d35ef759f2 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -509,6 +509,7 @@ config PWM_SUN4I config PWM_TEGRA tristate "NVIDIA Tegra PWM support" depends on ARCH_TEGRA || COMPILE_TEST + select PM_OPP help Generic PWM framework driver for the PWFM controller found on NVIDIA Tegra SoCs. diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 1daf591025c0..96c253127ff3 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -42,12 +42,15 @@ #include #include #include +#include #include #include #include #include #include +#include + #define PWM_ENABLE (1 << 31) #define PWM_DUTY_WIDTH 8 #define PWM_DUTY_SHIFT 16 @@ -145,7 +148,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, required_clk_rate = (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH; - err = clk_set_rate(pc->clk, required_clk_rate); + err = dev_pm_opp_set_rate(pc->dev, required_clk_rate); if (err < 0) return -EINVAL; @@ -181,6 +184,10 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * before writing the register. Otherwise, keep it enabled. */ if (!pwm_is_enabled(pwm)) { + err = dev_pm_opp_set_rate(pc->dev, pc->clk_rate); + if (err < 0) + return err; + err = clk_prepare_enable(pc->clk); if (err < 0) return err; @@ -191,9 +198,12 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, /* * If the PWM is not enabled, turn the clock off again to save power. + * Remove OPP performance/voltage vote after disabling the clock. */ - if (!pwm_is_enabled(pwm)) + if (!pwm_is_enabled(pwm)) { clk_disable_unprepare(pc->clk); + dev_pm_opp_set_rate(pc->dev, 0); + } return 0; } @@ -204,6 +214,10 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) int rc = 0; u32 val; + rc = dev_pm_opp_set_rate(pc->dev, pc->clk_rate); + if (rc < 0) + return rc; + rc = clk_prepare_enable(pc->clk); if (rc < 0) return rc; @@ -225,6 +239,7 @@ static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) pwm_writel(pc, pwm->hwpwm, val); clk_disable_unprepare(pc->clk); + dev_pm_opp_set_rate(pc->dev, 0); } static const struct pwm_ops tegra_pwm_ops = { @@ -234,6 +249,60 @@ static const struct pwm_ops tegra_pwm_ops = { .owner = THIS_MODULE, }; +static void tegra_pwm_deinit_opp_table(void *data) +{ + struct device *dev = data; + struct opp_table *opp_table; + + opp_table = dev_pm_opp_get_opp_table(dev); + dev_pm_opp_of_remove_table(dev); + dev_pm_opp_put_regulators(opp_table); + dev_pm_opp_put_opp_table(opp_table); +} + +static int devm_tegra_pwm_init_opp_table(struct device *dev) +{ + struct opp_table *opp_table; + const char *rname = "core"; + int err; + + /* voltage scaling is optional */ + if (device_property_present(dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + /* + * OPP table presence is optional and we want the set_rate() of OPP + * API to work similarly to clk_set_rate() if table is missing in a + * device-tree. The add_table() errors out if OPP is missing in DT. + */ + if (device_property_present(dev, "operating-points-v2")) { + err = dev_pm_opp_of_add_table(dev); + if (err) { + dev_err(dev, "failed to add OPP table: %d\n", err); + goto put_table; + } + } + + err = devm_add_action(dev, tegra_pwm_deinit_opp_table, dev); + if (err) + goto remove_table; + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(dev); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int tegra_pwm_probe(struct platform_device *pdev) { struct tegra_pwm_chip *pwm; @@ -258,8 +327,12 @@ static int tegra_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); + ret = devm_tegra_pwm_init_opp_table(&pdev->dev); + if (ret) + return ret; + /* Set maximum frequency of the IP */ - ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency); + ret = dev_pm_opp_set_rate(pwm->dev, pwm->soc->max_frequency); if (ret < 0) { dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); return ret; @@ -309,6 +382,10 @@ static int tegra_pwm_remove(struct platform_device *pdev) if (WARN_ON(!pc)) return -ENODEV; + err = dev_pm_opp_set_rate(pc->dev, pc->clk_rate); + if (err < 0) + return err; + err = clk_prepare_enable(pc->clk); if (err < 0) return err; @@ -375,6 +452,7 @@ static struct platform_driver tegra_pwm_driver = { .name = "tegra-pwm", .of_match_table = tegra_pwm_of_match, .pm = &tegra_pwm_pm_ops, + .sync_state = tegra_soc_device_sync_state, }, .probe = tegra_pwm_probe, .remove = tegra_pwm_remove, From patchwork Wed Nov 4 23:44:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B544C55178 for ; Wed, 4 Nov 2020 23:47:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CDF2B20867 for ; Wed, 4 Nov 2020 23:47:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lIEXO/La" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387415AbgKDXrV (ORCPT ); Wed, 4 Nov 2020 18:47:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733143AbgKDXpZ (ORCPT ); Wed, 4 Nov 2020 18:45:25 -0500 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85234C0613CF; Wed, 4 Nov 2020 15:45:25 -0800 (PST) Received: by mail-lf1-x141.google.com with SMTP id 74so174428lfo.5; Wed, 04 Nov 2020 15:45:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bYI1lTU0u9qugSWMqSGv5A3HDa8DCxBYBbaISJenZIs=; b=lIEXO/La7Zc0VwM0c4dDJ9vgZF6JXEGcQnUDRRMwyyD10nK8kcgrNp9DgX3Du75IIT OzpoO+2Bl7PIc8Pyh1aBFhzzFuhxYw/EGzxr89Ll+MHvnacmt4aq+occ46DdFWbChWkL izUIyLqX6Bqr0wRpJMiCGaqg2/bML9hVkLcegcNewXvrIjcjdirU/fjw5hxKasYetBF0 ag405LakLuvWIXmezrX37MwwgCR2hLz4ZwMbHvpDRnPUc1zYptM9IAdfmP4GvSqjJHt3 DpNnOKNZjLv+kBhz26qVrZFveREsWzpQVEUcELKxB05MXwMJE6kz+wM2C0LgbHfqMsKs A2gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bYI1lTU0u9qugSWMqSGv5A3HDa8DCxBYBbaISJenZIs=; b=VD23WUI/Iw9+s38Vg7zoOyUSj77CJTkl4oqVOeQuEVNk41Cr4W+AxINkEnY1yuBbK/ hMipYrDvC8bu1GWehfik3MJ7B2y5lCsu10ccyDIqJ5sONdz3WdF8RmWXGRFLFaR700mJ 426bTVx0DwyjSP9RLp9ZNgyKugM6L6YAwiOxkHfPcMuyiPnKcFD/yjT5tml4u9NAeyYL EGA/dXqDnnD0gLZBcq74udmM+X23BQkmnSdmKZLFcNfGN9u1P5GW9270gs8qs2ejJa/9 LGCKqrvkKTqAHXGjg6jKZDRR83oXyNBlLC5pcbfM9nFOx0owMPnk/Fl4QvxuGeE6C2I9 P1xw== X-Gm-Message-State: AOAM532/a1dHDvUt+Fs3ZJ3azm+6o9KuzK28puFwj+akkEAj2pRJxnM4 VpzEfNqsZnKmwP/R6397MI0= X-Google-Smtp-Source: ABdhPJzQf9TUjFglxLujGELvxqeC4uglPytS2wsivLSpqjwqfzVF8NSmMtie4mgdOemR7ln3Z7XqDQ== X-Received: by 2002:a19:7409:: with SMTP id v9mr59130lfe.402.1604533524002; Wed, 04 Nov 2020 15:45:24 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:23 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 20/30] usb: chipidea: tegra: Support OPP and SoC core voltage scaling Date: Thu, 5 Nov 2020 02:44:17 +0300 Message-Id: <20201104234427.26477-21-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add initial OPP and SoC CORE voltage scaling support to the Tegra UDC driver. This is required for enabling system-wide DVFS on older Tegra SoCs. Tested-by: Peter Geis Signed-off-by: Dmitry Osipenko --- drivers/usb/chipidea/Kconfig | 1 + drivers/usb/chipidea/ci_hdrc_tegra.c | 79 ++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/drivers/usb/chipidea/Kconfig b/drivers/usb/chipidea/Kconfig index 8bafcfc6080d..6a5bc08711d6 100644 --- a/drivers/usb/chipidea/Kconfig +++ b/drivers/usb/chipidea/Kconfig @@ -56,6 +56,7 @@ config USB_CHIPIDEA_TEGRA tristate "Enable Tegra UDC glue driver" if EMBEDDED depends on OF depends on USB_CHIPIDEA_UDC + select PM_OPP default USB_CHIPIDEA endif diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c index 7455df0ede49..7f0403e810fe 100644 --- a/drivers/usb/chipidea/ci_hdrc_tegra.c +++ b/drivers/usb/chipidea/ci_hdrc_tegra.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -47,6 +48,79 @@ static const struct of_device_id tegra_udc_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra_udc_of_match); +static void tegra_udc_deinit_opp_table(void *data) +{ + struct device *dev = data; + struct opp_table *opp_table; + + opp_table = dev_pm_opp_get_opp_table(dev); + dev_pm_opp_of_remove_table(dev); + dev_pm_opp_put_regulators(opp_table); + dev_pm_opp_put_opp_table(opp_table); +} + +static int devm_tegra_udc_init_opp_table(struct device *dev) +{ + unsigned long rate = ULONG_MAX; + struct opp_table *opp_table; + const char *rname = "core"; + struct dev_pm_opp *opp; + int err; + + /* legacy device-trees don't have OPP table */ + if (!device_property_present(dev, "operating-points-v2")) + return 0; + + /* voltage scaling is optional */ + if (device_property_present(dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + err = dev_pm_opp_of_add_table(dev); + if (err) { + dev_err(dev, "failed to add OPP table: %d\n", err); + goto put_table; + } + + /* find suitable OPP for the maximum clock rate */ + opp = dev_pm_opp_find_freq_floor(dev, &rate); + err = PTR_ERR_OR_ZERO(opp); + if (err) { + dev_err(dev, "failed to get OPP: %d\n", err); + goto remove_table; + } + + dev_pm_opp_put(opp); + + /* + * First dummy rate-set initializes voltage vote by setting voltage + * in accordance to the clock rate. + */ + err = dev_pm_opp_set_rate(dev, rate); + if (err) { + dev_err(dev, "failed to initialize OPP clock: %d\n", err); + goto remove_table; + } + + err = devm_add_action(dev, tegra_udc_deinit_opp_table, dev); + if (err) + goto remove_table; + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(dev); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int tegra_udc_probe(struct platform_device *pdev) { const struct tegra_udc_soc_info *soc; @@ -77,6 +151,11 @@ static int tegra_udc_probe(struct platform_device *pdev) return err; } + err = devm_tegra_udc_init_opp_table(&pdev->dev); + if (err) + return dev_err_probe(&pdev->dev, err, + "failed to initialize OPP\n"); + err = clk_prepare_enable(udc->clk); if (err < 0) { dev_err(&pdev->dev, "failed to enable clock: %d\n", err); From patchwork Wed Nov 4 23:44:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57ED8C56201 for ; Wed, 4 Nov 2020 23:47:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 085A720825 for ; Wed, 4 Nov 2020 23:47:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TONR2+QY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387423AbgKDXrV (ORCPT ); Wed, 4 Nov 2020 18:47:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733146AbgKDXp2 (ORCPT ); Wed, 4 Nov 2020 18:45:28 -0500 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E11FC0613CF; Wed, 4 Nov 2020 15:45:28 -0800 (PST) Received: by mail-lj1-x241.google.com with SMTP id t13so277303ljk.12; Wed, 04 Nov 2020 15:45:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q04sc3lZzk/7Y2Vrk729DLPvzmihTnah64pqG8qeyNY=; b=TONR2+QYbapieLnDTf0Jk1QPqXZDWAjT9sIbfsQFU3S1ETVVTGWoJK1Ebv6MvCDAxu iFk8mmpyuk40cSTU2xGCAu0IvpyN9KggSBaUQ0HHUcphlkxTbwyPOPgcJyrtemqawCUZ IzkDtKXECzbZCA4IZob2ibn2+8dNPZTXjcCGMnrjW2yoErdNbjFSO1mXDS+eEXyo3O1Q MiuzyQ7fZ3tJFl2zUxr54tAVzMmTWH5TTg40i9bJj1HAViKxiTpO4EWYns9q1Jeg+pQs KLY3Dznjpa3LVkpFr2X2vcRQjrEZceJCA+H2N4jXkG7kOszuNZZdKNm3I1X6sEtQCAK/ tPBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q04sc3lZzk/7Y2Vrk729DLPvzmihTnah64pqG8qeyNY=; b=ttrFGMrWo9Od/wPrCniM+u/qV/rAbQdlShPfD/6ngGAWCvxiBSowQwPuWr0r8ZOFr3 gvonxSBk/utw+vFWWs8NR2il8NtUI4BzhMJ5fhRovdKu3VcTjmShpjOspVBiCpGd9Rmt 6AaqHwr4QxvA5CeoaPesgnqUZQPBBrGkNKmgvAoB3yVhJa3+9IVZTG2naz7JPkHi6oS6 10oVLuXuxaIkC0KQObw0E7gzSq/5pndSUmSb98ULAx5+DOcjVI+m7RZ2FIrhsYs6N3qS BMt6Kllc1Ug4wwtcE5mm2pwTEKtXxP+o0MmisnyRvP3dxjWXE73OSO3nIIt+j2pm4UxI sCBQ== X-Gm-Message-State: AOAM533mOLmZl8T0f4DQ5Gb+GOSKyCtl2cOqNok+cEE3buXOAaSjWi5i CibJ1gGLTjMmXLiRMvQHLUzhLe0YfBs= X-Google-Smtp-Source: ABdhPJy4JvIN2UzMvC1UGoXxnZuYWhG4YhonA0JFk9Z9oJ2zbTum5L2HXCOgLCmGf47Q0qaQDlrH3A== X-Received: by 2002:a2e:a41b:: with SMTP id p27mr161088ljn.30.1604533526786; Wed, 04 Nov 2020 15:45:26 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:26 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 22/30] memory: tegra20-emc: Support Tegra SoC device state syncing Date: Thu, 5 Nov 2020 02:44:19 +0300 Message-Id: <20201104234427.26477-23-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Sync driver state using the Tegra SoC device state syncing API, telling to regulators voltage coupler that EMC state is ready for DVFS. This is required for enabling system-wide DVFS on Tegra20. Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 9946b957bb01..b1b0a2439689 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -1129,6 +1129,12 @@ static int tegra_emc_probe(struct platform_device *pdev) return err; } +static void tegra_emc_sync_state(struct device *dev) +{ + tegra_soc_device_sync_state(dev); + icc_sync_state(dev); +} + static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra20-emc", }, {}, @@ -1141,7 +1147,7 @@ static struct platform_driver tegra_emc_driver = { .name = "tegra20-emc", .of_match_table = tegra_emc_of_match, .suppress_bind_attrs = true, - .sync_state = icc_sync_state, + .sync_state = tegra_emc_sync_state, }, }; module_platform_driver(tegra_emc_driver); From patchwork Wed Nov 4 23:44:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00229C5517A for ; Wed, 4 Nov 2020 23:47:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A1C2220867 for ; Wed, 4 Nov 2020 23:47:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qk3P32kB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387444AbgKDXrX (ORCPT ); Wed, 4 Nov 2020 18:47:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733151AbgKDXpb (ORCPT ); Wed, 4 Nov 2020 18:45:31 -0500 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CA64C0613CF; Wed, 4 Nov 2020 15:45:31 -0800 (PST) Received: by mail-lj1-x243.google.com with SMTP id m16so307899ljo.6; Wed, 04 Nov 2020 15:45:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gxZqGk/ZMf8l9UbMDIPd7jdOdhUcVHtE7WzA1PmtWDg=; b=qk3P32kBW1RxeA7PoyCNvBPLJCdtiKl4MWIBl6NSYhckS7zhpZjih/eIFQc9CfkrKR QBqI644fhQW4mLWSisC9qSW3LcACR2l1N6UxOKrY1FC0CYtGrkCoh6rru/gRIdf1Bqmy +03qrV+7THkErJ4pTIvE3jV9THFP/EmrJfyPdsFrkd/12GgeeLQCbifklpNte/IaU13V rsoPxtyGsxt9OpKcfHNiFJmzq0DgS38cEfG+8LLIq3o13wTdkHylfC2uVqVTqoG+ja9l 1n3U8+1zo6+Yjbou+fTTmq99uCbXrnAunW8QTWLuZNXRCn3gzFzWb3GmjZxLoPV2LIcP IGEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gxZqGk/ZMf8l9UbMDIPd7jdOdhUcVHtE7WzA1PmtWDg=; b=hhvTezNespKAwjXQp3N2VuuAJVgyxCxOM9w9QWL1tKXPbSivdtDelkXoUoslEQR9hm Q3cR1OPCCRVSspLoqdMao75TNQjpIhUrkZUeJEPLWmnBGIYmER3lUuf4SqQTAYBhMprI EBX9bbfLsOm/uPUE5udx+LzCPNPRQz4W0cwz0hv/Ry1VahjHhAmn039zhfSMaK44xGV1 ye9tj0zSc3HdelVSlV/mDAY42jsPZ2JMWl959s+b52BhxXGQs1eqFOmakWVR73DzEWa5 PZWEb155DEMNJV3IG/0tXAOaF/ckYOUjFFuW55H6Q+4Kz0kGx4HIPWEb/rVoKEK3Tq3l mAzw== X-Gm-Message-State: AOAM532sb2gzAsonm/nqpuqPpXzxhw4VSgj4Cu3NLm0EI4BIhngNwNdM xGQN3N/UqXSfOf0walaZDuE= X-Google-Smtp-Source: ABdhPJymtrhEAbNncSymhtYyuCPxyJyXQvnjnRaM2aoZ0BBto/FDcYNrl5JrWRN0UUQPlX8BPKiCkg== X-Received: by 2002:a2e:9098:: with SMTP id l24mr126250ljg.163.1604533529567; Wed, 04 Nov 2020 15:45:29 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:29 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 24/30] ARM: tegra: Add OPP tables for Tegra20 peripheral devices Date: Thu, 5 Nov 2020 02:44:21 +0300 Message-Id: <20201104234427.26477-25-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add OPP tables for Tegra20 SoC devices. Signed-off-by: Dmitry Osipenko --- .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 386 ++++++++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 14 + 2 files changed, 400 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi index 25b1ba73951e..792dc79d32c5 100644 --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -89,4 +89,390 @@ opp@760000000 { opp-hz = /bits/ 64 <760000000>; }; }; + + vde_dvfs_opp_table: vde-opp-table { + compatible = "operating-points-v2"; + + opp@95000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + }; + + opp@123500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0001>; + }; + + opp@123500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + }; + + opp@152000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0002>; + }; + + opp@152000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + }; + + opp@171000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + }; + + opp@209000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0001>; + }; + + opp@209000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0004>; + }; + + opp@218500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + }; + + opp@237500000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0002>; + }; + + opp@275500000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0001>; + }; + + opp@285000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + }; + + opp@300000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0001>; + }; + + opp@300000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0006>; + }; + + opp@300000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + }; + }; + + gr2d_dvfs_opp_table: gr2d-opp-table { + compatible = "operating-points-v2"; + + opp@133000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + }; + + opp@171000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + }; + + opp@247000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + }; + + opp@300000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + }; + }; + + gr3d_dvfs_opp_table: gr3d-opp-table { + compatible = "operating-points-v2"; + + opp@114000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <114000000>; + opp-supported-hw = <0x0001>; + }; + + opp@161500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0001>; + }; + + opp@161500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0002>; + }; + + opp@209000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0002>; + }; + + opp@218500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0004>; + }; + + opp@247000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + }; + + opp@247000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0008>; + }; + + opp@256500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0004>; + }; + + opp@285000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0002>; + }; + + opp@285000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0008>; + }; + + opp@304000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0001>; + }; + + opp@323000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <323000000>; + opp-supported-hw = <0x0004>; + }; + + opp@333500000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0001>; + }; + + opp@333500000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0002>; + }; + + opp@351500000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <351500000>; + opp-supported-hw = <0x0008>; + }; + + opp@361000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0002>; + }; + + opp@380000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0004>; + }; + + opp@400000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + }; + + opp@400000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0008>; + }; + }; + + host1x_dvfs_opp_table: host1x-opp-table { + compatible = "operating-points-v2"; + + opp@104500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x000F>; + }; + + opp@133000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + }; + + opp@166000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <166000000>; + opp-supported-hw = <0x000F>; + }; + }; + + usbd_dvfs_opp_table: usbd-opp-table { + compatible = "operating-points-v2"; + + opp@480000000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + }; + }; + + usb2_dvfs_opp_table: usb2-opp-table { + compatible = "operating-points-v2"; + + opp@480000000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + }; + }; + + usb3_dvfs_opp_table: usb3-opp-table { + compatible = "operating-points-v2"; + + opp@480000000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + }; + }; + + sdmmc1_dvfs_opp_table: sdmmc1-opp-table { + compatible = "operating-points-v2"; + + opp@44000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + }; + + opp@52000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + }; + }; + + sdmmc2_dvfs_opp_table: sdmmc2-opp-table { + compatible = "operating-points-v2"; + + opp@44000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + }; + + opp@52000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + }; + }; + + sdmmc3_dvfs_opp_table: sdmmc3-opp-table { + compatible = "operating-points-v2"; + + opp@44000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + }; + + opp@52000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + }; + }; + + sdmmc4_dvfs_opp_table: sdmmc4-opp-table { + compatible = "operating-points-v2"; + + opp@44000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + }; + + opp@52000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + }; + }; + + hdmi_dvfs_opp_table: hdmi-opp-table { + compatible = "operating-points-v2"; + + opp@148500000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <148500000>; + }; + }; + + dc0_dvfs_opp_table: dc0-opp-table { + compatible = "operating-points-v2"; + + opp@158000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + }; + + opp@190000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + }; + }; + + dc1_dvfs_opp_table: dc1-opp-table { + compatible = "operating-points-v2"; + + opp@158000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + }; + + opp@190000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 6ce498178105..317bdf75ff6c 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -42,6 +42,7 @@ host1x@50000000 { clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; + operating-points-v2 = <&host1x_dvfs_opp_table>; #address-cells = <1>; #size-cells = <1>; @@ -91,6 +92,7 @@ gr2d@54140000 { clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + operating-points-v2 = <&gr2d_dvfs_opp_table>; }; gr3d@54180000 { @@ -99,6 +101,7 @@ gr3d@54180000 { clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + operating-points-v2 = <&gr3d_dvfs_opp_table>; }; dc@54200000 { @@ -110,6 +113,7 @@ dc@54200000 { clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + operating-points-v2 = <&dc0_dvfs_opp_table>; nvidia,head = <0>; @@ -138,6 +142,7 @@ dc@54240000 { clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + operating-points-v2 = <&dc1_dvfs_opp_table>; nvidia,head = <1>; @@ -167,6 +172,7 @@ hdmi@54280000 { resets = <&tegra_car 51>; reset-names = "hdmi"; status = "disabled"; + operating-points-v2 = <&hdmi_dvfs_opp_table>; }; tvo@542c0000 { @@ -319,6 +325,7 @@ vde@6001a000 { clocks = <&tegra_car TEGRA20_CLK_VDE>; reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; + operating-points-v2 = <&vde_dvfs_opp_table>; }; apbmisc@70000800 { @@ -755,6 +762,7 @@ usb@c5000000 { nvidia,needs-double-reset; nvidia,phy = <&phy1>; status = "disabled"; + operating-points-v2 = <&usbd_dvfs_opp_table>; }; phy1: usb-phy@c5000000 { @@ -792,6 +800,7 @@ usb@c5004000 { reset-names = "usb"; nvidia,phy = <&phy2>; status = "disabled"; + operating-points-v2 = <&usb2_dvfs_opp_table>; }; phy2: usb-phy@c5004000 { @@ -818,6 +827,7 @@ usb@c5008000 { reset-names = "usb"; nvidia,phy = <&phy3>; status = "disabled"; + operating-points-v2 = <&usb3_dvfs_opp_table>; }; phy3: usb-phy@c5008000 { @@ -852,6 +862,7 @@ mmc@c8000000 { resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; }; mmc@c8000200 { @@ -863,6 +874,7 @@ mmc@c8000200 { resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; + operating-points-v2 = <&sdmmc2_dvfs_opp_table>; }; mmc@c8000400 { @@ -874,6 +886,7 @@ mmc@c8000400 { resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; }; mmc@c8000600 { @@ -885,6 +898,7 @@ mmc@c8000600 { resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; + operating-points-v2 = <&sdmmc4_dvfs_opp_table>; }; cpus { From patchwork Wed Nov 4 23:44:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFA50C55178 for ; Wed, 4 Nov 2020 23:46:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 69C092072E for ; Wed, 4 Nov 2020 23:46:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="V9QwES8E" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733204AbgKDXqc (ORCPT ); Wed, 4 Nov 2020 18:46:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733163AbgKDXpc (ORCPT ); Wed, 4 Nov 2020 18:45:32 -0500 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D1CFC0613CF; Wed, 4 Nov 2020 15:45:32 -0800 (PST) Received: by mail-lj1-x233.google.com with SMTP id m16so307948ljo.6; Wed, 04 Nov 2020 15:45:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yjbdf3STEE4rNnRcEhcRQiqrSN3jG7H1bJGL9sZTG9k=; b=V9QwES8ET89AOiUBRT+eIvF6XzhjS+DjpLL1iRiIsSjluQePWdwKYG8fQbEgOmC8Hs VtAmIs/35THre4bevIa58fOFVhZrzx2Kxkk2WJEt+haAknxa56i5yQ8e4V2cN0MGR8n5 BdX7n+7ud+UK+Jtwj2gIH5afHRoExPH/96HsQ/E6b9xXO+hBkem/lcVpg70kUMz3DOEc ws+Od0WSws3nRin0sWeT0g94azNFnsU8Ux9/nnK1Eito+9xUDqZOdrqq5LA9pURZsB1z AxYAwFA7x9eWkhgx4amRNLtXxn0k5r3j6B50KYP6MXZL0wHMaRp9FFMlshP1pEH/7XrF DZFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yjbdf3STEE4rNnRcEhcRQiqrSN3jG7H1bJGL9sZTG9k=; b=jEnXX9ukz9YBvRfQIcE3fOlZl5RBDYzkr3z21sl5n8CruFN8bKJBlcwLzpsFRTOzOi +OyiT4IqgSA5zjL/32hAdI5wlxXakWj7M/zrxUleC3M+qiRI/wNhLj023yROfJEosbc+ FoB1Viv5bIL5ZYtYuwhzXEWC9bk1FHznHRUE5xR4kLJrqi490EfSesbqzChv674pULMd 3tGwgElRlnaecg9xMnOPILNHw/m9XbYa0oTK4BgDhSSNqKF6/BIzExvLfgZuIvQkLrQr YCCDhcKZeT+tX4jjfDvL7/a+yTItYNF+CSd6wt3As0K4t3AMBWWa1sy0sXes2vKfzQpt uzHw== X-Gm-Message-State: AOAM533WW1DALadLvhKoHrnFhQBadhjjFNoHk3STWbAd3kBHWgN3Gyqd HdnbuQo1orlYBkgkv4nFFbI= X-Google-Smtp-Source: ABdhPJwjhPhKFt0lNe90pTR2Xw1Lb6bFLFS58uf0LIGIGb1ElMvJNr+QWIO4rLzUWk04NzQTCXFSOQ== X-Received: by 2002:a2e:9114:: with SMTP id m20mr125119ljg.203.1604533530966; Wed, 04 Nov 2020 15:45:30 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:30 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 25/30] ARM: tegra: Add OPP tables for Tegra30 peripheral devices Date: Thu, 5 Nov 2020 02:44:22 +0300 Message-Id: <20201104234427.26477-26-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add OPP tables for Tegra30 SoC devices. Signed-off-by: Dmitry Osipenko --- .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 415 ++++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 13 + 2 files changed, 428 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi index cbe84d25e726..f8c522099dfe 100644 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -380,4 +380,419 @@ opp@900000000 { opp-peak-kBps = <7200000>; }; }; + + vde_dvfs_opp_table: vde-opp-table { + compatible = "operating-points-v2"; + + opp@228000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0003>; + }; + + opp@247000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + }; + + opp@275000000,1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <275000000>; + opp-supported-hw = <0x0003>; + }; + + opp@304000000,1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + }; + + opp@332000000,1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + }; + + opp@352000000,1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <352000000>; + opp-supported-hw = <0x0004>; + }; + + opp@380000000,1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + }; + + opp@400000000,1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + }; + + opp@416000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + }; + + opp@437000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <437000000>; + opp-supported-hw = <0x0004>; + }; + + opp@484000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + }; + + opp@520000000,1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + }; + + opp@600000000,1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + }; + + gr2d_dvfs_opp_table: gr2d-opp-table { + compatible = "operating-points-v2"; + + opp@267000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + }; + + opp@285000000,1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + }; + + opp@304000000,1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + }; + + opp@332000000,1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + }; + + opp@361000000,1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + }; + + opp@380000000,1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + }; + + opp@408000000,1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + }; + + opp@416000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + }; + + opp@446000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + }; + + opp@484000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + }; + + opp@520000000,1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + }; + + opp@600000000,1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + }; + + gr3d_dvfs_opp_table: gr3d-opp-table { + compatible = "operating-points-v2"; + + opp@234000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <234000000>; + opp-supported-hw = <0x0003>; + }; + + opp@247000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0004>; + }; + + opp@285000000,1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0003>; + }; + + opp@304000000,1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0004>; + }; + + opp@332000000,1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <332000000>; + opp-supported-hw = <0x0003>; + }; + + opp@361000000,1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0004>; + }; + + opp@380000000,1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0003>; + }; + + opp@408000000,1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0004>; + }; + + opp@416000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0003>; + }; + + opp@446000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <446000000>; + opp-supported-hw = <0x0004>; + }; + + opp@484000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <484000000>; + opp-supported-hw = <0x000C>; + }; + + opp@520000000,1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <520000000>; + opp-supported-hw = <0x0004>; + }; + + opp@600000000,1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + }; + + host1x_dvfs_opp_table: host1x-opp-table { + compatible = "operating-points-v2"; + + opp@152000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0007>; + }; + + opp@188000000,1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <188000000>; + opp-supported-hw = <0x0007>; + }; + + opp@222000000,1100 { + opp-microvolt = <1100000 1100000 1350000>; + opp-hz = /bits/ 64 <222000000>; + opp-supported-hw = <0x0007>; + }; + + opp@242000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <242000000>; + opp-supported-hw = <0x0008>; + }; + + opp@254000000,1150 { + opp-microvolt = <1150000 1150000 1350000>; + opp-hz = /bits/ 64 <254000000>; + opp-supported-hw = <0x0007>; + }; + + opp@267000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <267000000>; + opp-supported-hw = <0x0007>; + }; + + opp@300000000,1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + }; + }; + + usbd_dvfs_opp_table: usbd-opp-table { + compatible = "operating-points-v2"; + + opp@480000000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + }; + }; + + usb2_dvfs_opp_table: usb2-opp-table { + compatible = "operating-points-v2"; + + opp@480000000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + }; + }; + + usb3_dvfs_opp_table: usb3-opp-table { + compatible = "operating-points-v2"; + + opp@480000000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <480000000>; + }; + }; + + sdmmc1_dvfs_opp_table: sdmmc1-opp-table { + compatible = "operating-points-v2"; + + opp@104000000 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <104000000>; + }; + + opp@208000000 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <208000000>; + }; + }; + + sdmmc3_dvfs_opp_table: sdmmc3-opp-table { + compatible = "operating-points-v2"; + + opp@104000000 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <104000000>; + }; + + opp@208000000 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <208000000>; + }; + }; + + hdmi_dvfs_opp_table: hdmi-opp-table { + compatible = "operating-points-v2"; + + opp@148500000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <148500000>; + }; + }; + + pwm_dvfs_opp_table: pwm-opp-table { + compatible = "operating-points-v2"; + + opp@408000000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <408000000>; + }; + }; + + dc0_dvfs_opp_table: dc0-opp-table { + compatible = "operating-points-v2"; + + opp@120000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <120000000>; + opp-supported-hw = <0x0009>; + }; + + opp@155000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <155000000>; + opp-supported-hw = <0x0006>; + }; + + opp@190000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0009>; + }; + + opp@268000000,1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <268000000>; + opp-supported-hw = <0x0006>; + }; + }; + + dc1_dvfs_opp_table: dc1-opp-table { + compatible = "operating-points-v2"; + + opp@120000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <120000000>; + opp-supported-hw = <0x0009>; + }; + + opp@155000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <155000000>; + opp-supported-hw = <0x0006>; + }; + + opp@190000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0009>; + }; + + opp@268000000,1050 { + opp-microvolt = <1050000 1050000 1350000>; + opp-hz = /bits/ 64 <268000000>; + opp-supported-hw = <0x0006>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 44a6dbba7081..c387d46f737c 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -123,6 +123,7 @@ host1x@50000000 { resets = <&tegra_car 28>; reset-names = "host1x"; iommus = <&mc TEGRA_SWGROUP_HC>; + operating-points-v2 = <&host1x_dvfs_opp_table>; #address-cells = <1>; #size-cells = <1>; @@ -180,6 +181,7 @@ gr2d@54140000 { clocks = <&tegra_car TEGRA30_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + operating-points-v2 = <&gr2d_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_G2>; }; @@ -193,6 +195,7 @@ gr3d@54180000 { resets = <&tegra_car 24>, <&tegra_car 98>; reset-names = "3d", "3d2"; + operating-points-v2 = <&gr3d_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_NV>, <&mc TEGRA_SWGROUP_NV2>; @@ -207,6 +210,7 @@ dc@54200000 { clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + operating-points-v2 = <&dc0_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_DC>; @@ -237,6 +241,7 @@ dc@54240000 { clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + operating-points-v2 = <&dc1_dvfs_opp_table>; iommus = <&mc TEGRA_SWGROUP_DCB>; @@ -268,6 +273,7 @@ hdmi@54280000 { resets = <&tegra_car 51>; reset-names = "hdmi"; status = "disabled"; + operating-points-v2 = <&hdmi_dvfs_opp_table>; }; tvo@542c0000 { @@ -466,6 +472,7 @@ vde@6001a000 { reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; iommus = <&mc TEGRA_SWGROUP_VDE>; + operating-points-v2 = <&vde_dvfs_opp_table>; }; apbmisc@70000800 { @@ -574,6 +581,7 @@ pwm: pwm@7000a000 { resets = <&tegra_car 17>; reset-names = "pwm"; status = "disabled"; + operating-points-v2 = <&pwm_dvfs_opp_table>; }; rtc@7000e000 { @@ -906,6 +914,7 @@ mmc@78000000 { resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; }; mmc@78000200 { @@ -928,6 +937,7 @@ mmc@78000400 { resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; }; mmc@78000600 { @@ -952,6 +962,7 @@ usb@7d000000 { nvidia,needs-double-reset; nvidia,phy = <&phy1>; status = "disabled"; + operating-points-v2 = <&usbd_dvfs_opp_table>; }; phy1: usb-phy@7d000000 { @@ -991,6 +1002,7 @@ usb@7d004000 { reset-names = "usb"; nvidia,phy = <&phy2>; status = "disabled"; + operating-points-v2 = <&usb2_dvfs_opp_table>; }; phy2: usb-phy@7d004000 { @@ -1029,6 +1041,7 @@ usb@7d008000 { reset-names = "usb"; nvidia,phy = <&phy3>; status = "disabled"; + operating-points-v2 = <&usb3_dvfs_opp_table>; }; phy3: usb-phy@7d008000 { From patchwork Wed Nov 4 23:44:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2246C4741F for ; Wed, 4 Nov 2020 23:47:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3DDD20867 for ; Wed, 4 Nov 2020 23:47:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eN4h8wmK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733223AbgKDXqe (ORCPT ); Wed, 4 Nov 2020 18:46:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733168AbgKDXpi (ORCPT ); Wed, 4 Nov 2020 18:45:38 -0500 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5E74C0613D2; Wed, 4 Nov 2020 15:45:37 -0800 (PST) Received: by mail-lf1-x134.google.com with SMTP id i6so197369lfd.1; Wed, 04 Nov 2020 15:45:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JWa430PVIqmJIbeD7KBt0TZCN2r4IZvUOeKukZUULSM=; b=eN4h8wmKVmc98I8VpVQD05mgPsSKIV8roZRuvQUi3EOcizAEVMxhK4XcKenNODUP57 Rxze2zWAWjLCIfL2dNIRIGywZvC28Gu+MslIDgcQBiINpAIgA8ayEvdgAWeaNJS/UoUw AF/ln6R+1zf+7IT8b1pPX6qDWo8FajvGF+vv4uuipo2sXIA3JUzx7p8u+ktEcwm1o1pg 8EzDhwuYDylAakt40bWirCp8sipi2Klh9G/IBYON5H8zDXGqS29eR/JqRCTc9dW4pVKR y1mExIRa9//FQnuJ5e8gfTLqClqNg3UUpnvkCzqL0KLmGCs6gxB1ftFcHku0KNIwUxDo VvhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JWa430PVIqmJIbeD7KBt0TZCN2r4IZvUOeKukZUULSM=; b=NJUutTGgR8RwypVHJLcSm5Y2Y48RPau6LXgiYq/Ov51mJ4IJYtz9/YMLf2bMebokUA 2+mE2hV6OOicjPedvV2xs/eMwzwkZGOhx9bRkhKVIX3skdvIQ6FB1wotTag11JeMI4Dh n6b1YHYZaCkxe711w16iIcNt3K2nfkIHPPxRq2MNbnjlyPVZJ8lu4kFRZipHVjJgwLaS I/3le7b7/2P5BtsA7FrUurg0OPkh35yi0iPBw5MI0JJDm+iJ+XyTRQpbzHHHa4f+Oxv+ 5BKal+Due1LhQu2pxuZxGjyLaZV6V8JqVRCBlp8BcBvuHobq0WBa/z6iqqnVXnw5zy7N pU6g== X-Gm-Message-State: AOAM5330L8GlKNXjfEpg8LfUsK6IuKAFJhdmbhP560/qqiA+n1koXEcR 7enXq0BOSzQ4nwcIcK8Pz2U= X-Google-Smtp-Source: ABdhPJz6df+Ge/OfH/yyY6XjwgEffIPjNRxtB5oKKiqUFuVW6jG9sorT54nuDmLv0xSqhkTx9fOGHg== X-Received: by 2002:a05:6512:3388:: with SMTP id h8mr60396lfg.318.1604533536417; Wed, 04 Nov 2020 15:45:36 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:35 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 29/30] ARM: tegra: cardhu-a04: Add voltage supplies to DVFS-capable devices Date: Thu, 5 Nov 2020 02:44:26 +0300 Message-Id: <20201104234427.26477-30-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add voltage supplies to DVFS-capable devices in order to enable system-wide voltage scaling. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index c1c0ca628af1..7149e5594537 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -93,6 +93,34 @@ vdd_bl2_reg: regulator@106 { gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; }; + host1x@50000000 { + core-supply = <&vddcore_reg>; + + gr2d@54140000 { + core-supply = <&vddcore_reg>; + }; + + gr3d@54180000 { + core-supply = <&vddcore_reg>; + }; + + dc@54200000 { + core-supply = <&vddcore_reg>; + }; + + dc@54240000 { + core-supply = <&vddcore_reg>; + }; + }; + + vde@6001a000 { + core-supply = <&vddcore_reg>; + }; + + pwm: pwm@7000a000 { + core-supply = <&vddcore_reg>; + }; + i2c@7000d000 { pmic: tps65911@2d { regulators { @@ -117,6 +145,22 @@ vddcore_reg: tps62361@60 { }; }; + memory-controller@7000f400 { + core-supply = <&vddcore_reg>; + }; + + mmc@78000000 { + core-supply = <&vddcore_reg>; + }; + + mmc@78000600 { + core-supply = <&vddcore_reg>; + }; + + usb@7d008000 { + core-supply = <&vddcore_reg>; + }; + cpus { cpu0: cpu@0 { cpu-supply = <&vddctrl_reg>; From patchwork Wed Nov 4 23:44:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B3ADC388F7 for ; Wed, 4 Nov 2020 23:46:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1390021527 for ; Wed, 4 Nov 2020 23:46:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OMn9xsQe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733236AbgKDXqf (ORCPT ); Wed, 4 Nov 2020 18:46:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728416AbgKDXpj (ORCPT ); Wed, 4 Nov 2020 18:45:39 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DE3FC0613CF; Wed, 4 Nov 2020 15:45:39 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id v144so127177lfa.13; Wed, 04 Nov 2020 15:45:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H3MVi35NrfPSfRw//362HseqQCwlWGtdqp60bFnUhwA=; b=OMn9xsQeCPu/4JinLc/AgoFUYFf1NUAoZIU2Zlu6R9dPQunR73wlhPP73mbb5TTpva 8JiMy8NqbA0ZUwEVbGtyIWXt0/tfNkV48rTG7UCuIXLFva4JtNhIA8GqUErMg0IIfKUE OGNdyB9H+gojt3sZ7bQ7bIApJMJ4in5sly2bBNeehvG48k/7mXjUtjndqT8kWTqY/A8g qT2PIZ20opUDRyncNfJ/LO9879zyPy4vHJoeMho7u+q9lf9+ZJxM1tYmJF+TFnEibpMR nv5gAps0odmdCDhcgB3tni2hr1hAyEgQ9NPd3AF9mNe+BxeSr5+mlHHTfY0Od+dUrfDJ v6DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H3MVi35NrfPSfRw//362HseqQCwlWGtdqp60bFnUhwA=; b=bcCbuF6g2RDnQRMis9eNvfMhoxq3ENTn9eWEqRTouEuAve/039rri5QgKp5o6UR3pi 27mub76NpLXwpnIDaHkKMcIdAnXih/Dww4cjXxLpBhDtxTrJU5OITVblqKhD5GWw/HqH HgcQtST8UJs/3vZtQHuZ+SfXzuEJn92y5AQN9vtNlxWzZoYcBJDsTTQQCDKBzo5+EVw7 kEgFfJb1Ujux/wbeq4aGAE3q451saZRgDCT+K6wGbq5Dmdx34BKd65BDGqSvdUoBGiWl 2JO7kgw1PfSKdXULZUv5y5M7CHPMYfRES3zvjYFbFbX43y2Xr1jEvBzaicEHjHIU1sld iEMw== X-Gm-Message-State: AOAM532hdMnQAwwESBVCzEGhUHr3X0de2E9C0IKPDNTxAO6kJ4VMA4KW JkEJDsJu+adTA7y5X+cAfZY= X-Google-Smtp-Source: ABdhPJwyQ9D+w6Gwu+oNG3O4q0AAu7yTKLISIo+dIOXhdhlh+KdufIVDxOlsB9IAA16GjdDdX/+EHA== X-Received: by 2002:ac2:53a5:: with SMTP id j5mr41614lfh.253.1604533537747; Wed, 04 Nov 2020 15:45:37 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:37 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 30/30] ARM: tegra: nexus7: Add voltage supplies to DVFS-capable devices Date: Thu, 5 Nov 2020 02:44:27 +0300 Message-Id: <20201104234427.26477-31-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add voltage supplies to DVFS-capable devices in order to enable system-wide voltage scaling. Signed-off-by: Dmitry Osipenko --- .../tegra30-asus-nexus7-grouper-common.dtsi | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 261e266c61d8..2b405872ad2d 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -60,7 +60,19 @@ trustzone@bfe00000 { }; host1x@50000000 { + core-supply = <&vdd_core>; + + gr2d@54140000 { + core-supply = <&vdd_core>; + }; + + gr3d@54180000 { + core-supply = <&vdd_core>; + }; + dc@54200000 { + core-supply = <&vdd_core>; + rgb { status = "okay"; @@ -72,6 +84,10 @@ lcd_output: endpoint { }; }; }; + + dc@54240000 { + core-supply = <&vdd_core>; + }; }; gpio@6000d000 { @@ -90,6 +106,10 @@ init-low-power-mode { }; }; + vde@6001a000 { + core-supply = <&vdd_core>; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -835,6 +855,7 @@ bluetooth { pwm: pwm@7000a000 { status = "okay"; + core-supply = <&vdd_core>; }; i2c@7000c400 { @@ -994,6 +1015,7 @@ sdmmc3: mmc@78000400 { mmc-pwrseq = <&brcm_wifi_pwrseq>; vmmc-supply = <&vdd_3v3_sys>; + core-supply = <&vdd_core>; vqmmc-supply = <&vdd_1v8>; /* Azurewave AW-NH665 BCM4330 */ @@ -1018,6 +1040,7 @@ usb@7d000000 { compatible = "nvidia,tegra30-udc"; status = "okay"; dr_mode = "peripheral"; + core-supply = <&vdd_core>; }; usb-phy@7d000000 {