From patchwork Tue Jan 2 18:10:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 123198 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp9254041qgn; Tue, 2 Jan 2018 10:11:52 -0800 (PST) X-Google-Smtp-Source: ACJfBovoRO3FIPJpaEK+0SNrs9Pw0Q6lEkg+ROBswG6E3Xc4SLpSglPs7kzi5+wOTu/XeQ1bG2A9 X-Received: by 10.84.130.98 with SMTP id 89mr46722842plc.199.1514916712126; Tue, 02 Jan 2018 10:11:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1514916712; cv=none; d=google.com; s=arc-20160816; b=CFoU9ybDD3mpKGecICYlJzYKgU/AhdlJQmf0F6ImIlWq98I7/oFmIyhgIT/xro5c71 q9ALNIp9BnsvkU22M32OEwEfCxTemEG2W14/M9JRGGX8IDDsFeg9dGE1wMfpbJRSxC/D wCeZi63v0nUKV5zMeVlCg9D6XjTvHxlyuZyisTtU7hqTaJnE6M+9rAcfHtvdzWAo3zKx gC4xH1kFX6lZZqRFhMI1LiozkdpD3bFGHcqvkkeChr17CciaRoCvsk4cZAND77cJHhog 0gLCSFCU/Eu9c6LjzO9d0raFDZBPQStdzg3JJqfWEC8LelwBysd5s5Z8w0urSetNpydS +woQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=06ZZjnqZQPBuocA3CzZQ6zLWSmqm2H40DGbt0tBDBfE=; b=nx1iHzPV+hx96fpRJPEDT2WPoTGy/oA0EG236Y490VpYYuCI01vykZDuQDxxjV718A 139LRgsQ1fRXkkqOk6eFmMRtYNCWb8tRybxGKw3m6sPZXQSnXWA4Fqubw1FPdov84R9U 7nJXNuSiJBH6FvhXm85LH1MoEEvEcw+9ZkuQuXqt+w645WFFYadGpVJh7Ubf4/HPLDaQ ZRqakcuT7qjPb3iZajLX+bUPPjzzB4t+bd+DU+TAqysX4q/Ct5OQ03BSpAxoioCvQfci bGro6wlTYwHkmuQ7ghC//AydBHg1TEWl+deyY6+aMqD6Al8t5qEVeNPChZCNbpVAC9kc FWXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gABcXPQJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 91si28464217pla.15.2018.01.02.10.11.51; Tue, 02 Jan 2018 10:11:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gABcXPQJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751438AbeABSLI (ORCPT + 28 others); Tue, 2 Jan 2018 13:11:08 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:43317 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751382AbeABSLF (ORCPT ); Tue, 2 Jan 2018 13:11:05 -0500 Received: by mail-wm0-f66.google.com with SMTP id n138so62462002wmg.2 for ; Tue, 02 Jan 2018 10:11:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=06ZZjnqZQPBuocA3CzZQ6zLWSmqm2H40DGbt0tBDBfE=; b=gABcXPQJaDBponWKb05fBs9TX+NwvIhpYK5Qo8EDUR8WXcYOM29NaWhwg5oLZfm0oY dn/4I4HGTgGyOhN/LcbC4y3GD085q7OKST1UqxqNj+cChifwDA0IWCgOAvvHKqGXgtIc zAJAjh0qX9Y0sFLY46LLd8ADO9nPRWheuRK1M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=06ZZjnqZQPBuocA3CzZQ6zLWSmqm2H40DGbt0tBDBfE=; b=Z++bFbmC8SjJM3iH7inekjIMfV0X37OyUTos/WX4QDJ43H02D3jNajrg26bVOQRHyf cAjX4gSgb3frp7RATsLfPbb05owOdBVmZHy5de83KyMYj3pRVCAkTiyS2S9UAbAkQo8o 4E99N8kx7yM88CRaRLMGKyYZ5lWFSBrVTe5tMNJ6DnugBNqkQqprU7ToeEpGy7my3CHx Vc9FiaPaC9kUX7qWaE4bYvxeRMnQqLvNWEKtgIsLn2mNUiFDo/mxUFnE29+RHjgtKDDg nlTOPTaYk/4TomQz/QYjDLqlMwSZ3TO2ftqCMiOgCF3FT+IZZu/DDoUJXnttV381ZayJ lrag== X-Gm-Message-State: AKGB3mKkyFGvfCCndHNd5oQKItEGiufqNCKdaEJ4DErgvnVCwN72oSp5 FnedOKIdcbkBRyQknPib7iJqJA== X-Received: by 10.28.157.7 with SMTP id g7mr32755504wme.99.1514916663796; Tue, 02 Jan 2018 10:11:03 -0800 (PST) Received: from localhost.localdomain ([160.89.138.198]) by smtp.gmail.com with ESMTPSA id f5sm16496643wrh.24.2018.01.02.10.11.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Jan 2018 10:11:03 -0800 (PST) From: Ard Biesheuvel To: linux-efi@vger.kernel.org, Ingo Molnar , Thomas Gleixner , "H . Peter Anvin" Cc: Ard Biesheuvel , linux-kernel@vger.kernel.org, Arvind Yadav , Matt Fleming , Stephen Boyd , Tyler Baicar , Vasyl Gomonovych Subject: [PATCH 2/5] arm64: efi: ignore EFI_MEMORY_XP attribute if RP and/or WP are set Date: Tue, 2 Jan 2018 18:10:39 +0000 Message-Id: <20180102181042.19074-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180102181042.19074-1-ard.biesheuvel@linaro.org> References: <20180102181042.19074-1-ard.biesheuvel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The UEFI memory map is a bit vague about how to interpret the EFI_MEMORY_XP attribute when it is combined with EFI_MEMORY_RP and/or EFI_MEMORY_WP, which have retroactively been redefined as cacheability attributes rather than permission attributes. So let's ignore EFI_MEMORY_XP if _RP and/or _WP are also set. In this case, it is likely that they are being used to describe the capability of the region (i.e., whether it has the controls to reconfigure it as non-executable) rather than the nature of the contents of the region (i.e., whether it contains data that we will never attempt to execute) Reported-by: Stephen Boyd Tested-by: Stephen Boyd Cc: Matt Fleming Signed-off-by: Ard Biesheuvel --- arch/arm64/kernel/efi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.11.0 diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c index 82cd07592519..f85ac58d08a3 100644 --- a/arch/arm64/kernel/efi.c +++ b/arch/arm64/kernel/efi.c @@ -48,7 +48,9 @@ static __init pteval_t create_mapping_protection(efi_memory_desc_t *md) return pgprot_val(PAGE_KERNEL_ROX); /* RW- */ - if (attr & EFI_MEMORY_XP || type != EFI_RUNTIME_SERVICES_CODE) + if (((attr & (EFI_MEMORY_RP | EFI_MEMORY_WP | EFI_MEMORY_XP)) == + EFI_MEMORY_XP) || + type != EFI_RUNTIME_SERVICES_CODE) return pgprot_val(PAGE_KERNEL); /* RWX */ From patchwork Tue Jan 2 18:10:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 123197 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp9253626qgn; Tue, 2 Jan 2018 10:11:22 -0800 (PST) X-Google-Smtp-Source: ACJfBoueqi0PLChgiWMw7aQkxc59k9yPPPJTFeOpiH9hYFpmSh1SWRfiHcwWj2CaR3unVuIeiz6d X-Received: by 10.99.174.7 with SMTP id q7mr30094042pgf.428.1514916682837; Tue, 02 Jan 2018 10:11:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1514916682; cv=none; d=google.com; s=arc-20160816; b=JEZOXbl65moDT7nmvGXoKBI2t7N8EGWoPgn8Yl4YHWLRnMIT0KUou4Janbb0JXD+/m HNgnxcHLgZCaL4mwqYPnG5bbcDWt+/EMen3wCSVgk8KYlc/K6mxXmF5Hcnz2IxGjc+q6 FSO8JCuXq8xjfEqd0XKFdQc1g6W0TN8Kyzcm7BPHOgrirTv60PzRQVEl/u1Deg/KBysb AW871/KifT2RYiGLf7aDaPJvpdR2nSwNRbApqbzTU0CoOjHLQvrDMMH/2NHeI26+blHz qncqjVysaGLSKO9e/390CEpxIhGJZp0aKz+lJVh5rMMQw1FPOPRGEMw5KbUiybp2ZeAH 3n+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=EiSqfULE8AoKGXR0DXQFIMswJSBl5H1u/L7624+YOZc=; b=FgoSsSXgRA+flFigyabFLG5xDD/STjBtcCHF00oZVbTmzGbwffGVBkfGalg/V+lKw9 MB1rK0KDsGWI0H2bdU+19elnH+ZepiihCUE4ygsiD8KB5IWmfwzzBK9Zz1Oww9hA3i+p NrfZSsvYrusZc8BLhG4NDzF0c9iO4gkscUYZFuCCEYmoQuoAqCtn4IsrAA4HyKD8U0Im OwR6kLW0vpPDTEtQp8XaPViFRtsxWsvvsQUY6eizaggVKURXkjGLiaSGOIzao7V2hofa AexO+VfIMJQebi5bmocGN5cBAS8t0Kjxayyfo+K9vUAKsP1xEe7BBrHtTee/8drs8NMl E3bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ecUsFNbx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g3si128445plp.124.2018.01.02.10.11.22; Tue, 02 Jan 2018 10:11:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ecUsFNbx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751528AbeABSLS (ORCPT + 28 others); Tue, 2 Jan 2018 13:11:18 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:33656 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751416AbeABSLP (ORCPT ); Tue, 2 Jan 2018 13:11:15 -0500 Received: by mail-wm0-f65.google.com with SMTP id g130so17262362wme.0 for ; Tue, 02 Jan 2018 10:11:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EiSqfULE8AoKGXR0DXQFIMswJSBl5H1u/L7624+YOZc=; b=ecUsFNbxwub7STpJcgm3vuu3ZUmoQZw4u67Sx2tEwLeijd+zPO5IQVKtB0XkdXUcSP plR8XQgI8ExPQoHAzY8NhzuexhgF63ygnMzIkXo2ONsxwo9O1RpndmY+6fDbtxnYHTYP BRFisRT9FZQDPU6E62qHya9CeBUBPhWncuk6E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EiSqfULE8AoKGXR0DXQFIMswJSBl5H1u/L7624+YOZc=; b=KDGwMqnmlp3mmKSdzBSk8DaxSKZvrjKRhurl+rMIfoFU64RXdw4fBQaCDTUzqkTZyq q5bBfggA8OJ3+QXVwFkJE9JkkD9ZaNX/K5oD018RfRwdbs6+1yj6evVKzuquxraPR80S UBVhMeN0+qiTJHa123av0s24Wd7elfizfbEhOnOiWhBrpQ/me4VBR/bLQcTiqhJqa0/u IqQGU5W7/u7IAg8Vgy1klcCRYxJrw57kBE/N6EOKvJXMb3E/eDzi2PbT6pwLdHyqE8yL 6IbCpYBLV3dCJBs9tfQCaDae/9fXky4RzaJijOy3QJpItDDE0I6CZPE/gPPz4lsQ5Y7B f7XQ== X-Gm-Message-State: AKGB3mL2oM/sI4fbeY1xwRoOtnpUDvwQz9lWKiPp2E3iXldZP4qT6ehl tp4/nW3Ihay2P+BNpXLnN91J0Q== X-Received: by 10.28.26.139 with SMTP id a133mr9138007wma.90.1514916673752; Tue, 02 Jan 2018 10:11:13 -0800 (PST) Received: from localhost.localdomain ([160.89.138.198]) by smtp.gmail.com with ESMTPSA id f5sm16496643wrh.24.2018.01.02.10.11.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Jan 2018 10:11:12 -0800 (PST) From: Ard Biesheuvel To: linux-efi@vger.kernel.org, Ingo Molnar , Thomas Gleixner , "H . Peter Anvin" Cc: Ard Biesheuvel , linux-kernel@vger.kernel.org, Arvind Yadav , Matt Fleming , Stephen Boyd , Tyler Baicar , Vasyl Gomonovych Subject: [PATCH 5/5] efi: parse ARM error information value Date: Tue, 2 Jan 2018 18:10:42 +0000 Message-Id: <20180102181042.19074-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180102181042.19074-1-ard.biesheuvel@linaro.org> References: <20180102181042.19074-1-ard.biesheuvel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tyler Baicar ARM errors just print out the error information value, then the value needs to be manually decoded as per the UEFI spec. Add decoding of the ARM error information value so that the kernel logs capture all of the valid information at first glance. ARM error information value decoding is captured in UEFI 2.7 spec tables 263-265. Signed-off-by: Tyler Baicar Cc: Matt Fleming Signed-off-by: Ard Biesheuvel --- drivers/firmware/efi/cper-arm.c | 213 +++++++++++++++++++++++++++++++++++++++- include/linux/cper.h | 44 +++++++++ 2 files changed, 255 insertions(+), 2 deletions(-) -- 2.11.0 diff --git a/drivers/firmware/efi/cper-arm.c b/drivers/firmware/efi/cper-arm.c index 4afbfed52163..698e5c8e0c8d 100644 --- a/drivers/firmware/efi/cper-arm.c +++ b/drivers/firmware/efi/cper-arm.c @@ -44,13 +44,218 @@ static const char * const arm_reg_ctx_strs[] = { "Misc. system register structure", }; +static const char * const arm_err_trans_type_strs[] = { + "Instruction", + "Data Access", + "Generic", +}; + +static const char * const arm_bus_err_op_strs[] = { + "Generic error (type cannot be determined)", + "Generic read (type of instruction or data request cannot be determined)", + "Generic write (type of instruction of data request cannot be determined)", + "Data read", + "Data write", + "Instruction fetch", + "Prefetch", +}; + +static const char * const arm_cache_err_op_strs[] = { + "Generic error (type cannot be determined)", + "Generic read (type of instruction or data request cannot be determined)", + "Generic write (type of instruction of data request cannot be determined)", + "Data read", + "Data write", + "Instruction fetch", + "Prefetch", + "Eviction", + "Snooping (processor initiated a cache snoop that resulted in an error)", + "Snooped (processor raised a cache error caused by another processor or device snooping its cache)", + "Management", +}; + +static const char * const arm_tlb_err_op_strs[] = { + "Generic error (type cannot be determined)", + "Generic read (type of instruction or data request cannot be determined)", + "Generic write (type of instruction of data request cannot be determined)", + "Data read", + "Data write", + "Instruction fetch", + "Prefetch", + "Local management operation (processor initiated a TLB management operation that resulted in an error)", + "External management operation (processor raised a TLB error caused by another processor or device broadcasting TLB operations)", +}; + +static const char * const arm_bus_err_part_type_strs[] = { + "Local processor originated request", + "Local processor responded to request", + "Local processor observed", + "Generic", +}; + +static const char * const arm_bus_err_addr_space_strs[] = { + "External Memory Access", + "Internal Memory Access", + "Unknown", + "Device Memory Access", +}; + +static void cper_print_arm_err_info(const char *pfx, u32 type, + u64 error_info) +{ + u8 trans_type, op_type, level, participation_type, address_space; + u16 mem_attributes; + bool proc_context_corrupt, corrected, precise_pc, restartable_pc; + bool time_out, access_mode; + + /* If the type is unknown, bail. */ + if (type > CPER_ARM_MAX_TYPE) + return; + + /* + * Vendor type errors have error information values that are vendor + * specific. + */ + if (type == CPER_ARM_VENDOR_ERROR) + return; + + if (error_info & CPER_ARM_ERR_VALID_TRANSACTION_TYPE) { + trans_type = ((error_info >> CPER_ARM_ERR_TRANSACTION_SHIFT) + & CPER_ARM_ERR_TRANSACTION_MASK); + if (trans_type < ARRAY_SIZE(arm_err_trans_type_strs)) { + printk("%stransaction type: %s\n", pfx, + arm_err_trans_type_strs[trans_type]); + } + } + + if (error_info & CPER_ARM_ERR_VALID_OPERATION_TYPE) { + op_type = ((error_info >> CPER_ARM_ERR_OPERATION_SHIFT) + & CPER_ARM_ERR_OPERATION_MASK); + switch (type) { + case CPER_ARM_CACHE_ERROR: + if (op_type < ARRAY_SIZE(arm_cache_err_op_strs)) { + printk("%soperation type: %s\n", pfx, + arm_cache_err_op_strs[op_type]); + } + break; + case CPER_ARM_TLB_ERROR: + if (op_type < ARRAY_SIZE(arm_tlb_err_op_strs)) { + printk("%soperation type: %s\n", pfx, + arm_tlb_err_op_strs[op_type]); + } + break; + case CPER_ARM_BUS_ERROR: + if (op_type < ARRAY_SIZE(arm_bus_err_op_strs)) { + printk("%soperation type: %s\n", pfx, + arm_bus_err_op_strs[op_type]); + } + break; + } + } + + if (error_info & CPER_ARM_ERR_VALID_LEVEL) { + level = ((error_info >> CPER_ARM_ERR_LEVEL_SHIFT) + & CPER_ARM_ERR_LEVEL_MASK); + switch (type) { + case CPER_ARM_CACHE_ERROR: + printk("%scache level: %d\n", pfx, level); + break; + case CPER_ARM_TLB_ERROR: + printk("%sTLB level: %d\n", pfx, level); + break; + case CPER_ARM_BUS_ERROR: + printk("%saffinity level at which the bus error occurred: %d\n", + pfx, level); + break; + } + } + + if (error_info & CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT) { + proc_context_corrupt = ((error_info >> CPER_ARM_ERR_PC_CORRUPT_SHIFT) + & CPER_ARM_ERR_PC_CORRUPT_MASK); + if (proc_context_corrupt) + printk("%sprocessor context corrupted\n", pfx); + else + printk("%sprocessor context not corrupted\n", pfx); + } + + if (error_info & CPER_ARM_ERR_VALID_CORRECTED) { + corrected = ((error_info >> CPER_ARM_ERR_CORRECTED_SHIFT) + & CPER_ARM_ERR_CORRECTED_MASK); + if (corrected) + printk("%sthe error has been corrected\n", pfx); + else + printk("%sthe error has not been corrected\n", pfx); + } + + if (error_info & CPER_ARM_ERR_VALID_PRECISE_PC) { + precise_pc = ((error_info >> CPER_ARM_ERR_PRECISE_PC_SHIFT) + & CPER_ARM_ERR_PRECISE_PC_MASK); + if (precise_pc) + printk("%sPC is precise\n", pfx); + else + printk("%sPC is imprecise\n", pfx); + } + + if (error_info & CPER_ARM_ERR_VALID_RESTARTABLE_PC) { + restartable_pc = ((error_info >> CPER_ARM_ERR_RESTARTABLE_PC_SHIFT) + & CPER_ARM_ERR_RESTARTABLE_PC_MASK); + if (restartable_pc) + printk("%sProgram execution can be restarted reliably at the PC associated with the error.\n", pfx); + } + + /* The rest of the fields are specific to bus errors */ + if (type != CPER_ARM_BUS_ERROR) + return; + + if (error_info & CPER_ARM_ERR_VALID_PARTICIPATION_TYPE) { + participation_type = ((error_info >> CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT) + & CPER_ARM_ERR_PARTICIPATION_TYPE_MASK); + if (participation_type < ARRAY_SIZE(arm_bus_err_part_type_strs)) { + printk("%sparticipation type: %s\n", pfx, + arm_bus_err_part_type_strs[participation_type]); + } + } + + if (error_info & CPER_ARM_ERR_VALID_TIME_OUT) { + time_out = ((error_info >> CPER_ARM_ERR_TIME_OUT_SHIFT) + & CPER_ARM_ERR_TIME_OUT_MASK); + if (time_out) + printk("%srequest timed out\n", pfx); + } + + if (error_info & CPER_ARM_ERR_VALID_ADDRESS_SPACE) { + address_space = ((error_info >> CPER_ARM_ERR_ADDRESS_SPACE_SHIFT) + & CPER_ARM_ERR_ADDRESS_SPACE_MASK); + if (address_space < ARRAY_SIZE(arm_bus_err_addr_space_strs)) { + printk("%saddress space: %s\n", pfx, + arm_bus_err_addr_space_strs[address_space]); + } + } + + if (error_info & CPER_ARM_ERR_VALID_MEM_ATTRIBUTES) { + mem_attributes = ((error_info >> CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT) + & CPER_ARM_ERR_MEM_ATTRIBUTES_MASK); + printk("%smemory access attributes:0x%x\n", pfx, mem_attributes); + } + + if (error_info & CPER_ARM_ERR_VALID_ACCESS_MODE) { + access_mode = ((error_info >> CPER_ARM_ERR_ACCESS_MODE_SHIFT) + & CPER_ARM_ERR_ACCESS_MODE_MASK); + if (access_mode) + printk("%saccess mode: normal\n", pfx); + else + printk("%saccess mode: secure\n", pfx); + } +} + void cper_print_proc_arm(const char *pfx, const struct cper_sec_proc_arm *proc) { int i, len, max_ctx_type; struct cper_arm_err_info *err_info; struct cper_arm_ctx_info *ctx_info; - char newpfx[64]; + char newpfx[64], infopfx[64]; printk("%sMIDR: 0x%016llx\n", pfx, proc->midr); @@ -102,9 +307,13 @@ void cper_print_proc_arm(const char *pfx, printk("%serror_type: %d, %s\n", newpfx, err_info->type, err_info->type < ARRAY_SIZE(cper_proc_error_type_strs) ? cper_proc_error_type_strs[err_info->type] : "unknown"); - if (err_info->validation_bits & CPER_ARM_INFO_VALID_ERR_INFO) + if (err_info->validation_bits & CPER_ARM_INFO_VALID_ERR_INFO) { printk("%serror_info: 0x%016llx\n", newpfx, err_info->error_info); + snprintf(infopfx, sizeof(infopfx), "%s%s", newpfx, INDENT_SP); + cper_print_arm_err_info(infopfx, err_info->type, + err_info->error_info); + } if (err_info->validation_bits & CPER_ARM_INFO_VALID_VIRT_ADDR) printk("%svirtual fault address: 0x%016llx\n", newpfx, err_info->virt_fault_addr); diff --git a/include/linux/cper.h b/include/linux/cper.h index 3299e43c76eb..d14ef4e77c8a 100644 --- a/include/linux/cper.h +++ b/include/linux/cper.h @@ -275,6 +275,50 @@ enum { #define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2) #define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3) +#define CPER_ARM_CACHE_ERROR 0 +#define CPER_ARM_TLB_ERROR 1 +#define CPER_ARM_BUS_ERROR 2 +#define CPER_ARM_VENDOR_ERROR 3 +#define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR + +#define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0) +#define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1) +#define CPER_ARM_ERR_VALID_LEVEL BIT(2) +#define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3) +#define CPER_ARM_ERR_VALID_CORRECTED BIT(4) +#define CPER_ARM_ERR_VALID_PRECISE_PC BIT(5) +#define CPER_ARM_ERR_VALID_RESTARTABLE_PC BIT(6) +#define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE BIT(7) +#define CPER_ARM_ERR_VALID_TIME_OUT BIT(8) +#define CPER_ARM_ERR_VALID_ADDRESS_SPACE BIT(9) +#define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES BIT(10) +#define CPER_ARM_ERR_VALID_ACCESS_MODE BIT(11) + +#define CPER_ARM_ERR_TRANSACTION_SHIFT 16 +#define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0) +#define CPER_ARM_ERR_OPERATION_SHIFT 18 +#define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0) +#define CPER_ARM_ERR_LEVEL_SHIFT 22 +#define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0) +#define CPER_ARM_ERR_PC_CORRUPT_SHIFT 25 +#define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0) +#define CPER_ARM_ERR_CORRECTED_SHIFT 26 +#define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0) +#define CPER_ARM_ERR_PRECISE_PC_SHIFT 27 +#define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0) +#define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT 28 +#define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0) +#define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT 29 +#define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0) +#define CPER_ARM_ERR_TIME_OUT_SHIFT 31 +#define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0) +#define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT 32 +#define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0) +#define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT 34 +#define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK GENMASK(8,0) +#define CPER_ARM_ERR_ACCESS_MODE_SHIFT 43 +#define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0) + /* * All tables and structs must be byte-packed to match CPER * specification, since the tables are provided by the system BIOS