From patchwork Wed Nov 4 16:48:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D00A9C4742C for ; Wed, 4 Nov 2020 16:49:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7297E206CA for ; Wed, 4 Nov 2020 16:49:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GIW9qAMd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731402AbgKDQte (ORCPT ); Wed, 4 Nov 2020 11:49:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731297AbgKDQtd (ORCPT ); Wed, 4 Nov 2020 11:49:33 -0500 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 079F4C0613D4; Wed, 4 Nov 2020 08:49:33 -0800 (PST) Received: by mail-lf1-x141.google.com with SMTP id s30so5744292lfc.4; Wed, 04 Nov 2020 08:49:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=crJJm+NJzX9nNGfEw3yeviT1h3BYRo8BzSQA7+fLOns=; b=GIW9qAMdCMH2xtWA68F2XwDqytaBnWVGD1ga01N0NTSOrl8CxFhZbSLz8FlPcfkY4K bxTV5U0FHL8cHzww8fIOe8gSlFw/OLqA3ZpsoY409KGElyH+1hlYCoraDe34iD1UD6R5 wwS184NUI/ja1ZjaVJ6YMG2H6jFK9vLQbEAJc9gSwL6Scp8P6H94gezgbYiX6Nk8ZD6J 3UuP+REx+n65fzrGi4UjHJynleoqj1NAnotzHg79F9IUHz+bCPkmM7DBtenNvsEsszkI QoMas1l7Z27AQ8YN7AONii81cQbJBeladQanNyUuzDn1hUY9lRjzOSPlxEfAoqwr30qS 4P3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=crJJm+NJzX9nNGfEw3yeviT1h3BYRo8BzSQA7+fLOns=; b=o++xsp8g+mXxOnZy5+TTQJp51ofVU9mP0X4Vt4UmDBdwTxvGUDzNimGeJwxsZJq9br 9OGvocz7H2xFSPfHLFUbGKjmItQtNovgVLX856fRXnSvJnB7Ocnl0W51FBvxpPg2UjrX +Q1dycZoMEk0RyB3zeNBfkCI7u4RBaUrHHvzY9VYGMO/VvisjLESeVfuADaW1CtqzXH4 EZsySl/aFaK9bBu0QRZO+PKyPCEL+0WhtYuL6I5zhPf8ktKuvaw2efrkSsk49KiHZaww K91PXsOufwae8j3kjwveemi2pVZXJAxGRmzDZOoz4uzDTOD3q0efowYNM7HSFrApkSNv qKWg== X-Gm-Message-State: AOAM531MvILm5H+p53r/MOXVTRx3sMJYIN3SdmypgNqo+3OcRKzU0nvm Pyrb6OwGKLyXfJIZdPNm3mk= X-Google-Smtp-Source: ABdhPJxOl7/JqZ7qhE8E22tCWDcsvDG+RX5n/zXPK169JDaNrnMVeePskTl+GlbctB+qjSNT8+N+vQ== X-Received: by 2002:ac2:5938:: with SMTP id v24mr9168385lfi.228.1604508571556; Wed, 04 Nov 2020 08:49:31 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:31 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 01/47] clk: tegra: Export Tegra20 EMC kernel symbols Date: Wed, 4 Nov 2020 19:48:37 +0300 Message-Id: <20201104164923.21238-2-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We're going to modularize Tegra EMC drivers and some of the EMC-clock driver symbols need to be exported, let's export them. Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20-emc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20-emc.c b/drivers/clk/tegra/clk-tegra20-emc.c index 03bf0009a33c..dd74b8543bf1 100644 --- a/drivers/clk/tegra/clk-tegra20-emc.c +++ b/drivers/clk/tegra/clk-tegra20-emc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -235,6 +236,7 @@ void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, emc->cb_arg = cb_arg; } } +EXPORT_SYMBOL_GPL(tegra20_clk_set_emc_round_callback); bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw) { @@ -291,3 +293,4 @@ int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same) return 0; } +EXPORT_SYMBOL_GPL(tegra20_clk_prepare_emc_mc_same_freq); From patchwork Wed Nov 4 16:48:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFD84C4742C for ; Wed, 4 Nov 2020 16:54:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 992D22072C for ; Wed, 4 Nov 2020 16:54:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Z3dfOO9E" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731394AbgKDQyG (ORCPT ); Wed, 4 Nov 2020 11:54:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731410AbgKDQtf (ORCPT ); Wed, 4 Nov 2020 11:49:35 -0500 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69439C0613D3; Wed, 4 Nov 2020 08:49:35 -0800 (PST) Received: by mail-lj1-x243.google.com with SMTP id l10so2703762lji.4; Wed, 04 Nov 2020 08:49:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IBTRolvU8VaL1YCS6g8sUoNhiFnnAzkyMcEZUpaHxEY=; b=Z3dfOO9Ea67OkV3Tijv2exUT2/K+vtzBmZ+Qq6hq+aUqPd2GsIld85fQT4TYOsJHdK 2oHvop136sQLhZQmE3qBcPPDnS7rO2aUjQ9VEICgfr/nAoP5Xgno0Tf5ngbXHWiVC4IC PaLvpuCLguhxRDdZChNb/rfXoSPK3pvSgcIcF7rTzqp8WPv3nJtZ6Y7sXmV6y7iJpIRM YqEQ3gtyJJRkMJpy3rX+YTuSU5F+V2ci/heIYH0Kr99ihQPiicNqiAzHRccWwQGbD1eX fm+BH8Jr/YkmlVriAd9EUHq/aNgE9KUL4zXMOACUfJ5Lk7yWtXGQTCP/niLv1H6HZQn0 W0cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IBTRolvU8VaL1YCS6g8sUoNhiFnnAzkyMcEZUpaHxEY=; b=oHzR8qjMpRBq9i0DsL+Sj0seNmbhoqA7uKTgB9Rh2Rau2fPOgoDEl3E7VIZXQJU7wZ 6FDZi+fyTYvZN6l4NYwbPlryWHN5uNnPOdvAEdhJ4IK8OOJNYGsC354KLAu0b76DVDSQ 208db6B3ua9trCyPbu8rri81hrzkDhNESXu+cud5R4BmytPSH9w2S7vBPQkD4UzXugOJ X2h2UpKxkzoU4RpYM5o15PKh9fb96g+bqyMXpL8MNSdPRFIKYpKw84yl5YTZ7NOGlkvA 7yeSw4XS+p+2e0pMMR51PTrQdD2SS2qCz6vixYDodRjlve9YFj1HLIuSqdE2rJjakKSp sD6Q== X-Gm-Message-State: AOAM531TSRGbVqRSWX1td6wkSFMy2JtjWpIlzITt9xDmqxtVf2YHzDWr 6tbFIlhJKWT+YwLAW+MCyXI= X-Google-Smtp-Source: ABdhPJzPhfeNNf/JRh3qD+lncCpacw7ow+jldI3XtQ0mIJlcrmMGEaMXoZJl/n41aHF5th0Rj3O0Mg== X-Received: by 2002:a2e:854c:: with SMTP id u12mr7699503ljj.297.1604508573970; Wed, 04 Nov 2020 08:49:33 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:33 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 03/47] soc/tegra: fuse: Add stub for tegra_sku_info Date: Wed, 4 Nov 2020 19:48:39 +0300 Message-Id: <20201104164923.21238-4-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Drivers that use tegra_sku_info and have COMPILE_TEST are failing to be build due to the missing stub for tegra_sku_info, thus add the missing stub. Signed-off-by: Dmitry Osipenko --- include/soc/tegra/fuse.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index c702bd2911bc..78cbc787a4dc 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -56,7 +56,11 @@ u32 tegra_read_straps(void); u32 tegra_read_ram_code(void); int tegra_fuse_readl(unsigned long offset, u32 *value); +#ifdef CONFIG_ARCH_TEGRA extern struct tegra_sku_info tegra_sku_info; +#else +static struct tegra_sku_info tegra_sku_info __maybe_unused; +#endif struct device *tegra_soc_device_register(void); From patchwork Wed Nov 4 16:48:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81A43C388F9 for ; Wed, 4 Nov 2020 16:54:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2CAC52074B for ; Wed, 4 Nov 2020 16:54:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AJScU/2V" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731429AbgKDQtj (ORCPT ); Wed, 4 Nov 2020 11:49:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731040AbgKDQti (ORCPT ); Wed, 4 Nov 2020 11:49:38 -0500 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8F56C0613D4; Wed, 4 Nov 2020 08:49:37 -0800 (PST) Received: by mail-lj1-x243.google.com with SMTP id 23so23664674ljv.7; Wed, 04 Nov 2020 08:49:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YsN85nbqgTsS+El/SUQtmvE9KBR1cwbaNWWJDf0k4lI=; b=AJScU/2VUzKHgW+HOaC7NTJ41vUc4OxAtWpYQE0GFtojrKMFUpLQ745q30moeWMQon wdSZH2uwscd0ZtQ9Bxe/r8H76c5JsoD+DYz5P9HXNH0jWbXL3Qd/pUQIxrX+3YXHpktg OHlC9MvIadTH8DhHcqHoTzi0p9L/baJp6A352nxlijtsH4m9VdyC0QG3R5/rM5xeg1pn Cr95ssc0FkGQq7kFj4Ah5fSx8ng9IWh7aZhRSVwAx0Smf68mIuZZJYzt9QzIk7G55Fwv 4QxHxt07hJywqn8vAAhoRNiEV2aIPTVlR6v7hOcjkyMimua468+F6/Oa3ruEJg48Ix0B 05Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YsN85nbqgTsS+El/SUQtmvE9KBR1cwbaNWWJDf0k4lI=; b=qeTBVoczxK4ZZzjqSr/apyCuQmZN52L9pXORVPDDCPodvrfrP0sNLFCh5BHYudoiyq maISiHF0oQs3MRBMl7C19cB83v0RPZz395J9DTi2Z+8HPMhczz4Fa8oFvvHIWdap/ikR pXYrCX6WqXw+bJxD/rV8LmdO3oEBWqJK9li8F1WBj4zLw1ERAQTp9rSTG+gxCVn7vEoq 8ER44tje2twPbU3aAJJWfAYB+qGAyp7Lj3IvgJ3FhXmRXn25L0Q9wyiW9g0rjWpgPE7S SjRGd1+55c3k9V75cwdbtJI2nCzGmXN5lQw//U/U6tFEcmoVfVQpgeLpetu9mF/q9G9M ncIw== X-Gm-Message-State: AOAM532PIGvI5hf/chavkZwT+VvLp+lhdaaae+KBUU9gxii2gIX0u3UZ 0u0KzGK9NLGR9WdnbNRlWg8= X-Google-Smtp-Source: ABdhPJyVVSkc3ic01jwE4gY9fzJuqHoq8xVpnZn9HxWe+YprF9XVQzXAYL9UyDIGqgA8ZUVOH735wA== X-Received: by 2002:a2e:b4e9:: with SMTP id s9mr11895122ljm.141.1604508576389; Wed, 04 Nov 2020 08:49:36 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:35 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 05/47] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Date: Wed, 4 Nov 2020 19:48:41 +0300 Message-Id: <20201104164923.21238-6-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra20 External Memory Controller talks to DRAM chips and it needs to be reprogrammed when memory frequency changes. Tegra Memory Controller sits behind EMC and these controllers are tightly coupled. This patch adds the new phandle property which allows to properly express connection of EMC and MC hardware in a device-tree, it also put the Tegra20 EMC binding on par with Tegra30+ EMC bindings, which is handy to have. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 567cffd37f3f..1b0d4417aad8 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -12,6 +12,7 @@ Properties: irrespective of ram-code configuration. - interrupts : Should contain EMC General interrupt. - clocks : Should contain EMC clock. +- nvidia,memory-controller : Phandle of the Memory Controller node. Child device nodes describe the memory settings for different configurations and clock rates. @@ -24,6 +25,7 @@ Example: reg = <0x7000f400 0x400>; interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; + nvidia,memory-controller = <&mc>; } From patchwork Wed Nov 4 16:48:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F401C5517A for ; Wed, 4 Nov 2020 16:49:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 45289206ED for ; Wed, 4 Nov 2020 16:49:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="o+PN+lFW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731441AbgKDQtl (ORCPT ); Wed, 4 Nov 2020 11:49:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731437AbgKDQtl (ORCPT ); Wed, 4 Nov 2020 11:49:41 -0500 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 711EDC0613D4; Wed, 4 Nov 2020 08:49:40 -0800 (PST) Received: by mail-lj1-x243.google.com with SMTP id m16so23700301ljo.6; Wed, 04 Nov 2020 08:49:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XaJT1vjZMvf/X8YLSd9ZZ4MLx0gBpwx6yTJ1gBvJkXU=; b=o+PN+lFWYPC3q/5e+PBs4YIDTtISHaS7z8ihni+Qi3cmP7lxQEqiML6aqXk/WYwBSF /Fd3sH3BMXEPP62hwlW1yjjba6gaEliSe5J0Nw02lFmDlFyI76T/qnM1ekhX8jqEV8Fl 5W/zRpZ9yupjboVSPuVKuPYD9L1kPMD7uiLB1U48vllyTMVmj2X8HPYaXcPXBbA6LD0i mW9aBfOEn6F1F+Ik146ldnJKNxUhHlJ6Zbp60VjoXWKcGnZR+eaY6qQCrv8gK0rpwRWv cJUB5c4PMJ7mnxMqrTgO66ku7UAHcxcsIVaqqMk1rBGQmHEzgH8DBx62HCPzRcvDO2Nu Bd0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XaJT1vjZMvf/X8YLSd9ZZ4MLx0gBpwx6yTJ1gBvJkXU=; b=DnKtGon3NZESwiD6JO0JCLb/AuQIU8vgR4zFdbONLsTBPJgGVH3T538XTyUrGsB5Wa hsD1u0XORzHJxQYbYJwzDUizc8oYD3CbV1DrjtydOzxYT3gUkH1ZhRvtahiUP+XWQPIe a2LZ1nLc8nyLxHMMCvLBK0GD8eHNa8pQGofuM575scwgG0OV70shvEhinneqPRIbEE8n yHOnl8z4MXxmXGYU3/S5j0IC2qCvYgHVAgqlNN5HDAu6bku/00MPY6lPKGoqYmqriEJl xs9iOqyNM0IpnE1SggWR9ArQB/Yf1EUwH7DOMf3Z4v6V8IkrYcyi8oifDFTUqtQFU3BS +vmw== X-Gm-Message-State: AOAM530au0/xl4Q0BjrHt2NVnRA/O4awoFlXl26FiGNKj82qj3p/RkDw 3dtu8qWivPHMu46DcB5vxfw= X-Google-Smtp-Source: ABdhPJxPzT4dfgMeZPtc8/pOQuOJNmNAEDQa7Z1ToMwzkGX4WNVnUqfiw9g6i3aNgPTyVvE0XlbEXA== X-Received: by 2002:a2e:b1c6:: with SMTP id e6mr6983022lja.108.1604508578791; Wed, 04 Nov 2020 08:49:38 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:38 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 07/47] dt-bindings: memory: tegra20: emc: Document new interconnect property Date: Wed, 4 Nov 2020 19:48:43 +0300 Message-Id: <20201104164923.21238-8-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org External Memory Controller is interconnected with memory controller and with external memory. Document new interconnect property which turns EMC into interconnect provider. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 1b0d4417aad8..82bc5b2ae7e5 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -13,6 +13,7 @@ Properties: - interrupts : Should contain EMC General interrupt. - clocks : Should contain EMC clock. - nvidia,memory-controller : Phandle of the Memory Controller node. +- #interconnect-cells : Should be 0. Child device nodes describe the memory settings for different configurations and clock rates. @@ -21,6 +22,7 @@ Example: memory-controller@7000f400 { #address-cells = < 1 >; #size-cells = < 0 >; + #interconnect-cells = <0>; compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x400>; interrupts = <0 78 0x04>; From patchwork Wed Nov 4 16:48:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25147C388F9 for ; Wed, 4 Nov 2020 16:53:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF8A32072C for ; Wed, 4 Nov 2020 16:53:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YQlZjqd3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731933AbgKDQxp (ORCPT ); Wed, 4 Nov 2020 11:53:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731462AbgKDQtp (ORCPT ); Wed, 4 Nov 2020 11:49:45 -0500 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8B78C0613D4; Wed, 4 Nov 2020 08:49:44 -0800 (PST) Received: by mail-lf1-x142.google.com with SMTP id 184so28004152lfd.6; Wed, 04 Nov 2020 08:49:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zPe+0/YRUBexi5uMN/GkvJXoQXyO1wntuOhCKO4PYjA=; b=YQlZjqd3Y0ufLowRJA3QsB31Y7NpZIgj+06IXOQ6+eq9+UnKMvGEu24QLivpB6A7LQ 2C4zW+03RNLuCWi8xFQ3gLq27KGfqOHNnckzGWy5EMLQX8IaP87Sts3240FZtSAKYN+E SUCUDbRt73VFUFuE8y7oUdcGaU5ZVsSyy63i/5N96/TwKBxQ5TMKlm7/iHexN1/xofuu 925pFVVX4je6OnR3uoJqKOhnCNGrWKUj9Rh3RG5JRO4QyTHrS/K2WECqVzyMfyLQlPdN +sjgDWbxOGKXItzCcp9/TE2GjGEEO0gznzTODO5xC3nTw+nbnK9DUYjQB4uxiLkZw9gn OC1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zPe+0/YRUBexi5uMN/GkvJXoQXyO1wntuOhCKO4PYjA=; b=fWahjaPiAHfhxhRgBT2yBLcgOIhf3s2SU1dyKhYmt3dbTARyiLg1h8aYljOTcRVv+R sviCc32d0LG9qEe4EpdYJMDNw9gDVYfWN1SM1Bwqq4A9AZ+jmL5BFAOsUhZTPSwnDv+Y zjFTM6sm/4BmzNrkbThp9ePMJE5D72YACJQow2sGXq1ZeM6hy227478fDoDB8JlccRPP 9Yuy4sOytlfyqf+Et3wtYB/XMYhH7vJGxudCgaBdjDDp1RzXw+FU3o9IsYEyLY/vvpRY NoQV/hyNwqpvzBgXDfwUJ7rpnYm+ZuvzWdmKz0vzzzHqmlZ3CLCjmA6LdI2VOtcllpGR 0svw== X-Gm-Message-State: AOAM532JJ+rjji1nB4t5FnMqfLjIqcqXpcV2qeuiEP8V73R14vjHcHag uSYHYFSa9ScnHcuYo2XQqwc= X-Google-Smtp-Source: ABdhPJwgk4Q5UghCChg1NU+InTF2TRZHDkQb/vK7YBZF0U7epGDBX9SNAFzBVs1YHi/JLGyKJCc3EQ== X-Received: by 2002:a05:6512:358d:: with SMTP id m13mr10940243lfr.435.1604508583465; Wed, 04 Nov 2020 08:49:43 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:43 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 11/47] dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator Date: Wed, 4 Nov 2020 19:48:47 +0300 Message-Id: <20201104164923.21238-12-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document new OPP table and voltage regulator properties which are needed for supporting dynamic voltage-frequency scaling of the memory controller. Some boards may have a fixed core voltage regulator, hence it's optional because frequency scaling still may be desired. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../memory-controllers/nvidia,tegra30-emc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index c243986db420..0a2e2c0d0fdd 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -39,6 +39,15 @@ properties: description: Phandle of the Memory Controller node. + core-supply: + description: + Phandle of voltage regulator of the SoC "core" power domain. + + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC speedo ID mask. + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -218,6 +227,7 @@ required: - clocks - nvidia,memory-controller - "#interconnect-cells" + - operating-points-v2 additionalProperties: false @@ -230,6 +240,8 @@ examples: clocks = <&tegra_car 57>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; #interconnect-cells = <0>; From patchwork Wed Nov 4 16:48:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4D68C2D0A3 for ; Wed, 4 Nov 2020 16:53:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 69CB02072C for ; Wed, 4 Nov 2020 16:53:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ccWrihjA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731478AbgKDQtr (ORCPT ); Wed, 4 Nov 2020 11:49:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731472AbgKDQtq (ORCPT ); Wed, 4 Nov 2020 11:49:46 -0500 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16455C0613D3; Wed, 4 Nov 2020 08:49:46 -0800 (PST) Received: by mail-lf1-x143.google.com with SMTP id 126so27996673lfi.8; Wed, 04 Nov 2020 08:49:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G/gWaZVsDrg+B7oJiO/GfuEeS3ySH7bEMjaW24T/nJE=; b=ccWrihjAHhkulHQ70bzhiZSEnQyNp//mzVPgwLNcwy58NU6x6EHVJXt0bg7H6ckfjp 6nxWy9kxJDTswhw1vbgY69ZlPIWn8zLR0vDx22Z4oyvOnr2gpUcJVJ6s9i3EszAX6y+H aMXYnXrhWsGnk+1HvI8BWAVMXIkP6KFNgDeQAEYOmgWb1kFz8S4VJxK6Z/dtuSDGU7t7 sub9cu89dZMxY/tjGhByjNWvOq4aPZjZVFJ0GKmdzMbQign8sgF1rn6HOighSZ4q2RjQ w8odjDAWB5scMsfGMgVpoLONwh6ORbFmatrsRPGPkWSM4+Cd8OrliotngJALQLxnLvQn UhNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G/gWaZVsDrg+B7oJiO/GfuEeS3ySH7bEMjaW24T/nJE=; b=KQlOl2QupCJawXby7nAViDjescpoFUX8WRX12f2CzSP10d58JmGWZzCnIaYBvY899N 9+FWi6Lj1ldtMPy6ID0+ziWMHf9gQCgrk8Oq4qogI0UiqRcXGzlhwbXEksv4zE4r7AqA Xu8clp4tL+7Vrer6QPCEaxTusj5X6peE3X7+ZqyxCzwWlL6t3wJVj+97lsz7Nsa7wa5c pw+9yZ7cdp50nI1+Wv6wXZUR+jBoCDMBreyNzLNeVXAZ6UU3/UIMQvqHvvwfw47sHUKJ lGnBq70dS0aj7ZiB7ZVc/AsorlZywYNzG0J3rQkOkSa6bhqJ2IyK4JwX7OZCkO1Zhq67 qGXA== X-Gm-Message-State: AOAM530BodGZtDcgYzguAk2XWTtnPl9U34YMqHar6A0qbONZvIPu5J5v PkEnhcHGwL2Yqqs4xK0cTnY= X-Google-Smtp-Source: ABdhPJxeuKyJpt41bYMUa63HVmZKLXHDeIqS5FU59NXW9QJP9vR3xVUp6iPAf5ojcqJ1hR07YmjErw== X-Received: by 2002:a19:c97:: with SMTP id 145mr10418006lfm.81.1604508584629; Wed, 04 Nov 2020 08:49:44 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:44 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 12/47] dt-bindings: memory: tegra124: mc: Document new interconnect property Date: Wed, 4 Nov 2020 19:48:48 +0300 Message-Id: <20201104164923.21238-13-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 1 + .../bindings/memory-controllers/nvidia,tegra124-mc.yaml | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 278549f9e051..8ae3dae42d6e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -345,6 +345,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; external-memory-controller@7001b000 { diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml index 84d0339505b1..7b18b4d11e0a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -40,6 +40,9 @@ properties: "#iommu-cells": const: 1 + "#interconnect-cells": + const: 1 + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -104,6 +107,7 @@ required: - clock-names - "#reset-cells" - "#iommu-cells" + - "#interconnect-cells" additionalProperties: false @@ -119,6 +123,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; emc-timings-3 { nvidia,ram-code = <3>; From patchwork Wed Nov 4 16:48:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CFAAC388F9 for ; Wed, 4 Nov 2020 16:53:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C15672151B for ; Wed, 4 Nov 2020 16:53:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="i+A+m+U9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731485AbgKDQtt (ORCPT ); Wed, 4 Nov 2020 11:49:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731477AbgKDQtr (ORCPT ); Wed, 4 Nov 2020 11:49:47 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F50BC0613D3; Wed, 4 Nov 2020 08:49:47 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id h6so28021278lfj.3; Wed, 04 Nov 2020 08:49:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7VouJsB+vObe9wiNi+HSaArrhjsYuOEOXN6ddwqBmoE=; b=i+A+m+U9oG9PJ2GgdcKu6s6FyOrcp/z8e4pJwLBBVNfvCvHQsAQ4TnbFvqLYOle4EK b9pbIRk5rVOi7nBO97CfZA6e4/dZvN3QDyH6Bx9ap8RFchDYecE6HfFRoUIuiZqu68gj 4fUYV5lirqwpjscHeH2QPyfuLwEZyKY/Qr8W/bb/tQEcAzXENNol9OocqavGROzOEmPF PNEvyqFQUlaKxbuAHeimpTdNfvoSW0N8rHf7+ANiNWFGxArhNL4EwO85csk4g/SgLbHp eBdPaqLN/JiMCH5HWPiCaM1JjsN3oLnisz1hUpci6Xs+pKIlRziVFxecgFFNdkeSk5bZ bjxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7VouJsB+vObe9wiNi+HSaArrhjsYuOEOXN6ddwqBmoE=; b=QQwk3lCsCKxPrSB+q2TQIB6AcXsp7m6EOXSJlEKGEiKrtPtyCL4DFb0marOk3I3CTM FAfL5BRI3cbAlpTyNLdTe9Dlqi2i2Lj9Sx1AXd0gjn9oV9KBdu+c+gt+S1TsVrgxRhF+ T3zCEOplmxYlCjvb/1icROsP8K/kx6li1xjHI2e9eBKgf93MTjMf/qNNAn0CJgzcqMzm axS/Mz/VqC/zRFg4JTnFfJFcFn6rS3eG0UH8uek0iU9In9E8RlVc2njGnY83ZYYrUI5T gcIg3okzbkYsXApnja9jA1nG1Q83wtejYKHgB629zbxMlGhLQuV5hzyFLNVZpqNUfNCh +VAA== X-Gm-Message-State: AOAM532sEu56JUJjQRHMXroE6Joz2e2+G4NdFt+eBX1HBA4m6uQbdAk6 XBvXEMSKYAoK/kGclNk5VsXhTwq6/j4= X-Google-Smtp-Source: ABdhPJw6FROJUyYHTBPZolgWGE8NhnAwFz7xveT9/gT29SFiGPKdwlSk6tt7dC7CuIkAEG1ySU0n6A== X-Received: by 2002:a19:5d0:: with SMTP id 199mr5498039lff.69.1604508585799; Wed, 04 Nov 2020 08:49:45 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:45 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 13/47] dt-bindings: memory: tegra124: emc: Document new interconnect property Date: Wed, 4 Nov 2020 19:48:49 +0300 Message-Id: <20201104164923.21238-14-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns External Memory Controller into interconnect provider. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 8ae3dae42d6e..ac00832ceac1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -29,6 +29,9 @@ properties: items: - const: emc + "#interconnect-cells": + const: 0 + nvidia,memory-controller: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -327,6 +330,7 @@ required: - clocks - clock-names - nvidia,memory-controller + - "#interconnect-cells" additionalProperties: false @@ -356,6 +360,8 @@ examples: nvidia,memory-controller = <&mc>; + #interconnect-cells = <0>; + emc-timings-0 { nvidia,ram-code = <3>; From patchwork Wed Nov 4 16:48:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26343C4741F for ; Wed, 4 Nov 2020 16:49:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CCE16206ED for ; Wed, 4 Nov 2020 16:49:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l3LKe/mp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731471AbgKDQtv (ORCPT ); Wed, 4 Nov 2020 11:49:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731493AbgKDQtu (ORCPT ); Wed, 4 Nov 2020 11:49:50 -0500 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BF12C0613D4; Wed, 4 Nov 2020 08:49:49 -0800 (PST) Received: by mail-lj1-x242.google.com with SMTP id y16so23729252ljk.1; Wed, 04 Nov 2020 08:49:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d/Sk3dwc3ZzPQh0+4njd7Ejlh1IFm+rB1ccMwqr+vGE=; b=l3LKe/mpPu0S8/dCOq6M2kz5lSPjJIkDiZkJ392mXO0421xd0wR0g+uOXZu3Dp6GNh tig0xwfVmcWuRwSddNabK0tKmD9eiUiHmMnpBBpYyQsiolkHs6ybryKNoGIVmvUoj6mT ZoVdAYiceuqcnDB8+mK/Y52+5BOgvmMeR8RuFYe5GfwIbOlNfG7+BJWLe6WZpsli+6Pf JdpL/bqxj2ePobj0I6x+B4d6skuRAUZdvSHHxJhupeFc3dDdE3n0DFN/kYXJWmBqH0GV 6PBYnodpQBz72zJUvr33uIEYqRK5w81me4rBiefPXZLOBAHDnuZCa6+wdwuq0NWJzPtm LWEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d/Sk3dwc3ZzPQh0+4njd7Ejlh1IFm+rB1ccMwqr+vGE=; b=qKfTEtsSWSrWgctAWYgOXQ4Jyjah02Nlt4J54rryEd/wAXEM+UYAw2RlsaIugtEbWV CPHSeTaek1Mmjt9PyMO0ImsHrrZGciSb2a7F88XoSyz6ie3fTlh4e9yAXsBg3O5Cmzxz CBIa9/LNz5PQn8LKLncZawHivQt0sWB+ADyClsj4jL8rkzJhSZ1ma6nHmkhd7yx7ITuK ziKT/c5sr0tfmNOBm8vPhONKwz5ER1EQDjqhT6z0eWWHtWW+lro6n00Pk6IVCrGn/KOY yxGC5TfXsjirY+a61vk9PIZv7PCckoHuS2kpZkva65lbvBZ9vt8YvmNEezIQvzL0TC6F npTQ== X-Gm-Message-State: AOAM530IG87kQ5oJPmWL0til37cryXF8AgJthnZZjK/coHApI+w4su8v fv2CPrNJ21WKSa/Ww9IWqsI= X-Google-Smtp-Source: ABdhPJzOM97kyPaLdS5FBsoSI5pNCOmFXgHHRAlsYMvgYsazvVkHm7oOeCMGO/mgd30CUSSL1TDgdg== X-Received: by 2002:a2e:3a08:: with SMTP id h8mr11610597lja.125.1604508588138; Wed, 04 Nov 2020 08:49:48 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:47 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 15/47] dt-bindings: tegra30-actmon: Document OPP and interconnect properties Date: Wed, 4 Nov 2020 19:48:51 +0300 Message-Id: <20201104164923.21238-16-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document EMC DFS OPP table and interconnect paths that will be used for scaling of system's memory bandwidth based on memory utilization statistics. Previously ACTMON was supposed to drive EMC clock rate directly, but now it should do it using interconnect framework in order to support shared voltage scaling in addition to the frequency scaling. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../arm/tegra/nvidia,tegra30-actmon.txt | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt index ea670a5d7ee3..897eedfa2bc8 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt @@ -18,8 +18,30 @@ clock-names. See ../../clock/clock-bindings.txt for details. ../../reset/reset.txt for details. - reset-names: Must include the following entries: - actmon +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- interconnects: Should contain entries for memory clients sitting on + MC->EMC memory interconnect path. +- interconnect-names: Should include name of the interconnect path for each + interconnect entry. Consult TRM documentation for + information about available memory clients, see MEMORY + CONTROLLER section. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: bitfield indicating SoC speedo ID mask +- opp-peak-kBps: peak bandwidth of the memory channel Example: + dfs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp@12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <51000>; + }; + ... + }; + actmon@6000c800 { compatible = "nvidia,tegra124-actmon"; reg = <0x0 0x6000c800 0x0 0x400>; @@ -29,4 +51,7 @@ Example: clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu"; }; From patchwork Wed Nov 4 16:48:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FE11C55179 for ; Wed, 4 Nov 2020 16:53:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B8002072C for ; Wed, 4 Nov 2020 16:53:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VVcD04CQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731514AbgKDQty (ORCPT ); Wed, 4 Nov 2020 11:49:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731326AbgKDQtw (ORCPT ); Wed, 4 Nov 2020 11:49:52 -0500 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BFBEC0613D3; Wed, 4 Nov 2020 08:49:52 -0800 (PST) Received: by mail-lj1-x243.google.com with SMTP id p15so23744534ljj.8; Wed, 04 Nov 2020 08:49:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oxnHcBpTwsbel9FOdCvOvGcVMdtgauZnQmlNHsVp5Wk=; b=VVcD04CQnH0c3BLQrXh1uddglBv/7SPhavdQ0eJWso/vY0grDbo/Fkxh6Dly4r1flg HoLEVy45sSPa95Cv5f9egO84I0o2e62MNpX/YWIG4fesDCJLNF0ShRD8yI+pXWVTFWDy HIyJVT4NNrK9rCvpaPMA7/C2auJ7b2GUh3S6uzgyJq8mEPtfKAhbeupDW/kygT++WMnH 3/lJZcuFt2cbBV3Mjjstc7IYIOGp6oFmRI09L+IQUrYVJ4S/rDLtXMGwJBiw5Y2ptbJS JGcWEX6o5xcSJRblb2Qjej7mGKHIDwNOjFI9JVDBzoI47aw9YYtufsziYW64mkWNSvRN NeYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oxnHcBpTwsbel9FOdCvOvGcVMdtgauZnQmlNHsVp5Wk=; b=Ty2y4Sp12/4+UvenvgPJQ7Q1liGrlMTjEttZBka/CpONTVbHJH3js2DrMpeu+Q9bZZ WsO6Z3RjCprT0UUyDiJyZ0HPR4KWl0KIJO163NM5Ak3VqFvkq+o4151QuGu9hEtOO2ml styiD2y69ex4ZRSnbOVrwVFHc5rDN4B7Q0W1cbHfBV3i5EPVfdwPoTc2jNnq3qdbFE4R i6qK5v94h2cLgX5+p8ldCJVseqIiO/LrmxJXBrE/EqeLQhWPzI27ECn/zYIZR3bQUUFG xrTm0YY0YmKRACoxLzg64dXBfR88hiMXKeUrGkOqyquam+fEPIOi7+2SGT4OQxITQX6s 5G3A== X-Gm-Message-State: AOAM531d0gWYfebQtmBjmKCveuIUtxkWrms6PymQj45vAEX99Ix1Oz5I vLgz6irIYC9Azp7qUAWzKG8= X-Google-Smtp-Source: ABdhPJzhfBMXlYWI18S++MTSPZhU9UyR3dQHKwnTiL0Uyf2OU3YVTGaRl9rOjVXV4E2ZDw6q4aFHtg== X-Received: by 2002:a2e:9cd2:: with SMTP id g18mr8150866ljj.164.1604508590557; Wed, 04 Nov 2020 08:49:50 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:50 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 17/47] dt-bindings: memory: tegra20: Add memory client IDs Date: Wed, 4 Nov 2020 19:48:53 +0300 Message-Id: <20201104164923.21238-18-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Each memory client has unique hardware ID, add these IDs. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko Acked-by: Krzysztof Kozlowski --- include/dt-bindings/memory/tegra20-mc.h | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/include/dt-bindings/memory/tegra20-mc.h b/include/dt-bindings/memory/tegra20-mc.h index 35e131eee198..6f8829508ad0 100644 --- a/include/dt-bindings/memory/tegra20-mc.h +++ b/include/dt-bindings/memory/tegra20-mc.h @@ -18,4 +18,57 @@ #define TEGRA20_MC_RESET_VDE 13 #define TEGRA20_MC_RESET_VI 14 +#define TEGRA20_MC_DISPLAY0A 0 +#define TEGRA20_MC_DISPLAY0AB 1 +#define TEGRA20_MC_DISPLAY0B 2 +#define TEGRA20_MC_DISPLAY0BB 3 +#define TEGRA20_MC_DISPLAY0C 4 +#define TEGRA20_MC_DISPLAY0CB 5 +#define TEGRA20_MC_DISPLAY1B 6 +#define TEGRA20_MC_DISPLAY1BB 7 +#define TEGRA20_MC_EPPUP 8 +#define TEGRA20_MC_G2PR 9 +#define TEGRA20_MC_G2SR 10 +#define TEGRA20_MC_MPEUNIFBR 11 +#define TEGRA20_MC_VIRUV 12 +#define TEGRA20_MC_AVPCARM7R 13 +#define TEGRA20_MC_DISPLAYHC 14 +#define TEGRA20_MC_DISPLAYHCB 15 +#define TEGRA20_MC_FDCDRD 16 +#define TEGRA20_MC_G2DR 17 +#define TEGRA20_MC_HOST1XDMAR 18 +#define TEGRA20_MC_HOST1XR 19 +#define TEGRA20_MC_IDXSRD 20 +#define TEGRA20_MC_MPCORER 21 +#define TEGRA20_MC_MPE_IPRED 22 +#define TEGRA20_MC_MPEAMEMRD 23 +#define TEGRA20_MC_MPECSRD 24 +#define TEGRA20_MC_PPCSAHBDMAR 25 +#define TEGRA20_MC_PPCSAHBSLVR 26 +#define TEGRA20_MC_TEXSRD 27 +#define TEGRA20_MC_VDEBSEVR 28 +#define TEGRA20_MC_VDEMBER 29 +#define TEGRA20_MC_VDEMCER 30 +#define TEGRA20_MC_VDETPER 31 +#define TEGRA20_MC_EPPU 32 +#define TEGRA20_MC_EPPV 33 +#define TEGRA20_MC_EPPY 34 +#define TEGRA20_MC_MPEUNIFBW 35 +#define TEGRA20_MC_VIWSB 36 +#define TEGRA20_MC_VIWU 37 +#define TEGRA20_MC_VIWV 38 +#define TEGRA20_MC_VIWY 39 +#define TEGRA20_MC_G2DW 40 +#define TEGRA20_MC_AVPCARM7W 41 +#define TEGRA20_MC_FDCDWR 42 +#define TEGRA20_MC_HOST1XW 43 +#define TEGRA20_MC_ISPW 44 +#define TEGRA20_MC_MPCOREW 45 +#define TEGRA20_MC_MPECSWR 46 +#define TEGRA20_MC_PPCSAHBDMAW 47 +#define TEGRA20_MC_PPCSAHBSLVW 48 +#define TEGRA20_MC_VDEBSEVW 49 +#define TEGRA20_MC_VDEMBEW 50 +#define TEGRA20_MC_VDETPMW 51 + #endif From patchwork Wed Nov 4 16:48:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F10F8C4742C for ; Wed, 4 Nov 2020 16:53:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A8C092087C for ; Wed, 4 Nov 2020 16:53:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l28eK///" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731712AbgKDQxM (ORCPT ); Wed, 4 Nov 2020 11:53:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731519AbgKDQty (ORCPT ); Wed, 4 Nov 2020 11:49:54 -0500 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 578F2C0613D3; Wed, 4 Nov 2020 08:49:54 -0800 (PST) Received: by mail-lf1-x141.google.com with SMTP id l2so28079515lfk.0; Wed, 04 Nov 2020 08:49:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Wup0jgVqkx9Z2UtrB2UQcATbTsL4I5PHiSg5IeKsK8=; b=l28eK///7thfjpdLXMWhiHHWDQvoZhEFc21hkIrW2nmkPIUnISNVVRI5Q5kttUvAbX HefPgitvaywJSbF6hjkjoFVpJ+2vLQ1/dFZZpb+bUt+Bd4DxzoTw2p8Pvp7REtz56vUg ZHVZ9iLdALzbjUUucAR9l9J4mD4IGqTTlPq5tydYJ76/GVhIfZOufiSYBwQZddQyZRYj wFlNveXYjeo+wcTWahXrWJxKYwnXBLjx0voygI6w+I9jYZCnW5VCNLXRbvFT2K06PAWJ fm3BMEPBOl8NH1mb3ry3IqtrsJjEFsAz9jQEW2dapu+g01OSIcXuz6T6tcfI9l3+G+ju OpdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Wup0jgVqkx9Z2UtrB2UQcATbTsL4I5PHiSg5IeKsK8=; b=Edx1ekzz88sMMTdMKhb2GDEEa2qulL5GMCX79EcKLMB7t4QvlupgUtnK9Yzky9/FID d0I3uK0bCP1fuRAkk98cEkBhV6nL9gqKBjZXoNrx1cPUESzwepWCH8vLFokvE3oaLg6V cbhmRtZSw7hbELL8x4bzikUhc2HmKBEbddp8C/sNIn+KJu7O+O5ksioeHueGXN6WwZcl 0R2FvVHL7zEQcijBuHfGHcae+/Xzg8c4m9TeB69p0wpKfRCYwpyc3U18gobQmrEu5Lnh h1V6alzEI8ZmBed3EnO8tACiB5qcizO9kXzY3+ZD35fTMqm5JgP8jL+oPRfkGGfCwZFP BMXQ== X-Gm-Message-State: AOAM531C6u8ihrYmXmrPlqRZN9R75OyvuEEgZcV7GInCmfRGiYu0v3ft uvJDyuUFMRx4XUbaiXJfJTE= X-Google-Smtp-Source: ABdhPJxEeFZ6vuDc7FfaiND2otyL3xiZBcK7Vgh1+tUpTMHt4Cy8mql9zhsl6OV8nvicmg7VAmJMHw== X-Received: by 2002:a19:c8c6:: with SMTP id y189mr3343699lff.502.1604508592892; Wed, 04 Nov 2020 08:49:52 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:52 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 19/47] dt-bindings: memory: tegra124: Add memory client IDs Date: Wed, 4 Nov 2020 19:48:55 +0300 Message-Id: <20201104164923.21238-20-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Each memory client has unique hardware ID, add these IDs. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Acked-by: Krzysztof Kozlowski --- include/dt-bindings/memory/tegra124-mc.h | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h index 186e6b7e9b35..7e73bb400eca 100644 --- a/include/dt-bindings/memory/tegra124-mc.h +++ b/include/dt-bindings/memory/tegra124-mc.h @@ -54,4 +54,72 @@ #define TEGRA124_MC_RESET_ISP2B 22 #define TEGRA124_MC_RESET_GPU 23 +#define TEGRA124_MC_PTCR 0 +#define TEGRA124_MC_DISPLAY0A 1 +#define TEGRA124_MC_DISPLAY0AB 2 +#define TEGRA124_MC_DISPLAY0B 3 +#define TEGRA124_MC_DISPLAY0BB 4 +#define TEGRA124_MC_DISPLAY0C 5 +#define TEGRA124_MC_DISPLAY0CB 6 +#define TEGRA124_MC_AFIR 14 +#define TEGRA124_MC_AVPCARM7R 15 +#define TEGRA124_MC_DISPLAYHC 16 +#define TEGRA124_MC_DISPLAYHCB 17 +#define TEGRA124_MC_HDAR 21 +#define TEGRA124_MC_HOST1XDMAR 22 +#define TEGRA124_MC_HOST1XR 23 +#define TEGRA124_MC_MSENCSRD 28 +#define TEGRA124_MC_PPCSAHBDMAR 29 +#define TEGRA124_MC_PPCSAHBSLVR 30 +#define TEGRA124_MC_SATAR 31 +#define TEGRA124_MC_VDEBSEVR 34 +#define TEGRA124_MC_VDEMBER 35 +#define TEGRA124_MC_VDEMCER 36 +#define TEGRA124_MC_VDETPER 37 +#define TEGRA124_MC_MPCORELPR 38 +#define TEGRA124_MC_MPCORER 39 +#define TEGRA124_MC_MSENCSWR 43 +#define TEGRA124_MC_AFIW 49 +#define TEGRA124_MC_AVPCARM7W 50 +#define TEGRA124_MC_HDAW 53 +#define TEGRA124_MC_HOST1XW 54 +#define TEGRA124_MC_MPCORELPW 56 +#define TEGRA124_MC_MPCOREW 57 +#define TEGRA124_MC_PPCSAHBDMAW 59 +#define TEGRA124_MC_PPCSAHBSLVW 60 +#define TEGRA124_MC_SATAW 61 +#define TEGRA124_MC_VDEBSEVW 62 +#define TEGRA124_MC_VDEDBGW 63 +#define TEGRA124_MC_VDEMBEW 64 +#define TEGRA124_MC_VDETPMW 65 +#define TEGRA124_MC_ISPRA 68 +#define TEGRA124_MC_ISPWA 70 +#define TEGRA124_MC_ISPWB 71 +#define TEGRA124_MC_XUSB_HOSTR 74 +#define TEGRA124_MC_XUSB_HOSTW 75 +#define TEGRA124_MC_XUSB_DEVR 76 +#define TEGRA124_MC_XUSB_DEVW 77 +#define TEGRA124_MC_ISPRAB 78 +#define TEGRA124_MC_ISPWAB 80 +#define TEGRA124_MC_ISPWBB 81 +#define TEGRA124_MC_TSECSRD 84 +#define TEGRA124_MC_TSECSWR 85 +#define TEGRA124_MC_A9AVPSCR 86 +#define TEGRA124_MC_A9AVPSCW 87 +#define TEGRA124_MC_GPUSRD 88 +#define TEGRA124_MC_GPUSWR 89 +#define TEGRA124_MC_DISPLAYT 90 +#define TEGRA124_MC_SDMMCRA 96 +#define TEGRA124_MC_SDMMCRAA 97 +#define TEGRA124_MC_SDMMCR 98 +#define TEGRA124_MC_SDMMCRAB 99 +#define TEGRA124_MC_SDMMCWA 100 +#define TEGRA124_MC_SDMMCWAA 101 +#define TEGRA124_MC_SDMMCW 102 +#define TEGRA124_MC_SDMMCWAB 103 +#define TEGRA124_MC_VICSRD 108 +#define TEGRA124_MC_VICSWR 109 +#define TEGRA124_MC_VIW 114 +#define TEGRA124_MC_DISPLAYD 115 + #endif From patchwork Wed Nov 4 16:48:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B330C388F9 for ; Wed, 4 Nov 2020 16:53:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0F2092072C for ; Wed, 4 Nov 2020 16:53:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="o4UnBK9i" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730924AbgKDQxF (ORCPT ); Wed, 4 Nov 2020 11:53:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731525AbgKDQtz (ORCPT ); Wed, 4 Nov 2020 11:49:55 -0500 Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77DBAC0613D3; Wed, 4 Nov 2020 08:49:55 -0800 (PST) Received: by mail-lj1-x244.google.com with SMTP id m8so17654200ljj.0; Wed, 04 Nov 2020 08:49:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZqzEltuN5moc9KsPy66tWe+lPEJWveWVX7/N9Iczqdg=; b=o4UnBK9ibQLU6a5PeuY3NJhfuI78mBN5N5b3ypqcs9Iq8a69jE87KBp/h5euFrzrMO 8TTvjki2JeoiExtYHNfLOjrOm1PFy9hEdPGL7sigDc0KRXaG6wwWy3Vpc0m15WWY7dnR H5psVV7PaxohhErmm/PRDRxLixxoobSj515fy+X7zhQ6OT7UZ3dR3BWOtg88EiA4CZ4i pENxKZNq5rIL5mZ5rBUoEEpWJFovi04W2bd6nzt14hTAjKkH881oey9Nkhgrhnz6SYWc N3BqWVM8SyTodXb5pIFXyPRHSx72OJhpfc8UEaS1gBj8vAlW+E3skWiuk75+MdI+vMJ8 Yfkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZqzEltuN5moc9KsPy66tWe+lPEJWveWVX7/N9Iczqdg=; b=iBbOGUpeH6JFu7eJ4ot+JMro1Bn9k+RbB+/vb5XC8Y+zXs1IAFLQ2YlyST5CpOdhAB TdoITgPyTpoXfzryBevCpfeywxm1wRAXWwZgMqKjl8GNoD35fxsLq6XMC6eJrg1AwiKb 8ub8L1hohEnbzTyxkxkz2+h4HyyorXDJwCMuBfqsJgNv8UPCTObIQ+raneW4C5//hWKO xdzoFagpqxwF4bCv3OylkpuEDd0ZbVObZDFPfconplT0HDqxykFA+RVqkS8WRlpy3vK2 ho5cYHXs9Axvfsjv5pVHS6s4CCTaFYeWmUib676N8mTgFkzE7/A+xHy7q0+lp79Y7ubx keOg== X-Gm-Message-State: AOAM531mYF68gxvqfpqSJmLh66kuxugvE7hYafGPuly0c/Sd2XiYHhk1 Mryl/0NJBZzc2jVtRBqKddI= X-Google-Smtp-Source: ABdhPJyeX5Yfln+dusfWz3xKWppTsZIg6ArEcqN8glIFOwU51Lb09IzPCh9OsQa4/GpcEkLlbHZ3RA== X-Received: by 2002:a05:651c:291:: with SMTP id b17mr10424595ljo.34.1604508594027; Wed, 04 Nov 2020 08:49:54 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:53 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 20/47] ARM: tegra: Correct EMC registers size in Tegra20 device-tree Date: Wed, 4 Nov 2020 19:48:56 +0300 Message-Id: <20201104164923.21238-21-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Fix the size of Tegra20 EMC registers, which should be twice bigger. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 72a4211a618f..9347f7789245 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -634,7 +634,7 @@ mc: memory-controller@7000f000 { memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x200>; + reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; From patchwork Wed Nov 4 16:48:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B9AAC5DF9D for ; Wed, 4 Nov 2020 16:52:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 056B3221E2 for ; Wed, 4 Nov 2020 16:52:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Af0j9cQy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731537AbgKDQt6 (ORCPT ); Wed, 4 Nov 2020 11:49:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731533AbgKDQt5 (ORCPT ); Wed, 4 Nov 2020 11:49:57 -0500 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BA4CC0613D3; Wed, 4 Nov 2020 08:49:56 -0800 (PST) Received: by mail-lf1-x144.google.com with SMTP id l28so27978649lfp.10; Wed, 04 Nov 2020 08:49:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qXc6alv2GyhB3hhhLZedHDIUdftmQRoQ6V9Gv1leNe8=; b=Af0j9cQyYfqwGbLNFMo8DQIbaHxPcvuBSdMbyhlOHUzt5ONJ9XckN8qb/gJe8W0Kax 8dqF6rNmTRvckvxhSt5vUrX9Fz5POWuCbXtXka2MhNt4wm0+lj2gJk7ZaFPlxGEVw2jh t/2wgt+iBONe4r/ISY4f2E4A6CvXXg7FotjG8H8XZI6DrKz7iiIte2dowE9Y2KEyZA7a 8e4kFZjJRTS2mANq/Grexnd1PzuveBBsFv8E35PY/EmpiNLwIXUrMPX05yVBLYFCEN/J 9VUUGVugNuyC7Z8tKrS4DtpEWHjTiwHX5DxHTVSrVrgBGoTzscatoKUltYZRN3M60QSc s+Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qXc6alv2GyhB3hhhLZedHDIUdftmQRoQ6V9Gv1leNe8=; b=CpTIGKPDE/eUWpfvyT4JuEy0RtmAyoI59fNs5sf2VVJd4ckSNiENH8o6XFSeFeFZpL wK5/VH2cSrjat3Ym4zjDr5FMnXHXCITeVYsCXFgEt9uGot7uD4DdUwQE5OXvvY4BejFW WzrdNkwV1rE6agvEneekvE4wWRdNFQz5wsgsNEr4KF69x7J1/XXdz5h9PFbLW5l2YWdl eLciXfL7MunE8YtA7TctwR+7wwhGFhCecIM786mpeetYdjPwIFaCwYGGtcHDMB5oxBvd rXI8/6T58cUBmozB9dzwlcrb4r0ZZwTeSnObIAv7M6a7iaX0E4/BfoZODWZbw9lrksOe Vm9g== X-Gm-Message-State: AOAM531fnkibHlb0Y4RmcvWw9F0CS7cO7fTPno4jE7PW06j7sJHUTj3v DZ+vniT0mxz7EQuO3WwKJs8= X-Google-Smtp-Source: ABdhPJzbvyLORoXyQj3/KlGwtfFDf00kuQbn6UHu0zwxqEPLW3MMMC/l9l2xEy8HWSLg8WtRXbvnjA== X-Received: by 2002:a19:441:: with SMTP id 62mr9370540lfe.304.1604508595182; Wed, 04 Nov 2020 08:49:55 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:54 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 21/47] ARM: tegra: Add interconnect properties to Tegra20 device-tree Date: Wed, 4 Nov 2020 19:48:57 +0300 Message-Id: <20201104164923.21238-22-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9347f7789245..2e1304493f7d 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -111,6 +111,17 @@ dc@54200000 { nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -128,6 +139,17 @@ dc@54240000 { nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -630,15 +652,17 @@ mc: memory-controller@7000f000 { interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; }; fuse@7000f800 { From patchwork Wed Nov 4 16:49:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEA6EC2D0A3 for ; Wed, 4 Nov 2020 16:52:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 84BEA2072C for ; Wed, 4 Nov 2020 16:52:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UO8B49/4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731175AbgKDQwm (ORCPT ); Wed, 4 Nov 2020 11:52:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731563AbgKDQuC (ORCPT ); Wed, 4 Nov 2020 11:50:02 -0500 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B64FBC061A4A; Wed, 4 Nov 2020 08:50:01 -0800 (PST) Received: by mail-lj1-x243.google.com with SMTP id 11so4151032ljf.2; Wed, 04 Nov 2020 08:50:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GW0wTe+gt5VyOxWsSiwjzI84KSD6jTTPv8IbTk0txQk=; b=UO8B49/4/0J/Dd4kNqRVZDrMBKzvxqbWhg1yiCSu3r1wkzCLNB0nWiOsbDlk3Eenqc 5koOcyu1NyZY+1RIIRU2QjiahAnF+iT+iDryD6phXzbnwWYyxNB19yHeedDkYkF+uwiL 0x2lF15HVcdhY8B5RaWVarB1z/kQRTgO+SX90omVIrTmuhKLoxRP70ghtS4WGnf/sas5 xD1v5EQ+Gr/2LlqxucLhtGIbBLqPV93h3C4hxsIDEWBipT2gNmE+d9NFfCNzGwb/Qvna RMoVO00dD2U2LX3TMFmFoL3M4bYW6qzx1vCESa7aUDNNVtCKIA//HeK5Td199qq4rkIB UzgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GW0wTe+gt5VyOxWsSiwjzI84KSD6jTTPv8IbTk0txQk=; b=CVzQ7B8oOXJSX4ybY8qsTkNv9Sreb0RlcmPJo4mfVWgiw5ORkiBajswb9PB1KJtwUK ceb8eAtUuI11g/g948ylOyFqytfwUtjImeN5pXWwX8Vn8AFf8RJD6lOvBxVGpMLqz4pP LrT0dDwB+63WwzmUEVGXbDcP3T+2wbFdsGjjRNT2exyb4KEZtlEzjwwzN1s5BI2pyUY5 pNoP1r0Ke9310aYN33lntH00J+b8tray2tCq0juOvNvSgvrvkMmk2qydYCvwuqloMYSL UEs1XKW1qS2POl6+IO+c8hjwAVenwQcRPScV0st/uNyuLPNf60FzwKmFwzJ31SfMYoMQ J1BQ== X-Gm-Message-State: AOAM531hRHnPHdmsub1XO2/l73m3X9iBlCe972aNwuJmoPeIWwxNVjIb 0KIrTmfiPwIaIEEFVN4N+b8= X-Google-Smtp-Source: ABdhPJxYt5LA8OJ6imk5L19+n35f/XwsirbwfkDWccRyA8FcxeSb9Hgowa82LH8ZXxK68f2A0XJWwQ== X-Received: by 2002:a2e:9f05:: with SMTP id u5mr10159631ljk.192.1604508600194; Wed, 04 Nov 2020 08:50:00 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:59 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 25/47] ARM: tegra: Add DVFS properties to Tegra20 EMC device-tree node Date: Wed, 4 Nov 2020 19:49:01 +0300 Message-Id: <20201104164923.21238-26-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add EMC OPP DVFS table that will be used for dynamic scaling of memory frequency/voltage. Update board device-trees with optional EMC core supply and remove unsupported OPPs. Signed-off-by: Dmitry Osipenko --- .../boot/dts/tegra20-acer-a500-picasso.dts | 7 ++ arch/arm/boot/dts/tegra20-colibri.dtsi | 4 + arch/arm/boot/dts/tegra20-paz00.dts | 6 ++ .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 92 +++++++++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 3 + 5 files changed, 112 insertions(+) create mode 100644 arch/arm/boot/dts/tegra20-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index a0b829738e8f..b4ed88802387 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -1061,6 +1061,8 @@ map0 { memory-controller@7000f400 { nvidia,use-ram-code; + core-supply = <&vdd_core>; + emc-tables@0 { nvidia,ram-code = <0>; /* elpida-8gb */ @@ -1450,3 +1452,8 @@ emc-table@300000 { }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@666000000; + /delete-node/ opp@760000000; +}; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 6162d193e12c..585a5b441cf6 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -742,6 +742,10 @@ sound { }; }; +&emc_icc_dvfs_opp_table { + /delete-node/ opp@760000000; +}; + &gpio { lan-reset-n { gpio-hog; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index ada2bed8b1b5..52a81d888424 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -314,6 +314,8 @@ nvec@7000c500 { memory-controller@7000f400 { nvidia,use-ram-code; + core-supply = <&core_vdd_reg>; + emc-tables@0 { nvidia,ram-code = <0x0>; #address-cells = <1>; @@ -662,3 +664,7 @@ cpu@1 { }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@760000000; +}; diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi new file mode 100644 index 000000000000..25b1ba73951e --- /dev/null +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + compatible = "operating-points-v2"; + + opp@36000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <36000000>; + }; + + opp@47500000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <47500000>; + }; + + opp@50000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <50000000>; + }; + + opp@54000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <54000000>; + }; + + opp@57000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <57000000>; + }; + + opp@100000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <100000000>; + }; + + opp@108000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <108000000>; + }; + + opp@126666000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <126666000>; + }; + + opp@150000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <150000000>; + }; + + opp@190000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <190000000>; + }; + + opp@216000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <216000000>; + }; + + opp@300000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <300000000>; + }; + + opp@333000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <333000000>; + }; + + opp@380000000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <380000000>; + }; + + opp@600000000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <600000000>; + }; + + opp@666000000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <666000000>; + }; + + opp@760000000 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <760000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 8f8ad81916e7..6ce498178105 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -6,6 +6,8 @@ #include #include +#include "tegra20-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra20"; interrupt-parent = <&lic>; @@ -664,6 +666,7 @@ emc: memory-controller@7000f400 { #size-cells = <0>; #interconnect-cells = <0>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; nvidia,memory-controller = <&mc>; }; From patchwork Wed Nov 4 16:49:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DDF0C4741F for ; Wed, 4 Nov 2020 16:52:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F3912206FA for ; Wed, 4 Nov 2020 16:52:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WkXM3DJZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731506AbgKDQwa (ORCPT ); Wed, 4 Nov 2020 11:52:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731578AbgKDQuE (ORCPT ); Wed, 4 Nov 2020 11:50:04 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 674D7C0613D3; Wed, 4 Nov 2020 08:50:04 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id i6so28060906lfd.1; Wed, 04 Nov 2020 08:50:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+t0DsU6My3tVxrD7Qav6SIahBsjxD5Qw2s4eUzqdGNQ=; b=WkXM3DJZpbpSnCdi4yI8wQF6f9BrMWMhqsOZgL2zHvULDlDWlu4jLi2R2pfW7jW7BK Dqb0BaDoTGu1UV0LeLVNGJdi/kS1I1NihnUo6PamXE1/EGl/QPfimEaEza4DaWo9CNbz y8AUmxp35Tc3QAb4FgplFCSityng7LxVMErWcDD8rFWGARJsLRtwW0Hi9OleawLXJNXh +VedqCCEuZ8aN7MDCuZyBV2gOoqey0e7Q7uI2nFI2MrqJT+6f9DnXB8mMSXun8t1m/ZG aVj0JnzmUKcXEHYVfEHEZF1Fhc1gxOYWeMEOYN032mSbAL6kxKSYVBUYqb5O0Q8MlJO3 EVqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+t0DsU6My3tVxrD7Qav6SIahBsjxD5Qw2s4eUzqdGNQ=; b=YOLkVUog74nlMt7EzfC+NOnmXwyoyoGSM+HReKZh+ZiZjfhx0vJkd/E0TuFbR7qV0N RUDQQRJYDCEijl4QwHgzbqesYBw6ZX2+L+PGHn+rm1/jlsEUYcny9ECfNfUF8jPYkPGs 2PM6mvCKR80McKkDjkS6NG/01ed3iDAdUFcIVYR5H25K2Miwzn40MsebJyjavV+Kaw2p 1/6Cc8CMFWllevnTM0t40UGB7avL/bQb3DbprbEm8FJQnhxrgOsilbGHJEDXV5qf2kGk bO0SiTw5EtoTI+2XX8x0RpFndo7Po6j+ACuI2ypahyh3zAbe489k4pom2A/1raxIErOm rwMQ== X-Gm-Message-State: AOAM532csZ27XTQRF78MhR0+276S3UK2jpuhYfmD6rYMZE/pblYZ3bE0 j29rJZuLWcuxAJGggi17Q8Y= X-Google-Smtp-Source: ABdhPJxjRwPm3/FCNhHoiprA+/pMldPxGg+SakrPRMlSdIUNbY6uSU/rrqXSaCWic/NFBTtUkQ3GBg== X-Received: by 2002:ac2:4569:: with SMTP id k9mr10939869lfm.327.1604508602608; Wed, 04 Nov 2020 08:50:02 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:02 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 27/47] ARM: tegra: Add DVFS properties to Tegra124 EMC and ACTMON device-tree nodes Date: Wed, 4 Nov 2020 19:49:03 +0300 Message-Id: <20201104164923.21238-28-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for dynamic memory bandwidth scaling based on memory utilization statistics. Remove unsupported EMC OPPs from board device-trees. Note that ACTMON watches all memory interconnect paths, but we use a single CPU-READ interconnect path for driving memory bandwidth, for simplicity. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 8 + .../arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 8 + arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 10 + .../arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 10 + .../boot/dts/tegra124-peripherals-opp.dtsi | 419 ++++++++++++++++++ arch/arm/boot/dts/tegra124.dtsi | 6 + 6 files changed, 461 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index 32401457ae71..a7ac805eeed5 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -1465,3 +1465,11 @@ timing-924000000 { }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 861d3f22116b..df4e463afbd1 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -2420,3 +2420,11 @@ timing-924000000 { }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index c91647d13a50..a0f56cc9da5c 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -6649,3 +6649,13 @@ timing-792000000 { }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@924000000,1100; + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@924000000; + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index d2beea0bd15f..35c98734d35f 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -2048,3 +2048,13 @@ timing-792000000 { }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@924000000,1100; + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@924000000; + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi new file mode 100644 index 000000000000..49d9420a3289 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + compatible = "operating-points-v2"; + + opp@12750000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0003>; + }; + + opp@12750000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + }; + + opp@12750000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0010>; + }; + + opp@12750000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0004>; + }; + + opp@20400000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0003>; + }; + + opp@20400000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0008>; + }; + + opp@20400000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0010>; + }; + + opp@20400000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0004>; + }; + + opp@40800000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + }; + + opp@40800000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0008>; + }; + + opp@40800000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0010>; + }; + + opp@40800000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0004>; + }; + + opp@68000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + }; + + opp@68000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0008>; + }; + + opp@68000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0010>; + }; + + opp@68000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0004>; + }; + + opp@102000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + }; + + opp@102000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + }; + + opp@102000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0010>; + }; + + opp@102000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0004>; + }; + + opp@204000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0003>; + }; + + opp@204000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + }; + + opp@204000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0010>; + }; + + opp@204000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0004>; + }; + + opp@264000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0003>; + }; + + opp@264000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0008>; + }; + + opp@264000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0010>; + }; + + opp@264000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0004>; + }; + + opp@300000000,850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + }; + + opp@300000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + }; + + opp@300000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0010>; + }; + + opp@300000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + }; + + opp@348000000,850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0003>; + }; + + opp@348000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0008>; + }; + + opp@348000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0010>; + }; + + opp@348000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0004>; + }; + + opp@396000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0008>; + }; + + opp@396000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0003>; + }; + + opp@396000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0010>; + }; + + opp@396000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0004>; + }; + + opp@528000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0008>; + }; + + opp@528000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0003>; + }; + + opp@528000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0010>; + }; + + opp@528000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0004>; + }; + + opp@600000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0008>; + }; + + opp@600000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0003>; + }; + + opp@600000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0010>; + }; + + opp@600000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + + opp@792000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x000B>; + }; + + opp@792000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0010>; + }; + + opp@792000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0004>; + }; + + opp@924000000,1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + }; + + opp@1200000000,1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + }; + }; + + emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + compatible = "operating-points-v2"; + + opp@12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <204000>; + }; + + opp@20400000 { + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <326400>; + }; + + opp@40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <652800>; + }; + + opp@68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1088000>; + }; + + opp@102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1632000>; + }; + + opp@204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <3264000>; + }; + + opp@264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4224000>; + }; + + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4800000>; + }; + + opp@348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <5568000>; + }; + + opp@396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <6336000>; + }; + + opp@528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <8448000>; + }; + + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <9600000>; + }; + + opp@792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <12672000>; + }; + + opp@924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + opp-peak-kBps = <14784000>; + }; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <19200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 1801e30b1d3a..46441d10a3fc 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -8,6 +8,8 @@ #include #include +#include "tegra124-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra124"; interrupt-parent = <&lic>; @@ -290,6 +292,9 @@ actmon@6000c800 { clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; }; gpio: gpio@6000d000 { @@ -660,6 +665,7 @@ emc: external-memory-controller@7001b000 { clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; #interconnect-cells = <0>; }; From patchwork Wed Nov 4 16:49:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF485C2D0A3 for ; Wed, 4 Nov 2020 16:52:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6D76C2072C for ; Wed, 4 Nov 2020 16:52:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KpiAXbIN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731469AbgKDQwY (ORCPT ); Wed, 4 Nov 2020 11:52:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731595AbgKDQuH (ORCPT ); Wed, 4 Nov 2020 11:50:07 -0500 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E46AC0613D4; Wed, 4 Nov 2020 08:50:06 -0800 (PST) Received: by mail-lf1-x142.google.com with SMTP id 141so28036878lfn.5; Wed, 04 Nov 2020 08:50:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ontILFu87u1f4MUNSf7ISJYhooI1Fl6nxuqtZ8MK7KA=; b=KpiAXbIN9xyIT49De3HrEvU5DGh8CkAdeTEamjiprGA+wcYsFBjI7VaEwyQPpkJ0AH UcyWqBFvUp1Mi9/k+nOg0MXFukdp0qAlfHvpTMoL+qOyT+riM702VbkA7BwBl6WNydlA ycrTD1A/+45wJ0xinDRB8U3yXvEckk0H+vD4djxHznRHV9VNo22Xys6qNzKk6rlOuMeM OhFLTlyybkJ3hNdz/w91rbNUz36x0KXzyyGeCedtZjyesOeMyEV9J3A1CvMe2QDe0WHX XJAUu8XGCa41g/+o/TS+Dg+FFZJxCmQbHDhlJ01XTBCoZimI+uafm2pG7o4xw+eBaNdA Fazg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ontILFu87u1f4MUNSf7ISJYhooI1Fl6nxuqtZ8MK7KA=; b=qPDWGSyzL7NvLFJPAj7ZNyxwJ/XjFwmhwsnogbvup8saD8jjRrwTP77uZbAm99VngC YuF8PfMzNZ+OUvGZHHd7YgcPo4AflG8wanZHnE8J5ovj2wegWj/HxZZ1MzTkw49T8m/1 1ubaHRRzzENdOpym1G5aBLrYFMieBsOYW6bjYfmA3FM+/RfD47x77GbYRyeGVSVxMWnq px/P6FD6Qhy3sJTXQ9FOEE3tTZAjW5DZBzJxqxl0xrAj5KDXaYBnQmriyWvJQlugR4Up 84n04LI13diSP0snekK1qZmIykXXX6a5giA7eYIxNzJXktjlu6JniSB8av70esFOsZF3 hYvA== X-Gm-Message-State: AOAM531DpvXd0R7yWxVRcAI+coJKADhjaTlaDLQnSQ92vTOEYnKZSizT iRBnOpnUxxXMRvKnya3f3HE= X-Google-Smtp-Source: ABdhPJwFwRfM8+FLmXLSCezu8zR7YUZ+l+xLpkCbgrgY7ovwtYaZEuVGHW6YCQ0T4DaEpbT7+RwT4Q== X-Received: by 2002:a19:8605:: with SMTP id i5mr5409733lfd.356.1604508604974; Wed, 04 Nov 2020 08:50:04 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:04 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 29/47] memory: tegra: Use devm_platform_ioremap_resource() Date: Wed, 4 Nov 2020 19:49:05 +0300 Message-Id: <20201104164923.21238-30-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use devm_platform_ioremap_resource() helper which makes code a bit cleaner. Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra124-emc.c | 4 +--- drivers/memory/tegra/tegra20-emc.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index 35dbceb7f841..ee8ee39e98ed 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -1179,7 +1179,6 @@ static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; struct tegra_emc *emc; - struct resource *res; u32 ram_code; int err; @@ -1189,8 +1188,7 @@ static int tegra_emc_probe(struct platform_device *pdev) emc->dev = &pdev->dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - emc->regs = devm_ioremap_resource(&pdev->dev, res); + emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) return PTR_ERR(emc->regs); diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 027f46287dbf..5ba4e495bfc3 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -654,7 +654,6 @@ static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; struct tegra_emc *emc; - struct resource *res; int irq, err; /* driver has nothing to do in a case of memory timing absence */ @@ -689,8 +688,7 @@ static int tegra_emc_probe(struct platform_device *pdev) if (err) return err; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - emc->regs = devm_ioremap_resource(&pdev->dev, res); + emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) return PTR_ERR(emc->regs); From patchwork Wed Nov 4 16:49:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A07F0C63699 for ; Wed, 4 Nov 2020 16:52:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 443002074B for ; Wed, 4 Nov 2020 16:52:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hl9PYTeG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731624AbgKDQuL (ORCPT ); Wed, 4 Nov 2020 11:50:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731609AbgKDQuK (ORCPT ); Wed, 4 Nov 2020 11:50:10 -0500 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEC40C0613D3; Wed, 4 Nov 2020 08:50:08 -0800 (PST) Received: by mail-lj1-x243.google.com with SMTP id p15so23745561ljj.8; Wed, 04 Nov 2020 08:50:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TOGvVUHcibmPsiJFYWy41eUdIfTQfcWXxsgewF1xVKg=; b=hl9PYTeGaxu2o8M5LrEu6BtKQP8m6rA7XTM+RoY50/kPsRxa8J9MTXuP+rCTLD4pPI pcl/iTlEfddLxoJvSDTQMPheJb67tlB86IDV1YHFTv0Wm3/tj1K0nE/nVwYVhPdPaJYO NnCYXIPOOTIAbOp4kEH0pOeZMlF5DTw/3I3HK9+Lh2E52CEKYMxjgguS2YbdTN9m6wv1 NPtSS5cdQ9nHITAZMxMqyhbWonBhdZgkc7Bv4mSlbYvQ/7kJwrY7rUXzCOAfmrk6TzBU LghymARrfDpLRWy51/4HibOiUXHV5K2mzHPJyddJU7D/shVzQT3S+jUOgkFUtnIGEflH pR+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TOGvVUHcibmPsiJFYWy41eUdIfTQfcWXxsgewF1xVKg=; b=fCvKUaomN7IPSBzd5/2eDKo9407TC/12AJu+LVidHEtc9Bxyn4lZue2NG3MTt5l+fS zlOTOZQZ7FnvopR3l3didOrA8thMQsvt8up6tXZmUAUIb4uEozmIZ6g4HZn0m0YU6wpM GsRsmXGy7m0Jh6M2XeSoO2g8CvZ4WAk+z12uYsn03+1OUed2WOeWx252rtvgYEucTJEF 9Wu8KiyrIoOcObg2cXxuh/fiARIwjMuxJ1M0YWVYFrkolyfadbIBg5ScKzDGPc5cYOYR Q9Us09kNnDsouHZ4OrYpLdeQatmHqRx6dnUVDCPE+pToVUxWXV3Kxi02bXEDz3NMZFcV jU4g== X-Gm-Message-State: AOAM531kLYEChu722H2Z1yK8gq/jnUR6/lCPXN2qA61s2+kcd8iZGcLH gHf0pOfqlKiHJx6mW9wgzAc= X-Google-Smtp-Source: ABdhPJxze63P/PqGfFrXgCrXBjeFwj8H2RVN0iP7KJpDm/DqMJe1meNS4slHrFYeL5pTc5ZW0q+wPw== X-Received: by 2002:a2e:5d4:: with SMTP id 203mr577835ljf.137.1604508607389; Wed, 04 Nov 2020 08:50:07 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:06 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 31/47] memory: tegra: Add missing latency allowness entry for Page Table Cache Date: Wed, 4 Nov 2020 19:49:07 +0300 Message-Id: <20201104164923.21238-32-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing PTC memory client latency allowness entry to the Tegra MC drivers. This prevents erroneous clearing of MC_INTSTATUS 0x0 register during of the LA programming in tegra_mc_setup_latency_allowance() due to the missing entry. Note that this patch doesn't fix any known problems. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra114.c | 6 ++++++ drivers/memory/tegra/tegra124.c | 6 ++++++ drivers/memory/tegra/tegra30.c | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c index 48ef01c3ff90..ed376ba2d2fe 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -15,6 +15,12 @@ static const struct tegra_mc_client tegra114_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index 0cede24479bf..e2389573d3c0 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -15,6 +15,12 @@ static const struct tegra_mc_client tegra124_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index fcdd812eed80..b1990b4133d8 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -36,6 +36,12 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", From patchwork Wed Nov 4 16:49:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A853FC6369E for ; Wed, 4 Nov 2020 16:52:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 56D272072C for ; Wed, 4 Nov 2020 16:52:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="tnVjUemh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731631AbgKDQwM (ORCPT ); Wed, 4 Nov 2020 11:52:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731623AbgKDQuL (ORCPT ); Wed, 4 Nov 2020 11:50:11 -0500 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B9BAC061A4A; Wed, 4 Nov 2020 08:50:11 -0800 (PST) Received: by mail-lf1-x141.google.com with SMTP id l28so27979777lfp.10; Wed, 04 Nov 2020 08:50:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xT24YybZ9ESCUzYgdGCxIPBX3gyhxeGvxD42woUTjp4=; b=tnVjUemha3ft441R6cHZarZDnvpO3jI+yLR26WM4VdGva6bOHWI1NSLO+Zp3h/iOr3 uE9svPHNVMKaQoLP/0ekpVZ0tKKI9Hw0dSaImzIqUCcrRzDbn9VUmanH6I0TzpBBxstZ WtckXa9nAXWgwhVlOsECB5/M90E7JkP8MTobICLfHGcQd9aa3qOWJhYoJwIaZ+1u+SLg eaVbg9YBU3pgbUQQCdgaUpULNa1ujdp4tQX2uPEeM4ricWugMwxgfaIUJ4uy+LbNvGtx BdUFMFJ3NuP+QGTgxgGunCYHimKMyL3jlIG/pyqj/2hfVmhghKjLoj/eWumXn7E6O5Bx IWKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xT24YybZ9ESCUzYgdGCxIPBX3gyhxeGvxD42woUTjp4=; b=jBldAqmr/eV6Lqwd/WjtbxJPkgvuT0puub6DtYpbd7bS//dLducF7Y1hSAEEUBDze1 lEIwoJuB/NSRZbzGmAvo69YvHkOo1f0W7iOOtvdN0PK8ZmNl/BnbCITMcU5kdVAiMmxS wMFYrch148isyZ305ZUmzYGFEvq41eRJ3n2Y+mfNyivkfni+AKVo9NxkC2sqw0Zbf6LG 9gOZz90ajdTA8prv4ZbPTjaWdn2kXXMjTmPDWsXe9lxYwKkw4gCVobDjoXFrC1NaU0BU Z9t82SWz1saYS8F0dP/KASfnjq5QLkxdWQAL9TW1GrbVWqzixP8wOgoAQeXCxMI51ZzV 45TQ== X-Gm-Message-State: AOAM530mcG5mfhZIVBxR76J0jmNQoLzWHd1dirZHfIC0BxItZR9OD8fq qrf8mP23JWeJTCD/sR0yjBY= X-Google-Smtp-Source: ABdhPJzBVgcu5tqRSkCoQPWfnMYlkh8Bf1SUYRqiEau5NByTFy2W61uGqqDNsNINaJKset+Q4hRvdg== X-Received: by 2002:a19:3fd6:: with SMTP id m205mr9540980lfa.1.1604508609726; Wed, 04 Nov 2020 08:50:09 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:09 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 33/47] memory: tegra20-emc: Make driver modular Date: Wed, 4 Nov 2020 19:49:09 +0300 Message-Id: <20201104164923.21238-34-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add modularization support to the Tegra20 EMC driver, which now can be compiled as a loadable kernel module. Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/tegra20-emc.c | 17 ++++++++++++----- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index b38e5255effe..ff426747cd7d 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -9,7 +9,7 @@ config TEGRA_MC NVIDIA Tegra SoCs. config TEGRA20_EMC - bool "NVIDIA Tegra20 External Memory Controller driver" + tristate "NVIDIA Tegra20 External Memory Controller driver" default y depends on ARCH_TEGRA_2x_SOC help diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index c9fe58a724ee..88619e3ec435 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -721,6 +721,13 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; unset_cb: @@ -733,6 +740,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra20-emc", }, {}, }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct platform_driver tegra_emc_driver = { .probe = tegra_emc_probe, @@ -742,9 +750,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int __init tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Dmitry Osipenko "); +MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Nov 4 16:49:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19075C5517A for ; Wed, 4 Nov 2020 16:51:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A13A22072C for ; Wed, 4 Nov 2020 16:51:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="A87Wg4QK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731390AbgKDQv5 (ORCPT ); Wed, 4 Nov 2020 11:51:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731641AbgKDQuO (ORCPT ); Wed, 4 Nov 2020 11:50:14 -0500 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B53A9C0613D4; Wed, 4 Nov 2020 08:50:13 -0800 (PST) Received: by mail-lf1-x143.google.com with SMTP id h6so28023449lfj.3; Wed, 04 Nov 2020 08:50:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+PlVNz2DO82Pxa4NldbfLMdE8+v1PrLJFS/R38S8Isg=; b=A87Wg4QKQL3q3FFqkehTbQpaq4XT5eRAOqy33Xin6xKb8B8xzLme7pkgNfpl7ZlP/i giaZ0EpKejZOAVQx/SNrU8fFRUdIyoCVBG8dPYx/2tA94KZwZVpEDN8b2lg281Aot9qx 2A+J2KTD5vT9PkpJlOglQRAprHjGvaRTCqSa+Y8pJiWFPNfxSEouoH4hia9Zw/NE+PCA HVXVvTsqPPlP6s8dBBPhGQzD8S0tDhYfOSaUJCTyQbN90XVDbWA11WBpqKQ32oPX5lkv FMuOuhtdTLmMebPYeXCdVfzroiGg39ySDreUr06cg+eO5eFkoKaZ6f6feLdweJJzVJvS q39w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+PlVNz2DO82Pxa4NldbfLMdE8+v1PrLJFS/R38S8Isg=; b=YGrgyAsityfkJS6ses1Y97rPWysSO+9wIpKsxrytIH15c89c+YpJYcRBvwhBrugInU h0gPy9GHrkGvZmRueONn9mOnfoLdX4mjPhXIQENX46WUcgLESQPINRwt8bq6z7OstCQv 1cK9je8PMGJ5l0OsAbZb18yD18x+vfbBozdfZSVObleFqdEksZlnY4jw8kq7pijeXM/L C7JH3dKCZWf94GTwZ0j/FIaUxLDSLWpINTloIoHkQdaP+psf1iEj34MBPriRSAKJfcWy +FGyADqHSKrdTfTkLJMJqr1onAdQ4/KvxuqgZAPGg6cfSp2yqXX1aNkcGlp8dSAnJW/F FVKg== X-Gm-Message-State: AOAM531BpjtZWIy4l3ToHmsEgNcfC9siL0G9mbRQnN3kJeY9MKrg0ezu 2WIbPiLi8wYTdzpG+kk+HQ8= X-Google-Smtp-Source: ABdhPJyZcwK2knrE+1ZPczga3RIbbzmkeGQ19AMjHZaGvSJ65EWHyr+iyJ/B+1M40rO2bPZLHvExkA== X-Received: by 2002:a05:6512:1da:: with SMTP id f26mr10741885lfp.245.1604508612132; Wed, 04 Nov 2020 08:50:12 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:11 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 35/47] memory: tegra20: Support interconnect framework Date: Wed, 4 Nov 2020 19:49:11 +0300 Message-Id: <20201104164923.21238-36-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now Internal and External Memory Controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 3 +- drivers/memory/tegra/tegra20-emc.c | 310 ++++++++++++++++++++++++++++- drivers/memory/tegra/tegra20.c | 77 +++++++ 3 files changed, 386 insertions(+), 4 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index ff426747cd7d..ac3dfe155505 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -11,7 +11,8 @@ config TEGRA_MC config TEGRA20_EMC tristate "NVIDIA Tegra20 External Memory Controller driver" default y - depends on ARCH_TEGRA_2x_SOC + depends on TEGRA_MC && ARCH_TEGRA_2x_SOC + select PM_OPP help This driver is for the External Memory Controller (EMC) found on Tegra20 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index a49658d217a7..5e10aa97809f 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -9,18 +9,25 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include +#include +#include #include #include +#include #include +#include "mc.h" + #define EMC_INTSTATUS 0x000 #define EMC_INTMASK 0x004 #define EMC_DBG 0x008 @@ -62,6 +69,11 @@ #define EMC_ODT_READ 0x0b4 #define EMC_FBIO_CFG5 0x104 #define EMC_FBIO_CFG6 0x114 +#define EMC_STAT_CONTROL 0x160 +#define EMC_STAT_LLMC_CONTROL 0x178 +#define EMC_STAT_PWR_CLOCK_LIMIT 0x198 +#define EMC_STAT_PWR_CLOCKS 0x19c +#define EMC_STAT_PWR_COUNT 0x1a0 #define EMC_AUTO_CAL_INTERVAL 0x2a8 #define EMC_CFG_2 0x2b8 #define EMC_CFG_DIG_DLL 0x2bc @@ -88,6 +100,8 @@ #define EMC_DBG_READ_DQM_CTRL BIT(9) #define EMC_DBG_CFG_PRIORITY BIT(24) +#define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4) + static const u16 emc_timing_registers[] = { EMC_RC, EMC_RFC, @@ -142,11 +156,25 @@ struct emc_timing { u32 data[ARRAY_SIZE(emc_timing_registers)]; }; +enum emc_rate_request_type { + EMC_RATE_DEBUG, + EMC_RATE_ICC, + EMC_RATE_TYPE_MAX, +}; + +struct emc_rate_request { + unsigned long min_rate; + unsigned long max_rate; +}; + struct tegra_emc { struct device *dev; + struct tegra_mc *mc; + struct icc_provider provider; struct notifier_block clk_nb; struct clk *clk; void __iomem *regs; + unsigned int dram_bus_width; struct emc_timing *timings; unsigned int num_timings; @@ -156,6 +184,15 @@ struct tegra_emc { unsigned long min_rate; unsigned long max_rate; } debugfs; + + /* + * There are multiple sources in the EMC driver which could request + * a min/max clock rate, these rates are contained in this array. + */ + struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; + + /* protect shared rate-change code path */ + struct mutex rate_lock; }; static irqreturn_t tegra_emc_isr(int irq, void *data) @@ -413,7 +450,7 @@ tegra_emc_find_node_by_ram_code(struct device *dev) static int emc_setup_hw(struct tegra_emc *emc) { u32 intmask = EMC_REFRESH_OVERFLOW_INT; - u32 emc_cfg, emc_dbg; + u32 emc_cfg, emc_dbg, emc_fbio; emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); @@ -444,6 +481,15 @@ static int emc_setup_hw(struct tegra_emc *emc) emc_dbg &= ~EMC_DBG_FORCE_UPDATE; writel_relaxed(emc_dbg, emc->regs + EMC_DBG); + emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5); + + if (emc_fbio & EMC_FBIO_CFG5_DRAM_WIDTH_X16) + emc->dram_bus_width = 16; + else + emc->dram_bus_width = 32; + + dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); + return 0; } @@ -488,6 +534,83 @@ static long emc_round_rate(unsigned long rate, return timing->rate; } +static void tegra_emc_rate_requests_init(struct tegra_emc *emc) +{ + unsigned int i; + + for (i = 0; i < EMC_RATE_TYPE_MAX; i++) { + emc->requested_rate[i].min_rate = 0; + emc->requested_rate[i].max_rate = ULONG_MAX; + } +} + +static int emc_request_rate(struct tegra_emc *emc, + unsigned long new_min_rate, + unsigned long new_max_rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = emc->requested_rate; + unsigned long min_rate = 0, max_rate = ULONG_MAX; + unsigned int i; + int err; + + /* select minimum and maximum rates among the requested rates */ + for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) { + if (i == type) { + min_rate = max(new_min_rate, min_rate); + max_rate = min(new_max_rate, max_rate); + } else { + min_rate = max(req->min_rate, min_rate); + max_rate = min(req->max_rate, max_rate); + } + } + + if (min_rate > max_rate) { + dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", + __func__, type, min_rate, max_rate); + return -ERANGE; + } + + /* + * EMC rate-changes should go via OPP API because it manages voltage + * changes. + */ + err = dev_pm_opp_set_rate(emc->dev, min_rate); + if (err) + return err; + + emc->requested_rate[type].min_rate = new_min_rate; + emc->requested_rate[type].max_rate = new_max_rate; + + return 0; +} + +static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, rate, req->max_rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + +static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, req->min_rate, rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + /* * debugfs interface * @@ -571,7 +694,7 @@ static int tegra_emc_debug_min_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_min_rate(emc->clk, rate); + err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -601,7 +724,7 @@ static int tegra_emc_debug_max_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_max_rate(emc->clk, rate); + err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -658,6 +781,177 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node_data * +emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node_data *ndata; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id != TEGRA_ICC_EMEM) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + /* + * SRC and DST nodes should have matching TAG in order to have + * it set by default for a requested path. + */ + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + ndata->node = node; + + return ndata; + } + + return ERR_PTR(-EPROBE_DEFER); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); + unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); + unsigned long long rate = max(avg_bw, peak_bw); + unsigned int dram_data_bus_width_bytes; + int err; + + /* + * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data + * is sampled on both clock edges. This means that EMC clock rate + * equals to the peak data-rate. + */ + dram_data_bus_width_bytes = emc->dram_bus_width / 8; + do_div(rate, dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); + if (err) + return err; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + const struct tegra_mc_soc *soc; + struct icc_node *node; + int err; + + emc->mc = devm_tegra_memory_controller_get(emc->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); + + soc = emc->mc->soc; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.aggregate = soc->icc_ops->aggregate; + emc->provider.xlate_extended = emc_of_icc_xlate_extended; + + err = icc_provider_add(&emc->provider); + if (err) + goto err_msg; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto del_provider; + } + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); +del_provider: + icc_provider_del(&emc->provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + +static int tegra_emc_opp_table_init(struct tegra_emc *emc) +{ + struct opp_table *opp_table; + const char *rname = "core"; + int err; + + /* + * Legacy device-trees don't have OPP table and EMC driver isn't + * useful in this case. + */ + if (!device_property_present(emc->dev, "operating-points-v2")) { + dev_err(emc->dev, + "OPP table not found, please update your device tree\n"); + return -ENODEV; + } + + /* voltage scaling is optional */ + if (device_property_present(emc->dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(emc->dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(emc->dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + err = dev_pm_opp_of_add_table(emc->dev); + if (err) { + dev_err(emc->dev, "failed to add OPP table: %d\n", err); + goto put_table; + } + + dev_info(emc->dev, "current clock rate %lu MHz\n", + clk_get_rate(emc->clk) / 1000000); + + /* first dummy rate-set initializes voltage state */ + err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); + if (err) { + dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); + goto remove_table; + } + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(emc->dev); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -674,6 +968,7 @@ static int tegra_emc_probe(struct platform_device *pdev) if (!emc) return -ENOMEM; + mutex_init(&emc->rate_lock); emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; emc->dev = &pdev->dev; @@ -716,8 +1011,14 @@ static int tegra_emc_probe(struct platform_device *pdev) goto unset_cb; } + err = tegra_emc_opp_table_init(emc); + if (err) + goto unreg_notifier; + platform_set_drvdata(pdev, emc); + tegra_emc_rate_requests_init(emc); tegra_emc_debugfs_init(emc); + tegra_emc_interconnect_init(emc); /* * Don't allow the kernel module to be unloaded. Unloading adds some @@ -728,6 +1029,8 @@ static int tegra_emc_probe(struct platform_device *pdev) return 0; +unreg_notifier: + clk_notifier_unregister(emc->clk, &emc->clk_nb); unset_cb: tegra20_clk_set_emc_round_callback(NULL, NULL); @@ -746,6 +1049,7 @@ static struct platform_driver tegra_emc_driver = { .name = "tegra20-emc", .of_match_table = tegra_emc_of_match, .suppress_bind_attrs = true, + .sync_state = icc_sync_state, }, }; module_platform_driver(tegra_emc_driver); diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index a8098bff91d9..29ecf02805a0 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -3,6 +3,10 @@ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. */ +#include +#include +#include + #include #include "mc.h" @@ -280,6 +284,78 @@ static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = { .reset_status = tegra20_mc_reset_status, }; +static int tegra20_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + /* + * It should be possible to tune arbitration knobs here, but the + * default values are known to work well on all devices. Hence + * nothing to do here so far. + */ + return 0; +} + +static int tegra20_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + /* + * ISO clients need to reserve extra bandwidth up-front because + * there could be high bandwidth pressure during initial filling + * of the client's FIFO buffers. Secondly, we need to take into + * account impurities of the memory subsystem. + */ + if (tag & TEGRA_MC_ICC_TAG_ISO) + peak_bw = tegra_mc_scale_percents(peak_bw, 300); + + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static struct icc_node_data * +tegra20_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(data); + unsigned int i, idx = spec->args[0]; + struct icc_node_data *ndata; + struct icc_node *node; + + list_for_each_entry(node, &mc->provider.nodes, node_list) { + if (node->id != idx) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + ndata->node = node; + + /* these clients are isochronous by default */ + if (strstarts(node->name, "display") || + strstarts(node->name, "vi")) + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + else + ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT; + + return ndata; + } + + for (i = 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id == idx) + return ERR_PTR(-EPROBE_DEFER); + } + + dev_err(mc->dev, "invalid ICC client ID %u\n", idx); + + return ERR_PTR(-EINVAL); +} + +static const struct tegra_mc_icc_ops tegra20_mc_icc_ops = { + .xlate_extended = tegra20_mc_of_icc_xlate_extended, + .aggregate = tegra20_mc_icc_aggreate, + .set = tegra20_mc_icc_set, +}; + const struct tegra_mc_soc tegra20_mc_soc = { .clients = tegra20_mc_clients, .num_clients = ARRAY_SIZE(tegra20_mc_clients), @@ -290,4 +366,5 @@ const struct tegra_mc_soc tegra20_mc_soc = { .reset_ops = &tegra20_mc_reset_ops, .resets = tegra20_mc_resets, .num_resets = ARRAY_SIZE(tegra20_mc_resets), + .icc_ops = &tegra20_mc_icc_ops, }; From patchwork Wed Nov 4 16:49:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21501C4742C for ; Wed, 4 Nov 2020 16:51:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BD211206FA for ; Wed, 4 Nov 2020 16:51:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FdG4fKKN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731669AbgKDQuS (ORCPT ); Wed, 4 Nov 2020 11:50:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731657AbgKDQuQ (ORCPT ); Wed, 4 Nov 2020 11:50:16 -0500 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20FB3C0613D3; Wed, 4 Nov 2020 08:50:16 -0800 (PST) Received: by mail-lf1-x141.google.com with SMTP id 126so27999063lfi.8; Wed, 04 Nov 2020 08:50:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ygGFEixuoZ4watwj5KaB3ZZnbm2DyZvxWKijeTY8Pq8=; b=FdG4fKKNqML8eJhkAB7c4DI1NNF3XiowauUAPWRzSoq49ugMkpYTOiy6B0+H1OoCyB PTWfFnOqx2p6k1iYhHJmhru4hPzsED9AelCYoFxQJ1wzcuiqBVXxGQ+eArBojv2PTYuk 7n1M07z3pmlhSXctZAS56bePOS7JOfLDzjtVvl9F1NQh5p6GR2qojdKvWIB+zautJs4n Qu8yanlMhfIegSIwD6EbwixGypphjP/2AYSEKEMkPr9R71RrrQoDJMA/zliEfszUo2eM EOySSq/LRAw5WhcbojYmwKIiIkVloKOKMrABrwTeP/2OWLl87RALattpPXfiGtvloL3S hWew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ygGFEixuoZ4watwj5KaB3ZZnbm2DyZvxWKijeTY8Pq8=; b=iwMfGBzTc91qzuiGoU9bOozFWABUYDQWwjpJqeY4a9OTUMq5CaQ4DYaAGX7nZLxHqV SAvHuz5fBGhoLRM1xA+xdmISbfW1NRG5DIdJFFFn9YfTu6XawgE0D4EY04p6EIMTTsW4 oys3Mdrg14mtB9ZdL/A4QudKgQbWTueMfY5LrfTU1ect2aWhfudHGRVcLdl9gL1vsPPf GvdxRgmVvG2PmwARWimIr5voT6bbcEivh7KuYViBkHhkg1nePBMqnrFB2h6i0wUyLx0e 5HT4oBlnjKslbfoFwxsLHNRA/SZGCbjlY5xcRgQA2Z0n9Y0QFmo/MJFpMfziAkmpzAKO j4jQ== X-Gm-Message-State: AOAM530PjGtLWRpRVBEpS2sYlMJd8WjHtlAtyv9x2EA/OfxClD8ZtPoe 2ZJH+tfJdEi5fyRtciiUKVc= X-Google-Smtp-Source: ABdhPJxHR622/VhfuA+lQrrhbDmFYYe2tnjkL8o/GJNrVPWzaVMgNQ9/ye30jidxAXieLAa/ftQpaw== X-Received: by 2002:a19:8c52:: with SMTP id i18mr9920164lfj.115.1604508614539; Wed, 04 Nov 2020 08:50:14 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:14 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 37/47] memory: tegra30: Add FIFO sizes to memory clients Date: Wed, 4 Nov 2020 19:49:13 +0300 Message-Id: <20201104164923.21238-38-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The latency allowness is calculated based on buffering capabilities of memory clients. Add FIFO sizes to the Tegra30 memory clients. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra30.c | 66 ++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index b1990b4133d8..d0314f29608d 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -42,6 +42,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0, }, + .fifo_size = 16 * 2, }, { .id = 0x01, .name = "display0a", @@ -56,6 +57,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x02, .name = "display0ab", @@ -70,6 +72,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x03, .name = "display0b", @@ -84,6 +87,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x04, .name = "display0bb", @@ -98,6 +102,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x05, .name = "display0c", @@ -112,6 +117,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x06, .name = "display0cb", @@ -126,6 +132,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x07, .name = "display1b", @@ -140,6 +147,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x08, .name = "display1bb", @@ -154,6 +162,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x09, .name = "eppup", @@ -168,6 +177,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x17, }, + .fifo_size = 16 * 8, }, { .id = 0x0a, .name = "g2pr", @@ -182,6 +192,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x09, }, + .fifo_size = 16 * 64, }, { .id = 0x0b, .name = "g2sr", @@ -196,6 +207,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x09, }, + .fifo_size = 16 * 64, }, { .id = 0x0c, .name = "mpeunifbr", @@ -210,6 +222,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x50, }, + .fifo_size = 16 * 8, }, { .id = 0x0d, .name = "viruv", @@ -224,6 +237,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x2c, }, + .fifo_size = 16 * 8, }, { .id = 0x0e, .name = "afir", @@ -238,6 +252,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 32, }, { .id = 0x0f, .name = "avpcarm7r", @@ -252,6 +267,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x04, }, + .fifo_size = 16 * 2, }, { .id = 0x10, .name = "displayhc", @@ -266,6 +282,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 2, }, { .id = 0x11, .name = "displayhcb", @@ -280,6 +297,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 2, }, { .id = 0x12, .name = "fdcdrd", @@ -294,6 +312,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x13, .name = "fdcdrd2", @@ -308,6 +327,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x14, .name = "g2dr", @@ -322,6 +342,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x15, .name = "hdar", @@ -336,6 +357,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 16, }, { .id = 0x16, .name = "host1xdmar", @@ -350,6 +372,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x05, }, + .fifo_size = 16 * 16, }, { .id = 0x17, .name = "host1xr", @@ -364,6 +387,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x50, }, + .fifo_size = 16 * 8, }, { .id = 0x18, .name = "idxsrd", @@ -378,6 +402,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x19, .name = "idxsrd2", @@ -392,6 +417,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x1a, .name = "mpe_ipred", @@ -406,6 +432,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x80, }, + .fifo_size = 16 * 2, }, { .id = 0x1b, .name = "mpeamemrd", @@ -420,6 +447,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x42, }, + .fifo_size = 16 * 64, }, { .id = 0x1c, .name = "mpecsrd", @@ -434,6 +462,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 8, }, { .id = 0x1d, .name = "ppcsahbdmar", @@ -448,6 +477,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 2, }, { .id = 0x1e, .name = "ppcsahbslvr", @@ -462,6 +492,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x12, }, + .fifo_size = 16 * 8, }, { .id = 0x1f, .name = "satar", @@ -476,6 +507,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x33, }, + .fifo_size = 16 * 32, }, { .id = 0x20, .name = "texsrd", @@ -490,6 +522,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x21, .name = "texsrd2", @@ -504,6 +537,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x22, .name = "vdebsevr", @@ -518,6 +552,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 8, }, { .id = 0x23, .name = "vdember", @@ -532,6 +567,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xd0, }, + .fifo_size = 16 * 4, }, { .id = 0x24, .name = "vdemcer", @@ -546,6 +582,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x2a, }, + .fifo_size = 16 * 16, }, { .id = 0x25, .name = "vdetper", @@ -560,6 +597,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x74, }, + .fifo_size = 16 * 16, }, { .id = 0x26, .name = "mpcorelpr", @@ -570,6 +608,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x04, }, + .fifo_size = 16 * 14, }, { .id = 0x27, .name = "mpcorer", @@ -580,6 +619,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x04, }, + .fifo_size = 16 * 14, }, { .id = 0x28, .name = "eppu", @@ -594,6 +634,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x6c, }, + .fifo_size = 16 * 64, }, { .id = 0x29, .name = "eppv", @@ -608,6 +649,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x6c, }, + .fifo_size = 16 * 64, }, { .id = 0x2a, .name = "eppy", @@ -622,6 +664,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x6c, }, + .fifo_size = 16 * 64, }, { .id = 0x2b, .name = "mpeunifbw", @@ -636,6 +679,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 8, }, { .id = 0x2c, .name = "viwsb", @@ -650,6 +694,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x12, }, + .fifo_size = 16 * 64, }, { .id = 0x2d, .name = "viwu", @@ -664,6 +709,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xb2, }, + .fifo_size = 16 * 64, }, { .id = 0x2e, .name = "viwv", @@ -678,6 +724,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xb2, }, + .fifo_size = 16 * 64, }, { .id = 0x2f, .name = "viwy", @@ -692,6 +739,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x12, }, + .fifo_size = 16 * 64, }, { .id = 0x30, .name = "g2dw", @@ -706,6 +754,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x9, }, + .fifo_size = 16 * 128, }, { .id = 0x31, .name = "afiw", @@ -720,6 +769,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0c, }, + .fifo_size = 16 * 32, }, { .id = 0x32, .name = "avpcarm7w", @@ -734,6 +784,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0e, }, + .fifo_size = 16 * 2, }, { .id = 0x33, .name = "fdcdwr", @@ -748,6 +799,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x34, .name = "fdcdwr2", @@ -762,6 +814,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x35, .name = "hdaw", @@ -776,6 +829,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 16, }, { .id = 0x36, .name = "host1xw", @@ -790,6 +844,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 32, }, { .id = 0x37, .name = "ispw", @@ -804,6 +859,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 64, }, { .id = 0x38, .name = "mpcorelpw", @@ -814,6 +870,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0e, }, + .fifo_size = 16 * 24, }, { .id = 0x39, .name = "mpcorew", @@ -824,6 +881,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0e, }, + .fifo_size = 16 * 24, }, { .id = 0x3a, .name = "mpecswr", @@ -838,6 +896,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 8, }, { .id = 0x3b, .name = "ppcsahbdmaw", @@ -852,6 +911,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 2, }, { .id = 0x3c, .name = "ppcsahbslvw", @@ -866,6 +926,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x06, }, + .fifo_size = 16 * 4, }, { .id = 0x3d, .name = "sataw", @@ -880,6 +941,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x33, }, + .fifo_size = 16 * 32, }, { .id = 0x3e, .name = "vdebsevw", @@ -894,6 +956,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 4, }, { .id = 0x3f, .name = "vdedbgw", @@ -908,6 +971,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 16, }, { .id = 0x40, .name = "vdembew", @@ -922,6 +986,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x42, }, + .fifo_size = 16 * 2, }, { .id = 0x41, .name = "vdetpmw", @@ -936,6 +1001,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x2a, }, + .fifo_size = 16 * 16, }, }; From patchwork Wed Nov 4 16:49:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0622C56201 for ; Wed, 4 Nov 2020 16:51:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6911C2151B for ; Wed, 4 Nov 2020 16:51:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eblmypJF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731675AbgKDQuS (ORCPT ); Wed, 4 Nov 2020 11:50:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731664AbgKDQuR (ORCPT ); Wed, 4 Nov 2020 11:50:17 -0500 Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 372CDC0613D3; Wed, 4 Nov 2020 08:50:17 -0800 (PST) Received: by mail-lj1-x244.google.com with SMTP id p15so23746046ljj.8; Wed, 04 Nov 2020 08:50:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rgi+XhUR0z96Rn3qewMTA7hO6Avu0FjffhBJqRZONd8=; b=eblmypJFyQJ2ZmnAQXDVYzIfTcgWZpSEDPPBDJhpHcajzNuoN1OljoGc3Tf9n9FzZT nX5bGr4ROZoQRFV2uHzErMGUL9vEFUCQ1eY5uzuNWQcVC5eLEEeyUj/wDk2NjRIe0pEP zv3/yl7cCmleK4tLV7vPZUBhxfDS6ytosavKOKf5zZ8j/Zw6dZf9NFzKM4wN3kkkL88g 4N7I/PPNLQSC78Y4Z/KP4sYByZFnB5WfzQXwJbe98IPK7194JPdylHdU6Intjdkb+6od U2o/YCxA/ZR4HANV4O0ZvUzb2PxV+B+CF4Qo50AURAiezeT9y2m0vRgTi4wgkRVgLSeI q2wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Rgi+XhUR0z96Rn3qewMTA7hO6Avu0FjffhBJqRZONd8=; b=AZNUjFpATG5SJkqMISZOwvtZBZaViwZOfTuJPPIwwDSkqflT3hnjDpwL1EnXBU0ww0 WC2sEhpGTdTHr2u6MxOdYX4dH1pIa4TcdFu+FKiYzJhC+wjHtlSG2Kc+Jt4U/K5f+ssY pJ17ffkncPc1YPYuLBySuIghmelBkEM9wcvrPbW1/VsuGnfmvNjvh23wnYkNl3eCQ03L haf7JuL/6KBZ/cb5no3VYflnBB+fOhV7v6/M6HuYXdvkA/ZOITUsIiFRVkuD666O5+Ep s5Z6w1rELPb7CII4eK69kPl46Jw8Yd+Vb1qYgEqsjsypA6v3X/nHd9o4/nDPf/8p+iZn YFFQ== X-Gm-Message-State: AOAM531i1rbmOqgzYFcCe5zd01W/5jYXrXJPO+CA4cCH3/+3rRICGqbG Lt37ts/J/hAJPoYHagqJ7sk= X-Google-Smtp-Source: ABdhPJyFMsotfbn43p3mdj6tXK15eT+RmyhuGbAD+Ubsb+LV71BrigRuYtuvHdFFxKDITvUOzOf/7A== X-Received: by 2002:a2e:320a:: with SMTP id y10mr8068831ljy.393.1604508615721; Wed, 04 Nov 2020 08:50:15 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:15 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 38/47] memory: tegra30-emc: Make driver modular Date: Wed, 4 Nov 2020 19:49:14 +0300 Message-Id: <20201104164923.21238-39-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add modularization support to the Tegra30 EMC driver, which now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/mc.c | 3 +++ drivers/memory/tegra/tegra30-emc.c | 17 ++++++++++++----- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 76e9a3b10839..6779a2201fe4 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -22,7 +22,7 @@ config TEGRA20_EMC external memory. config TEGRA30_EMC - bool "NVIDIA Tegra30 External Memory Controller driver" + tristate "NVIDIA Tegra30 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_3x_SOC help diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index a7e6a8e4c95a..44064de962c2 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -346,6 +347,7 @@ int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) return 0; } +EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration); unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) { @@ -357,6 +359,7 @@ unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) return dram_count; } +EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); static int load_one_timing(struct tegra_mc *mc, struct tegra_mc_timing *timing, diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 1be28e28ec34..d0926088360a 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1330,6 +1330,13 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; unset_cb: @@ -1380,6 +1387,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra30-emc", }, {}, }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct platform_driver tegra_emc_driver = { .probe = tegra_emc_probe, @@ -1390,9 +1398,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int __init tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Dmitry Osipenko "); +MODULE_DESCRIPTION("NVIDIA Tegra30 EMC driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Nov 4 16:49:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DD49C55179 for ; Wed, 4 Nov 2020 16:51:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 44E62206ED for ; Wed, 4 Nov 2020 16:51:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="taDTiV3S" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731706AbgKDQuW (ORCPT ); Wed, 4 Nov 2020 11:50:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731699AbgKDQuV (ORCPT ); Wed, 4 Nov 2020 11:50:21 -0500 Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01870C0613D3; Wed, 4 Nov 2020 08:50:21 -0800 (PST) Received: by mail-lj1-x244.google.com with SMTP id k25so23707467lji.9; Wed, 04 Nov 2020 08:50:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IBDSVLceH42ghd/sR4M7H2Ikede4GW7JPwdSJ9jMlOg=; b=taDTiV3SzCKMk/PixwEOGzaOsAdFjiPDf3mL1DNc+FCM++cad54XkR+z8qDcOKAsXT +PcLekF7f8RfMrCvOR/X1QhC9IGuRm3JEYtu+jXTmn+wg2BGdBRzsOD3ccwkMqvdNYfm BOkt+P63uY1zcrD86thGxUxwCCI8EzYEbazvUeoTN9CKpe2pisa4QPBRdxuJcWVuA6iy nPvEHfwq5mjfLXiTKbrkeBFij+0rv7NOtIRnUiS6LLJxAvggY4GEpHfhtRbzcF+x7r3x HLjzIEqIUPF/FzagNpkBAXuiMVVl0Ok2uf+w5L0X1pT4Yvm/4BUMywU9TrracrssrI8r eoIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IBDSVLceH42ghd/sR4M7H2Ikede4GW7JPwdSJ9jMlOg=; b=GYYVZ7sANbhGWD4+cFV2oql6NZuSRDxxC0e1WwSlUur1iQXbDakNotZbsGbbMAuNZg qO+zCW2UJXMFFPqis+YzR8ixr1bp0TpeikHkzFXrVyV6S75oBPlazdYeixGvLC3qqmN8 hP3bvzdjwTT/wP0ppXRbvjIZUO/44RLNXcnk9khTg+2qbHUmnLBzkG2v9WXZQ9IIvgB6 lS2go388B4DvCkEQjkFWG8LVUohscTfZQSvY5vYnPiWumyBKngYKrPi61XmxeivoWc+s C02xEtRjeSCJFRzOyTVh9VGvT0gNnKrUudSXl4HfgQhnVZZLNNC1Ghkgl3X7bVBsPxBX jDhA== X-Gm-Message-State: AOAM5311F9dUwy+1TbXV8zlL6eG6JaWSCettpqa5xs8+rU5qcBmsZI6X LzqSwl3e5JvjpvpkFEimm1M= X-Google-Smtp-Source: ABdhPJw4ilpmq2RSdroewmGcVScETUJMoICYBZJ2u8Wm7iRGIB9o4JBpngkMRemfIBLHkQwEBOb6eA== X-Received: by 2002:a2e:584e:: with SMTP id x14mr10190824ljd.335.1604508619419; Wed, 04 Nov 2020 08:50:19 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:18 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 41/47] memory: tegra124-emc: Make driver modular Date: Wed, 4 Nov 2020 19:49:17 +0300 Message-Id: <20201104164923.21238-42-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add modularization support to the Tegra124 EMC driver, which now can be compiled as a loadable kernel module. Note that EMC clock must be registered at clk-init time, otherwise PLLM will be disabled as unused clock at boot time if EMC driver is compiled as a module. Hence add a prepare/complete callbacks. similarly to what is done for the Tegra20/30 EMC drivers. Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/Makefile | 3 +- drivers/clk/tegra/clk-tegra124-emc.c | 41 ++++++++++++++++++++++++---- drivers/clk/tegra/clk-tegra124.c | 27 ++++++++++++++++-- drivers/clk/tegra/clk.h | 16 +++-------- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/tegra124-emc.c | 31 ++++++++++++++------- include/linux/clk/tegra.h | 8 ++++++ include/soc/tegra/emc.h | 16 ----------- 8 files changed, 96 insertions(+), 48 deletions(-) delete mode 100644 include/soc/tegra/emc.h diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index eec2313fd37e..53b76133e905 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -22,7 +22,8 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra20-emc.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o obj-$(CONFIG_TEGRA_CLK_DFLL) += clk-tegra124-dfll-fcpu.o -obj-$(CONFIG_TEGRA124_EMC) += clk-tegra124-emc.o +obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-emc.o +obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124-emc.o obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o obj-y += cvb.o obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o diff --git a/drivers/clk/tegra/clk-tegra124-emc.c b/drivers/clk/tegra/clk-tegra124-emc.c index 745f9faa98d8..bdf6f4a51617 100644 --- a/drivers/clk/tegra/clk-tegra124-emc.c +++ b/drivers/clk/tegra/clk-tegra124-emc.c @@ -11,7 +11,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -21,7 +23,6 @@ #include #include -#include #include "clk.h" @@ -80,6 +81,9 @@ struct tegra_clk_emc { int num_timings; struct emc_timing *timings; spinlock_t *lock; + + tegra124_emc_prepare_timing_change_cb *prepare_timing_change; + tegra124_emc_complete_timing_change_cb *complete_timing_change; }; /* Common clock framework callback implementations */ @@ -176,6 +180,9 @@ static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra) if (tegra->emc) return tegra->emc; + if (!tegra->prepare_timing_change || !tegra->complete_timing_change) + return NULL; + if (!tegra->emc_node) return NULL; @@ -241,7 +248,7 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, div = timing->parent_rate / (timing->rate / 2) - 2; - err = tegra_emc_prepare_timing_change(emc, timing->rate); + err = tegra->prepare_timing_change(emc, timing->rate); if (err) return err; @@ -259,7 +266,7 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, spin_unlock_irqrestore(tegra->lock, flags); - tegra_emc_complete_timing_change(emc, timing->rate); + tegra->complete_timing_change(emc, timing->rate); clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent)); clk_disable_unprepare(tegra->prev_parent); @@ -473,8 +480,8 @@ static const struct clk_ops tegra_clk_emc_ops = { .get_parent = emc_get_parent, }; -struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, - spinlock_t *lock) +struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np, + spinlock_t *lock) { struct tegra_clk_emc *tegra; struct clk_init_data init; @@ -538,3 +545,27 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, return clk; }; + +void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb) +{ + struct clk *clk = __clk_lookup("emc"); + struct tegra_clk_emc *tegra; + struct clk_hw *hw; + + if (clk) { + hw = __clk_get_hw(clk); + tegra = container_of(hw, struct tegra_clk_emc, hw); + + tegra->prepare_timing_change = prep_cb; + tegra->complete_timing_change = complete_cb; + } +} +EXPORT_SYMBOL_GPL(tegra124_clk_set_emc_callbacks); + +bool tegra124_clk_emc_driver_available(struct clk_hw *hw) +{ + struct tegra_clk_emc *tegra = container_of(hw, struct tegra_clk_emc, hw); + + return tegra->prepare_timing_change && tegra->complete_timing_change; +} diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index e931319dcc9d..b4f2ae4066a6 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -929,6 +929,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true }, [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true }, [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true }, + [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = false }, }; static struct tegra_devclk devclks[] __initdata = { @@ -1500,6 +1501,26 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np) writel(plld_base, clk_base + PLLD_BASE); } +static struct clk *tegra124_clk_src_onecell_get(struct of_phandle_args *clkspec, + void *data) +{ + struct clk_hw *hw; + struct clk *clk; + + clk = of_clk_src_onecell_get(clkspec, data); + if (IS_ERR(clk)) + return clk; + + hw = __clk_get_hw(clk); + + if (clkspec->args[0] == TEGRA124_CLK_EMC) { + if (!tegra124_clk_emc_driver_available(hw)) + return ERR_PTR(-EPROBE_DEFER); + } + + return clk; +} + /** * tegra124_132_clock_init_post - clock initialization postamble for T124/T132 * @np: struct device_node * of the DT node for the SoC CAR IP block @@ -1516,10 +1537,10 @@ static void __init tegra124_132_clock_init_post(struct device_node *np) &pll_x_params); tegra_init_special_resets(1, tegra124_reset_assert, tegra124_reset_deassert); - tegra_add_of_provider(np, of_clk_src_onecell_get); + tegra_add_of_provider(np, tegra124_clk_src_onecell_get); - clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, - &emc_lock); + clks[TEGRA124_CLK_EMC] = tegra124_clk_register_emc(clk_base, np, + &emc_lock); tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 6b565f6b5f66..2da7c93c1a6c 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -881,18 +881,6 @@ void tegra_super_clk_gen5_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params); -#ifdef CONFIG_TEGRA124_EMC -struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, - spinlock_t *lock); -#else -static inline struct clk *tegra_clk_register_emc(void __iomem *base, - struct device_node *np, - spinlock_t *lock) -{ - return NULL; -} -#endif - void tegra114_clock_tune_cpu_trimmers_high(void); void tegra114_clock_tune_cpu_trimmers_low(void); void tegra114_clock_tune_cpu_trimmers_init(void); @@ -922,6 +910,10 @@ void tegra_clk_periph_resume(void); bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw); struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter); +struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np, + spinlock_t *lock); +bool tegra124_clk_emc_driver_available(struct clk_hw *emc_hw); + struct clk *tegra210_clk_register_emc(struct device_node *np, void __iomem *regs); diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index e7c295d50734..b5824c6cf664 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -33,7 +33,7 @@ config TEGRA30_EMC external memory. config TEGRA124_EMC - bool "NVIDIA Tegra124 External Memory Controller driver" + tristate "NVIDIA Tegra124 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_124_SOC help diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index ee8ee39e98ed..edfbf6d6d357 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -9,16 +9,17 @@ #include #include #include +#include #include #include #include +#include #include #include #include #include #include -#include #include #include @@ -562,8 +563,8 @@ static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, return timing; } -int tegra_emc_prepare_timing_change(struct tegra_emc *emc, - unsigned long rate) +static int tegra_emc_prepare_timing_change(struct tegra_emc *emc, + unsigned long rate) { struct emc_timing *timing = tegra_emc_find_timing(emc, rate); struct emc_timing *last = &emc->last_timing; @@ -790,8 +791,8 @@ int tegra_emc_prepare_timing_change(struct tegra_emc *emc, return 0; } -void tegra_emc_complete_timing_change(struct tegra_emc *emc, - unsigned long rate) +static void tegra_emc_complete_timing_change(struct tegra_emc *emc, + unsigned long rate) { struct emc_timing *timing = tegra_emc_find_timing(emc, rate); struct emc_timing *last = &emc->last_timing; @@ -987,6 +988,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra132-emc" }, {} }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct device_node * tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code) @@ -1226,9 +1228,19 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); + tegra124_clk_set_emc_callbacks(tegra_emc_prepare_timing_change, + tegra_emc_complete_timing_change); + if (IS_ENABLED(CONFIG_DEBUG_FS)) emc_debugfs_init(&pdev->dev, emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; }; @@ -1240,9 +1252,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Mikko Perttunen "); +MODULE_DESCRIPTION("NVIDIA Tegra124 EMC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index 3f01d43f0598..eb016fc9cc0b 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -136,6 +136,7 @@ extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value); extern void tegra210_clk_emc_update_setting(u32 emc_src_value); struct clk; +struct tegra_emc; typedef long (tegra20_clk_emc_round_cb)(unsigned long rate, unsigned long min_rate, @@ -146,6 +147,13 @@ void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, void *cb_arg); int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same); +typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb); + struct tegra210_clk_emc_config { unsigned long rate; bool same_freq; diff --git a/include/soc/tegra/emc.h b/include/soc/tegra/emc.h deleted file mode 100644 index 05199a97ccf4..000000000000 --- a/include/soc/tegra/emc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 NVIDIA Corporation. All rights reserved. - */ - -#ifndef __SOC_TEGRA_EMC_H__ -#define __SOC_TEGRA_EMC_H__ - -struct tegra_emc; - -int tegra_emc_prepare_timing_change(struct tegra_emc *emc, - unsigned long rate); -void tegra_emc_complete_timing_change(struct tegra_emc *emc, - unsigned long rate); - -#endif /* __SOC_TEGRA_EMC_H__ */ From patchwork Wed Nov 4 16:49:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D813C5517A for ; Wed, 4 Nov 2020 16:51:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E9027206E3 for ; Wed, 4 Nov 2020 16:51:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mBIZ+z3A" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731682AbgKDQvU (ORCPT ); Wed, 4 Nov 2020 11:51:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731672AbgKDQuZ (ORCPT ); Wed, 4 Nov 2020 11:50:25 -0500 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19333C061A4A; Wed, 4 Nov 2020 08:50:25 -0800 (PST) Received: by mail-lj1-x243.google.com with SMTP id v19so18770590lji.5; Wed, 04 Nov 2020 08:50:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FzRtX226Ns3ZKp6+Uq+Yk4+eY0Se/Xl5BO5wShlYK5k=; b=mBIZ+z3AGHgKtZ8J0vw9IDOhiu7RO9dSUfhU5Ry+UE6oJPHtmQ0YVWeqHZD76IqkL7 ypyi3Zq0fJlKo3yjvQDvFGVgwFk+U627MS9pRZpqSUtXaPAkWhKEAnoQRCCpyR1ajPvC W/IGXmP83sYT4lDitUYngD5jggJixP57F59tqHcaQp2LLfN/+vDl6Mvs2TSUpzi0yEff EeuGljdKmdVbfri/BpyvPaXD8EnvdxbRttck52x+lEAwyUNHyx4KtbI/iU41+NAMBn3V 6/lkliV/1dhMjSBBrUGNnsLkSlRWTq8g3kGc3gwpfFpdicOlDL65vIbwR968x6tg5xRD CKLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FzRtX226Ns3ZKp6+Uq+Yk4+eY0Se/Xl5BO5wShlYK5k=; b=jKZMGdQWYEukoiuYSniGEWg060ogI04OKyCr45UV15MvC0K3tO9BkDmbZDOJ1CKHO6 /ulrKi6UVUWye2x5GcP0mzkpUsrZxKbIM0UNNG3qiUwgMscb3lGSDL86CFAl5QTRpwEe zksi5Knb1PKvtnwdjtF0715w15jiat5JTMs/i9BF5ZkCK4uzwFtasBg37G0CVWUFieun ol2SEkWkxm7rER9aM6rBdUc8XkIV3WxWjLknhwo85mZuPBQieImWX8imgqKAjp1zyXQg E9xNt9/o7BTx/LvXn0YY4oEmL1RzlAlAgida6Nmy4vlA7HyZYIO12JqNroc2K0LSkPJG cNnw== X-Gm-Message-State: AOAM5324vzJNY2gWB81kr2UIxyRB0Vdf5nAyMzf0my1HXX5ODopoinUo w7W/8NTRJYo3DJYh1kbjtLs= X-Google-Smtp-Source: ABdhPJyOC59Ix41fXQXTZLbW5qdZVtfibNUJwBFUtazB1+xbtSOxZJ+Kkaq92Z0z1qs3gUWWqjYq5A== X-Received: by 2002:a2e:b4ba:: with SMTP id q26mr11711603ljm.121.1604508623388; Wed, 04 Nov 2020 08:50:23 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:22 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 44/47] drm/tegra: dc: Extend debug stats with total number of events Date: Wed, 4 Nov 2020 19:49:20 +0300 Message-Id: <20201104164923.21238-45-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It's useful to know the total number of underflow events and currently the debug stats are getting reset each time CRTC is being disabled. Let's account the overall number of events that doesn't get a reset. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/dc.c | 10 ++++++++++ drivers/gpu/drm/tegra/dc.h | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 14168f792977..fd7c8828652d 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1539,6 +1539,11 @@ static int tegra_dc_show_stats(struct seq_file *s, void *data) seq_printf(s, "underflow: %lu\n", dc->stats.underflow); seq_printf(s, "overflow: %lu\n", dc->stats.overflow); + seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); + seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); + seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); + seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); + return 0; } @@ -2308,6 +2313,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) /* dev_dbg(dc->dev, "%s(): frame end\n", __func__); */ + dc->stats.frames_total++; dc->stats.frames++; } @@ -2316,6 +2322,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); */ drm_crtc_handle_vblank(&dc->base); + dc->stats.vblank_total++; dc->stats.vblank++; } @@ -2323,6 +2330,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) /* dev_dbg(dc->dev, "%s(): underflow\n", __func__); */ + dc->stats.underflow_total++; dc->stats.underflow++; } @@ -2330,11 +2338,13 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) /* dev_dbg(dc->dev, "%s(): overflow\n", __func__); */ + dc->stats.overflow_total++; dc->stats.overflow++; } if (status & HEAD_UF_INT) { dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); + dc->stats.underflow_total++; dc->stats.underflow++; } diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 0d7bdf66a1ec..ba4ed35139fb 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -48,6 +48,11 @@ struct tegra_dc_stats { unsigned long vblank; unsigned long underflow; unsigned long overflow; + + unsigned long frames_total; + unsigned long vblank_total; + unsigned long underflow_total; + unsigned long overflow_total; }; struct tegra_windowgroup_soc { From patchwork Wed Nov 4 16:49:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAFABC2D0A3 for ; Wed, 4 Nov 2020 16:51:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7A9F22074B for ; Wed, 4 Nov 2020 16:51:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="k52noqyA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731818AbgKDQvM (ORCPT ); Wed, 4 Nov 2020 11:51:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731723AbgKDQu0 (ORCPT ); Wed, 4 Nov 2020 11:50:26 -0500 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2678FC0613D3; Wed, 4 Nov 2020 08:50:26 -0800 (PST) Received: by mail-lf1-x144.google.com with SMTP id h6so28024486lfj.3; Wed, 04 Nov 2020 08:50:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mbYLixKAKMh01u2kjS61AwjX8itdjctHpznoDrWxbbw=; b=k52noqyAvvAq8ManCN0BMbmq87pyAcvZNen2rsj6tJpkRaItqSC/7vFIN5mpiTQ79r vz/GGKaFwbFOOqywvyLfyW3XorZLqJnskOXiwUiegVB9VboQc2b67VmjesrpMFFI7ol1 iR4T6oTGan5a4ljuvE0MM8RiWNoz/UFOkx0DO9MG2bSRGeIASfmVvco4ErQBPfHpa/GX KpRBB2kD8DD4mDh56cfLiCBRz92DCxvPiMqUDK0nJClk3jseGji03Py0tNpoMd9fhe9V nUGO0g7/N6OsB6gkpfYdA7kMeJI8OYiRLHsnw1XDlZjl22PkbYADlbi6SeROYlfD8bK2 qKXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mbYLixKAKMh01u2kjS61AwjX8itdjctHpznoDrWxbbw=; b=oQU68QCPyZtp8e1TnQyy5O0A72jdyp03BQpD8WNDLNPG413k7YG04l79/7fkHoQkn6 AvRSr4UTq1T0gS3XyEZE7hCQyxvhc32Nmow1A+wVKTgfh/cNFhXUpKrLLZgEZskj5gL/ NJCbnYNKpWhG/uZn/GTtdb7sVcc7m7IFxCNQ36Eq6ry5zbxrKbPoTyB1e1WptkZn+FYW GNICRTIL40TrJvN8aWgqY6FgKe8ftxArtrPTxE0xGfoQ+2hmUDvk3Q2o0CZHLVP/1sco X5OgAc6swrAo8SsUGgaY8W0j8I//VXq7VnJG1XC/f5WKg/snWEFZ4b649jW1KPm5B138 bsQg== X-Gm-Message-State: AOAM530sNCs8rPZfDUdcb2yubvMOexMo/Y48DofxHgeLylJR5BLblSA3 PwTErlZttZfEQOMCVjC3n2I= X-Google-Smtp-Source: ABdhPJxkcY4Zv+2j1nCRhM0A7S9j0DyXmGdVYXojshDsYWTvQbccdEztcR0un4e5qtRem8AabGP4OQ== X-Received: by 2002:ac2:592f:: with SMTP id v15mr6583677lfi.512.1604508624645; Wed, 04 Nov 2020 08:50:24 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:24 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 45/47] PM / devfreq: tegra30: Support interconnect and OPPs from device-tree Date: Wed, 4 Nov 2020 19:49:21 +0300 Message-Id: <20201104164923.21238-46-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch moves ACTMON driver away from generating OPP table by itself, transitioning it to use the table which comes from device-tree. This change breaks compatibility with older device-trees in order to bring support for the interconnect framework to the driver. This is a mandatory change which needs to be done in order to implement interconnect-based memory DVFS. Users of legacy device-trees will get a message telling that theirs DT needs to be upgraded. Now ACTMON issues memory bandwidth request using dev_pm_opp_set_bw(), instead of driving EMC clock rate directly. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko Acked-by: Chanwoo Choi --- drivers/devfreq/tegra30-devfreq.c | 96 +++++++++++++++++-------------- 1 file changed, 54 insertions(+), 42 deletions(-) diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c index 38cc0d014738..4db027ca17e1 100644 --- a/drivers/devfreq/tegra30-devfreq.c +++ b/drivers/devfreq/tegra30-devfreq.c @@ -19,6 +19,8 @@ #include #include +#include + #include "governor.h" #define ACTMON_GLB_STATUS 0x0 @@ -155,6 +157,7 @@ struct tegra_devfreq_device { struct tegra_devfreq { struct devfreq *devfreq; + struct opp_table *opp_table; struct reset_control *reset; struct clk *clock; @@ -612,34 +615,19 @@ static void tegra_actmon_stop(struct tegra_devfreq *tegra) static int tegra_devfreq_target(struct device *dev, unsigned long *freq, u32 flags) { - struct tegra_devfreq *tegra = dev_get_drvdata(dev); - struct devfreq *devfreq = tegra->devfreq; struct dev_pm_opp *opp; - unsigned long rate; - int err; + int ret; opp = devfreq_recommended_opp(dev, freq, flags); if (IS_ERR(opp)) { dev_err(dev, "Failed to find opp for %lu Hz\n", *freq); return PTR_ERR(opp); } - rate = dev_pm_opp_get_freq(opp); - dev_pm_opp_put(opp); - - err = clk_set_min_rate(tegra->emc_clock, rate * KHZ); - if (err) - return err; - - err = clk_set_rate(tegra->emc_clock, 0); - if (err) - goto restore_min_rate; - - return 0; -restore_min_rate: - clk_set_min_rate(tegra->emc_clock, devfreq->previous_freq); + ret = dev_pm_opp_set_bw(dev, opp); + dev_pm_opp_put(opp); - return err; + return ret; } static int tegra_devfreq_get_dev_status(struct device *dev, @@ -655,7 +643,7 @@ static int tegra_devfreq_get_dev_status(struct device *dev, stat->private_data = tegra; /* The below are to be used by the other governors */ - stat->current_frequency = cur_freq; + stat->current_frequency = cur_freq * KHZ; actmon_dev = &tegra->devices[MCALL]; @@ -705,7 +693,12 @@ static int tegra_governor_get_target(struct devfreq *devfreq, target_freq = max(target_freq, dev->target_freq); } - *freq = target_freq; + /* + * tegra-devfreq driver operates with KHz units, while OPP table + * entries use Hz units. Hence we need to convert the units for the + * devfreq core. + */ + *freq = target_freq * KHZ; return 0; } @@ -774,13 +767,22 @@ static struct devfreq_governor tegra_devfreq_governor = { static int tegra_devfreq_probe(struct platform_device *pdev) { + u32 hw_version = BIT(tegra_sku_info.soc_speedo_id); struct tegra_devfreq_device *dev; struct tegra_devfreq *tegra; + struct opp_table *opp_table; struct devfreq *devfreq; unsigned int i; long rate; int err; + /* legacy device-trees don't have OPP table and must be updated */ + if (!device_property_present(&pdev->dev, "operating-points-v2")) { + dev_err(&pdev->dev, + "OPP table not found, please update your device tree\n"); + return -ENODEV; + } + tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); if (!tegra) return -ENOMEM; @@ -822,11 +824,31 @@ static int tegra_devfreq_probe(struct platform_device *pdev) return err; } + tegra->opp_table = dev_pm_opp_get_opp_table(&pdev->dev); + err = PTR_ERR_OR_ZERO(tegra->opp_table); + if (err) { + dev_err(&pdev->dev, "Failed to prepare OPP table: %d\n", err); + return err; + } + + opp_table = dev_pm_opp_set_supported_hw(&pdev->dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(opp_table); + if (err) { + dev_err(&pdev->dev, "Failed to set supported HW: %d\n", err); + goto put_table; + } + + err = dev_pm_opp_of_add_table(&pdev->dev); + if (err) { + dev_err(&pdev->dev, "Failed to add OPP table: %d\n", err); + goto put_hw; + } + err = clk_prepare_enable(tegra->clock); if (err) { dev_err(&pdev->dev, "Failed to prepare and enable ACTMON clock\n"); - return err; + goto remove_table; } err = reset_control_reset(tegra->reset); @@ -850,23 +872,6 @@ static int tegra_devfreq_probe(struct platform_device *pdev) dev->regs = tegra->regs + dev->config->offset; } - for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) { - rate = clk_round_rate(tegra->emc_clock, rate); - - if (rate < 0) { - dev_err(&pdev->dev, - "Failed to round clock rate: %ld\n", rate); - err = rate; - goto remove_opps; - } - - err = dev_pm_opp_add(&pdev->dev, rate / KHZ, 0); - if (err) { - dev_err(&pdev->dev, "Failed to add OPP: %d\n", err); - goto remove_opps; - } - } - platform_set_drvdata(pdev, tegra); tegra->clk_rate_change_nb.notifier_call = tegra_actmon_clk_notify_cb; @@ -882,7 +887,6 @@ static int tegra_devfreq_probe(struct platform_device *pdev) } tegra_devfreq_profile.initial_freq = clk_get_rate(tegra->emc_clock); - tegra_devfreq_profile.initial_freq /= KHZ; devfreq = devfreq_add_device(&pdev->dev, &tegra_devfreq_profile, "tegra_actmon", NULL); @@ -902,6 +906,12 @@ static int tegra_devfreq_probe(struct platform_device *pdev) reset_control_reset(tegra->reset); disable_clk: clk_disable_unprepare(tegra->clock); +remove_table: + dev_pm_opp_of_remove_table(&pdev->dev); +put_hw: + dev_pm_opp_put_supported_hw(tegra->opp_table); +put_table: + dev_pm_opp_put_opp_table(tegra->opp_table); return err; } @@ -913,11 +923,13 @@ static int tegra_devfreq_remove(struct platform_device *pdev) devfreq_remove_device(tegra->devfreq); devfreq_remove_governor(&tegra_devfreq_governor); - dev_pm_opp_remove_all_dynamic(&pdev->dev); - reset_control_reset(tegra->reset); clk_disable_unprepare(tegra->clock); + dev_pm_opp_of_remove_table(&pdev->dev); + dev_pm_opp_put_supported_hw(tegra->opp_table); + dev_pm_opp_put_opp_table(tegra->opp_table); + return 0; } From patchwork Wed Nov 4 16:49:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FB59C4741F for ; Wed, 4 Nov 2020 16:51:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 46577206ED for ; Wed, 4 Nov 2020 16:51:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RaOKVsHl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731124AbgKDQu7 (ORCPT ); Wed, 4 Nov 2020 11:50:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731737AbgKDQu1 (ORCPT ); Wed, 4 Nov 2020 11:50:27 -0500 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 659B1C0613D3; Wed, 4 Nov 2020 08:50:27 -0800 (PST) Received: by mail-lj1-x229.google.com with SMTP id x6so23723780ljd.3; Wed, 04 Nov 2020 08:50:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0iEwaTGjBhhhYbqhEB674AFJTwQ7XfjZia90rQHHnqQ=; b=RaOKVsHl0zQ706fDUOJ4r3MY+qrWEFTCtfEgOzBQc4TFtDZLWSLDIdWoTn/DhShhX4 UpB2hqZc5X3ZwOWK7leoEm9cuuL/a9L8c+4axgQ3oOYk1vPHTF4qruUm52QwS1efJkvA Q0DINB6hbWYv9Bj57TeeZwSWZRw+ibVe8oqF2WUozTZR9FaH/0tob/gYIXHXBD6EaIiI HWSY9bRwSb5BQdHJT65GH1+Fwi1ITzWLREmAUEJZ5raO6WRMEPSiRl0LRFR9lgXFIUwZ jwMrAmq5ZK2gnKN2JiB8vt1ZorV08LOT06nZQz8d8VOH9sChFmKuO2z5rKLcWx4KSZca lOOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0iEwaTGjBhhhYbqhEB674AFJTwQ7XfjZia90rQHHnqQ=; b=RPi+Ia6OeRIWmoJsQL0XeIgGKe+LeinYCterar3L9iqpE7NxQbds7fiM2DSc7Ina7u ws38cIojR7Pt3AsfQJgb7MqcJVaJ3wH3/PpJaVsa2J09BHDFUDaLuBZDROO8dbu7eDUc Bevk58aZTaXWaYs4IzhhAEI74fOxz6MGgm456yILd1JNbadG6RF49JOuTSpEYaRMUKxf BGP/euL8rVSATif/NuMrrVwY6zo03Jdszb3Q63aVwatkPYiEm4vUIjI0chjNnEHNKycY sHWYlogsfv3gYsOpXHEsRJo/o5Z4YMP5d7XRU3He102WJGU1MHwzO3ZP24d7Ex2XGQIV oCMg== X-Gm-Message-State: AOAM530FllejDVojV001fQmqeXcX6LSIrMjGNKxnMD/MIImwPuwXOncG y6GWUJEVfchXM/uHmgQR2ZY= X-Google-Smtp-Source: ABdhPJzi8UyuzGks82q4fzvpFQNvhcIrq5nuS+hMmVa6Y/MRKXlWqjSwqjZ6sMPrylaY5AUN02CHbw== X-Received: by 2002:a2e:b0c7:: with SMTP id g7mr10368958ljl.433.1604508625829; Wed, 04 Nov 2020 08:50:25 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:25 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 46/47] PM / devfreq: tegra30: Separate configurations per-SoC generation Date: Wed, 4 Nov 2020 19:49:22 +0300 Message-Id: <20201104164923.21238-47-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Previously we were using count-weight of the T124 for T30 in order to get EMC clock rate that was reasonable for T30. In fact the count-weight should be x2 times smaller on T30, but then devfreq was producing a bit too low EMC clock rate for ISO memory clients, like display controller for example. Now both Tegra ACTMON and Tegra DRM display drivers support interconnect framework and display driver tells to ICC what a minimum memory bandwidth is needed, preventing FIFO underflows. Thus, now we can use a proper count-weight value for Tegra30 and MC_ALL device config needs a bit more aggressive boosting. Add a separate ACTMON driver configuration that is specific to Tegra30. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko Acked-by: Chanwoo Choi --- drivers/devfreq/tegra30-devfreq.c | 68 ++++++++++++++++++++++++------- 1 file changed, 54 insertions(+), 14 deletions(-) diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c index 4db027ca17e1..aaa22077815c 100644 --- a/drivers/devfreq/tegra30-devfreq.c +++ b/drivers/devfreq/tegra30-devfreq.c @@ -57,13 +57,6 @@ #define ACTMON_BELOW_WMARK_WINDOW 3 #define ACTMON_BOOST_FREQ_STEP 16000 -/* - * Activity counter is incremented every 256 memory transactions, and each - * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is - * 4 * 256 = 1024. - */ -#define ACTMON_COUNT_WEIGHT 0x400 - /* * ACTMON_AVERAGE_WINDOW_LOG2: default value for @DEV_CTRL_K_VAL, which * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128 @@ -111,7 +104,7 @@ enum tegra_actmon_device { MCCPU, }; -static const struct tegra_devfreq_device_config actmon_device_configs[] = { +static const struct tegra_devfreq_device_config tegra124_device_configs[] = { { /* MCALL: All memory accesses (including from the CPUs) */ .offset = 0x1c0, @@ -133,6 +126,28 @@ static const struct tegra_devfreq_device_config actmon_device_configs[] = { }, }; +static const struct tegra_devfreq_device_config tegra30_device_configs[] = { + { + /* MCALL: All memory accesses (including from the CPUs) */ + .offset = 0x1c0, + .irq_mask = 1 << 26, + .boost_up_coeff = 200, + .boost_down_coeff = 50, + .boost_up_threshold = 20, + .boost_down_threshold = 10, + }, + { + /* MCCPU: memory accesses from the CPUs */ + .offset = 0x200, + .irq_mask = 1 << 25, + .boost_up_coeff = 800, + .boost_down_coeff = 40, + .boost_up_threshold = 27, + .boost_down_threshold = 10, + .avg_dependency_threshold = 16000, /* 16MHz in kHz units */ + }, +}; + /** * struct tegra_devfreq_device - state specific to an ACTMON device * @@ -155,6 +170,12 @@ struct tegra_devfreq_device { unsigned long target_freq; }; +struct tegra_devfreq_soc_data { + const struct tegra_devfreq_device_config *configs; + /* Weight value for count measurements */ + unsigned int count_weight; +}; + struct tegra_devfreq { struct devfreq *devfreq; struct opp_table *opp_table; @@ -171,11 +192,13 @@ struct tegra_devfreq { struct delayed_work cpufreq_update_work; struct notifier_block cpu_rate_change_nb; - struct tegra_devfreq_device devices[ARRAY_SIZE(actmon_device_configs)]; + struct tegra_devfreq_device devices[2]; unsigned int irq; bool started; + + const struct tegra_devfreq_soc_data *soc; }; struct tegra_actmon_emc_ratio { @@ -488,7 +511,7 @@ static void tegra_actmon_configure_device(struct tegra_devfreq *tegra, tegra_devfreq_update_avg_wmark(tegra, dev); tegra_devfreq_update_wmark(tegra, dev); - device_writel(dev, ACTMON_COUNT_WEIGHT, ACTMON_DEV_COUNT_WEIGHT); + device_writel(dev, tegra->soc->count_weight, ACTMON_DEV_COUNT_WEIGHT); device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS); val |= ACTMON_DEV_CTRL_ENB_PERIODIC; @@ -787,6 +810,8 @@ static int tegra_devfreq_probe(struct platform_device *pdev) if (!tegra) return -ENOMEM; + tegra->soc = of_device_get_match_data(&pdev->dev); + tegra->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(tegra->regs)) return PTR_ERR(tegra->regs); @@ -866,9 +891,9 @@ static int tegra_devfreq_probe(struct platform_device *pdev) tegra->max_freq = rate / KHZ; - for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) { + for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) { dev = tegra->devices + i; - dev->config = actmon_device_configs + i; + dev->config = tegra->soc->configs + i; dev->regs = tegra->regs + dev->config->offset; } @@ -933,9 +958,24 @@ static int tegra_devfreq_remove(struct platform_device *pdev) return 0; } +static const struct tegra_devfreq_soc_data tegra124_soc = { + .configs = tegra124_device_configs, + + /* + * Activity counter is incremented every 256 memory transactions, + * and each transaction takes 4 EMC clocks. + */ + .count_weight = 4 * 256, +}; + +static const struct tegra_devfreq_soc_data tegra30_soc = { + .configs = tegra30_device_configs, + .count_weight = 2 * 256, +}; + static const struct of_device_id tegra_devfreq_of_match[] = { - { .compatible = "nvidia,tegra30-actmon" }, - { .compatible = "nvidia,tegra124-actmon" }, + { .compatible = "nvidia,tegra30-actmon", .data = &tegra30_soc, }, + { .compatible = "nvidia,tegra124-actmon", .data = &tegra124_soc, }, { }, };