From patchwork Thu Oct 8 19:14:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 317526 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp1667727ilm; Thu, 8 Oct 2020 12:15:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxf3iDVNsat5z6TLNw8pnuAKnWutfGRkTycDNLpLuVc3R7zJLu6kx/emiSoGVK5+uk0ZR8V X-Received: by 2002:aa7:d352:: with SMTP id m18mr10469158edr.287.1602184512501; Thu, 08 Oct 2020 12:15:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602184512; cv=none; d=google.com; s=arc-20160816; b=S9mu2iYw9KK6BdxM/6LOIt0ygbiFibeTFxhMp5hF3rQJ5wC0b9woFoAsW6nYIy+qPa sGr33e679MeTdlGYufzVyZnGZyl+l0L2Goq0X5wbBwxivRwMK4vr0+PrZl8Gic+BClyb tvSyN/zbNLjLNDWCSqLnR6EKrv0WfU0xdr1SJNr2gH6vSl+j8fF5KEI1iMFcGUiBsDDv vDBdLxK2N4PHiMhWfhMUSQB6L4m+RDt/yHTKmk4SBjyvn5eC4v1YQ9srhax+3NdfZUKa Pt9Poza8SXnrHZ7cK1mKNHf1FKN853rA2aKz22tetP7F8+2hTq+lPjZWq0M7jlMFIDxA SSzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=bF5gXXr+ssmc7bZu2xeC0A/E2MTwIXKkSJH63heuYHo=; b=CR0R8tRmIUWV0J8xqzPGTxlaSJ1MBxiEJvEm6K7TxZDazPHuDLS5Dp4JcdHXc4S2f0 q5J5wWvL88pPVv2FpqiY9FLMtyokLbcKKl8030px1op0JftfxL2QCiWyvnLZO/XI8lmU +BpJ99+eKEqzs3z+Bdg7AdhGA/HiRZHfg7skFs4NcBjBWIK/czGxno/+zbUyu0pLdo1b fHfS8EZbtkJfRXrYe8tv41rL4OrCZVUQ+r1l4mueAtr7r5fopWmc4Os0hNiSQG9mkP1T LIziAh13MyqANxMBBob/e0vD1r2dhOpxV55CK9J4cPwJV2S6nMqNwO8a/MAOh5M6pXQz F/nw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bw3si4437136ejb.515.2020.10.08.12.15.12; Thu, 08 Oct 2020 12:15:12 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729640AbgJHTPE (ORCPT + 6 others); Thu, 8 Oct 2020 15:15:04 -0400 Received: from foss.arm.com ([217.140.110.172]:45324 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726469AbgJHTPB (ORCPT ); Thu, 8 Oct 2020 15:15:01 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 489D0152F; Thu, 8 Oct 2020 12:15:01 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B78353F70D; Thu, 8 Oct 2020 12:14:59 -0700 (PDT) From: Sudeep Holla To: Jassi Brar , Jassi Brar , Viresh Kumar , ALKML , DTML , LKML Cc: Sudeep Holla , Vincent Guittot , Frank Rowand , Bjorn Andersson , Rob Herring , Rob Herring Subject: [PATCH v2 1/4] dt-bindings: mailbox : arm, mhu: Convert to Json-schema Date: Thu, 8 Oct 2020 20:14:49 +0100 Message-Id: <20201008191452.38672-2-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201008191452.38672-1-sudeep.holla@arm.com> References: <20201008191452.38672-1-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Viresh Kumar Convert the DT binding over to Json-schema. Reviewed-by: Rob Herring Signed-off-by: Viresh Kumar Signed-off-by: Sudeep Holla --- .../devicetree/bindings/mailbox/arm,mhu.yaml | 87 +++++++++++++++++++ .../devicetree/bindings/mailbox/arm-mhu.txt | 43 --------- 2 files changed, 87 insertions(+), 43 deletions(-) create mode 100644 Documentation/devicetree/bindings/mailbox/arm,mhu.yaml delete mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml new file mode 100644 index 000000000000..2c8df7979c22 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/arm,mhu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM MHU Mailbox Controller + +maintainers: + - Jassi Brar + +description: | + The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3 + independent channels/links to communicate with remote processor(s). MHU links + are hardwired on a platform. A link raises interrupt for any received data. + However, there is no specified way of knowing if the sent data has been read + by the remote. This driver assumes the sender polls STAT register and the + remote clears it after having read the data. The last channel is specified to + be a 'Secure' resource, hence can't be used by Linux running NS. + +# We need a select here so we don't match all nodes with 'arm,primecell' +select: + properties: + compatible: + contains: + const: arm,mhu + required: + - compatible + +properties: + compatible: + items: + - const: arm,mhu + - const: arm,primecell + + reg: + maxItems: 1 + + interrupts: + items: + - description: low-priority non-secure + - description: high-priority non-secure + - description: Secure + maxItems: 3 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + '#mbox-cells': + description: Index of the channel. + const: 1 + +required: + - compatible + - reg + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mhuA: mailbox@2b1f0000 { + #mbox-cells = <1>; + compatible = "arm,mhu", "arm,primecell"; + reg = <0 0x2b1f0000 0 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + mhu_client_scb: scb@2e000000 { + compatible = "fujitsu,mb86s70-scb-1.0"; + reg = <0 0x2e000000 0 0x4000>; + mboxes = <&mhuA 1>; /* HP-NonSecure */ + }; + }; diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt deleted file mode 100644 index 4971f03f0b33..000000000000 --- a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt +++ /dev/null @@ -1,43 +0,0 @@ -ARM MHU Mailbox Driver -====================== - -The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has -3 independent channels/links to communicate with remote processor(s). - MHU links are hardwired on a platform. A link raises interrupt for any -received data. However, there is no specified way of knowing if the sent -data has been read by the remote. This driver assumes the sender polls -STAT register and the remote clears it after having read the data. -The last channel is specified to be a 'Secure' resource, hence can't be -used by Linux running NS. - -Mailbox Device Node: -==================== - -Required properties: --------------------- -- compatible: Shall be "arm,mhu" & "arm,primecell" -- reg: Contains the mailbox register address range (base - address and length) -- #mbox-cells Shall be 1 - the index of the channel needed. -- interrupts: Contains the interrupt information corresponding to - each of the 3 links of MHU. - -Example: --------- - - mhu: mailbox@2b1f0000 { - #mbox-cells = <1>; - compatible = "arm,mhu", "arm,primecell"; - reg = <0 0x2b1f0000 0x1000>; - interrupts = <0 36 4>, /* LP-NonSecure */ - <0 35 4>, /* HP-NonSecure */ - <0 37 4>; /* Secure */ - clocks = <&clock 0 2 1>; - clock-names = "apb_pclk"; - }; - - mhu_client: scb@2e000000 { - compatible = "fujitsu,mb86s70-scb-1.0"; - reg = <0 0x2e000000 0x4000>; - mboxes = <&mhu 1>; /* HP-NonSecure */ - }; From patchwork Thu Oct 8 19:14:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 317527 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp1667739ilm; Thu, 8 Oct 2020 12:15:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzYk1nHVkQ0swiHoHHRF9gU1XzVH+VJYKyPEvmwYmMSHVfm+DBscTHlcnHMkSIma5n59Q9F X-Received: by 2002:a50:c309:: with SMTP id a9mr10841868edb.199.1602184513090; Thu, 08 Oct 2020 12:15:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602184513; cv=none; d=google.com; s=arc-20160816; b=gJ9NKB8nBxMcb/7y8Dgxfrsvx5ufJ/DHpKivg9xdeYNQgdcWGvlV5GhrFbu9fbJyrQ BUnj4vR473TYxeRWfnxzeNVbVnfNSXc7sIPZ4WTfdy+SEYGgZWbtu+n1L/IznA4WCv27 ivpHGcMZOj8orITe9pLSDZ7rOpVKOet7buf+B/y3klBVnW+LXd3jlSvjOtIIosjkWcVb oerKeTu1b9BgZlrJObLKUs2V69C3nsQMfuVfBCjS9R4P+V5lV40iq/BlnzK7vysYh2BB t+X0+pQ9KltV8ptkE6XoNeBOhaV29hzjM3wgBK4ijte7ECkH7uAfT9C2SWXrDQgcgR9j hC+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=76oPjUgbJRwqgwHcwk60j6uv3w0FZYuw4+zw5UdLA88=; b=IS7v3DPPS8iSth3UJZDN8jVCcOzZGAjtAG76b1/SAYxoYsJL5Ssm9sm2C09n9yKKP3 LlKtW49Dd0Hh2iZzFG+erNW2oLzmzNxtN7Atj4vTP6x0jwxN4r+ZdMC/PIGDHkFvIM0v DN4KTcsY78SU3XtuEfJt3TQb9++okqPyEJQKazweGPupOBTuGbt7Jg2BS2d68np2mOLq bMJseDMw8hB4UxE6sOcEK8zxv7TaRjFUnbMfNm0iikE5+v3sd2sCUIYWschsmqylr9W7 OuovtOcqFz0/9G1emahRXhBOKHEP7v9P+DCwD2j0z8/DffaNjBoui5B1hFgMCnAF3XVm Dfcg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bw3si4437136ejb.515.2020.10.08.12.15.12; Thu, 08 Oct 2020 12:15:13 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729626AbgJHTPD (ORCPT + 6 others); Thu, 8 Oct 2020 15:15:03 -0400 Received: from foss.arm.com ([217.140.110.172]:45330 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729620AbgJHTPD (ORCPT ); Thu, 8 Oct 2020 15:15:03 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0E5121529; Thu, 8 Oct 2020 12:15:03 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7B9803F70D; Thu, 8 Oct 2020 12:15:01 -0700 (PDT) From: Sudeep Holla To: Jassi Brar , Jassi Brar , Viresh Kumar , ALKML , DTML , LKML Cc: Sudeep Holla , Vincent Guittot , Frank Rowand , Bjorn Andersson , Rob Herring , Rob Herring Subject: [PATCH v2 2/4] dt-bindings: mailbox: add doorbell support to ARM MHU Date: Thu, 8 Oct 2020 20:14:50 +0100 Message-Id: <20201008191452.38672-3-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201008191452.38672-1-sudeep.holla@arm.com> References: <20201008191452.38672-1-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ARM MHU's reference manual states following: "The MHU drives the signal using a 32-bit register, with all 32 bits logically ORed together. The MHU provides a set of registers to enable software to set, clear, and check the status of each of the bits of this register independently. The use of 32 bits for each interrupt line enables software to provide more information about the source of the interrupt. For example, each bit of the register can be associated with a type of event that can contribute to raising the interrupt." This patch thus extends the MHU controller's DT binding to add support for doorbell mode. Though the same MHU hardware controller is used in the two modes, A new compatible string is added here to represent the combination of the MHU hardware and the firmware sitting on the other side (which expects each bit to represent a different signal now). Reviewed-by: Rob Herring Acked-by: Arnd Bergmann Co-developed-by: Viresh Kumar Signed-off-by: Viresh Kumar Signed-off-by: Sudeep Holla --- .../devicetree/bindings/mailbox/arm,mhu.yaml | 60 +++++++++++++++++-- 1 file changed, 54 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml index 2c8df7979c22..d43791a2dde7 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml @@ -18,20 +18,40 @@ description: | remote clears it after having read the data. The last channel is specified to be a 'Secure' resource, hence can't be used by Linux running NS. + The MHU hardware also allows operations in doorbell mode. The MHU drives the + interrupt signal using a 32-bit register, with all 32-bits logically ORed + together. It provides a set of registers to enable software to set, clear and + check the status of each of the bits of this register independently. The use + of 32 bits per interrupt line enables software to provide more information + about the source of the interrupt. For example, each bit of the register can + be associated with a type of event that can contribute to raising the + interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote + processor. + # We need a select here so we don't match all nodes with 'arm,primecell' select: properties: compatible: contains: - const: arm,mhu + enum: + - arm,mhu + - arm,mhu-doorbell required: - compatible properties: compatible: - items: - - const: arm,mhu - - const: arm,primecell + oneOf: + - description: Data transfer mode + items: + - const: arm,mhu + - const: arm,primecell + + - description: Doorbell mode + items: + - const: arm,mhu-doorbell + - const: arm,primecell + reg: maxItems: 1 @@ -51,8 +71,11 @@ description: | - const: apb_pclk '#mbox-cells': - description: Index of the channel. - const: 1 + description: | + Set to 1 in data transfer mode and represents index of the channel. + Set to 2 in doorbell mode and represents index of the channel and doorbell + number. + enum: [ 1, 2 ] required: - compatible @@ -63,6 +86,7 @@ description: | additionalProperties: false examples: + # Data transfer mode. - | soc { #address-cells = <2>; @@ -85,3 +109,27 @@ additionalProperties: false mboxes = <&mhuA 1>; /* HP-NonSecure */ }; }; + + # Doorbell mode. + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mhuB: mailbox@2b2f0000 { + #mbox-cells = <2>; + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0 0x2b2f0000 0 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + mhu_client_scpi: scpi@2f000000 { + compatible = "arm,scpi"; + reg = <0 0x2f000000 0 0x200>; + mboxes = <&mhuB 1 4>; /* HP-NonSecure, 5th doorbell */ + }; + }; From patchwork Thu Oct 8 19:14:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 317525 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp1667714ilm; Thu, 8 Oct 2020 12:15:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwx7A9RJk6S5GAaAfBJ4yp5/d+V+YeOI5NjivS1gtRQrjPZ60k7ajPH9oQ/HZsSt4eARmh4 X-Received: by 2002:a05:6402:1012:: with SMTP id c18mr10438415edu.77.1602184511487; Thu, 08 Oct 2020 12:15:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602184511; cv=none; d=google.com; s=arc-20160816; b=mPg97Y7n9yZ28VyHHYTWtlT867Z2we48ng2H2/l3EWAQF8sxvoToQ8B8v1UPHBaLYq LNcvsPuehTLta9teJStISqPj2RmujCyzHKiixyiq2WEAsq8EyuAez1cy0NG9S8Rc3j28 UUNprbmuBmROEKO73NNAUglTF4c9bubMQ/91doxzETguFfkY5bVRx5Ck9oUo33LfUI+d wTbH8MDowWaxW668Ydt9ja8pKATiUXOu3HgCQBBhBNuSOgZ3BcWxPUF6XbbflHDDDPov y50SgqYXOvuJPoixxJtmPv6SwpdsJlgU95ZGMgxtytvacghGeYCNZW+SikHydhpkysfy +Vlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=UUwJs4P1DqFLb+/9QcgvuwdxLm4ikSjENMblrccvMV8=; b=qhB1ZxjUD3WmyL2X7fX8EqmzsfLsnspg1cddjv3qABmtZQ0m8d00M9AQ9EUoIP5Yvn B19DH2iAGwJmR1S/UolYzKcn+Im6v/gBJoA+VpGslo6d+dTKxqtuvC007JJuSxSMAqXt X86qES8hyXsh7RZz49V6WRLQroMDU6nrl7CE8flmFY7i+hieiQMdnAyfSd25L4vq0mTr kpo+2IVSTQB3XSiEhbFeFcVZtxRsH5aoqSgrEk17hFgcjJCDjX+s60+c7cLphqUgn1DH KPtdPe0BWA+LJUowkD6pq5G5gOpB5Ry6GzQP00wtG+atOvmXtpUOlKntTFNr27wwu9Oe q89A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bw3si4437136ejb.515.2020.10.08.12.15.11; Thu, 08 Oct 2020 12:15:11 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729674AbgJHTPH (ORCPT + 6 others); Thu, 8 Oct 2020 15:15:07 -0400 Received: from foss.arm.com ([217.140.110.172]:45348 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729651AbgJHTPF (ORCPT ); Thu, 8 Oct 2020 15:15:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CEF6B153B; Thu, 8 Oct 2020 12:15:04 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3F8B63F70D; Thu, 8 Oct 2020 12:15:03 -0700 (PDT) From: Sudeep Holla To: Jassi Brar , Jassi Brar , Viresh Kumar , ALKML , DTML , LKML Cc: Sudeep Holla , Vincent Guittot , Frank Rowand , Bjorn Andersson , Rob Herring , Rob Herring Subject: [PATCH v2 3/4] mailbox: arm_mhu: Match only if compatible is "arm, mhu" Date: Thu, 8 Oct 2020 20:14:51 +0100 Message-Id: <20201008191452.38672-4-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201008191452.38672-1-sudeep.holla@arm.com> References: <20201008191452.38672-1-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since we will be soon adding a separate driver based on this ARM MHU driver to support doorbell mode, let us add explicit check to match the default compatible for this driver. This is needed as the probe and match reuses the AMBA device ids currently and don't have any explicit compatible check. Signed-off-by: Sudeep Holla --- drivers/mailbox/arm_mhu.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/drivers/mailbox/arm_mhu.c b/drivers/mailbox/arm_mhu.c index 9da236552bd7..b7fbf276eb62 100644 --- a/drivers/mailbox/arm_mhu.c +++ b/drivers/mailbox/arm_mhu.c @@ -113,6 +113,9 @@ static int mhu_probe(struct amba_device *adev, const struct amba_id *id) struct device *dev = &adev->dev; int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET}; + if (!of_device_is_compatible(dev->of_node, "arm,mhu")) + return -ENODEV; + /* Allocate memory for device */ mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL); if (!mhu) From patchwork Thu Oct 8 19:14:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 317528 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp1667791ilm; Thu, 8 Oct 2020 12:15:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy/ll9MuPwsC7H7fxU3vzoAYEOLQO0VSDY8+piHZzCrfn8dGlghy93/NlXRyBV6w9kg8WR2 X-Received: by 2002:a17:906:b2d1:: with SMTP id cf17mr10174227ejb.321.1602184516867; Thu, 08 Oct 2020 12:15:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602184516; cv=none; d=google.com; s=arc-20160816; b=UyB0MXQXvO/7eN3omwzG24y+dslADjIez1cpp7egpHg2nvZNFRzt77xKByVOkGBP20 FW4kjJYl0IEiyWt3mTMzKhuQdka0HFU/qLA1LMA66WNDt8d5/KskwZmMEnOwAKe/tr8H i3yB3GLOBPBjvcBwIlmVTuQ0Z21ZS0sTOYVkLNgAWq2j6aic094fh5S3u5/SpIxUH+P7 VORWN3EuHRbBTgnhwEOX+a/v4+NZPfR16cP356nMA43cS6B+6c2dUfkuBUOInui7OjWC iO0CEOcZXLr2L4UpBtCyBk4UfMCBnhKLyZMynwZJhBqIWAXtMChVkytpTEygFGhtEfjJ rF1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=JVL/K2sgEvI7p44E+gclVZppNHnORIeBJhiLzX7nGg0=; b=f39c4UXP+rmgDjG67cen+CFzYG1vYr81BqZ+Rhrp1nedmnCeD9bsnDl+7mal+dr5V7 gD+FTHe25nkWrrDD5Ke7m4xWNjCYCQPFo67kzH0Zi7nwk5pKKmWdOY9EXKp7k+61mDLW ToN1bC4bTZV5olhYt4nA4Gxaxn/fIyNIzWCaJzdbkp2B4TwFHtx7G4aaGyyCZYGQ4xvB BVFU++2MYFF5v4ktE2z+C1okE9rIA5bmxoS8nrNUm7zoJSGbfldA9KOnPCgdqvBWwrzQ /vhVFMYZ2bTiT+7KzQOVTDOGPU90OQmN6TxO2plYgXv19XB5p5gZ7rEMDlQacsnMQbBg tS8Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bw3si4437136ejb.515.2020.10.08.12.15.16; Thu, 08 Oct 2020 12:15:16 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729718AbgJHTPQ (ORCPT + 6 others); Thu, 8 Oct 2020 15:15:16 -0400 Received: from foss.arm.com ([217.140.110.172]:45368 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726469AbgJHTPH (ORCPT ); Thu, 8 Oct 2020 15:15:07 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 95FFB1063; Thu, 8 Oct 2020 12:15:06 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0F6FD3F70D; Thu, 8 Oct 2020 12:15:04 -0700 (PDT) From: Sudeep Holla To: Jassi Brar , Jassi Brar , Viresh Kumar , ALKML , DTML , LKML Cc: Sudeep Holla , Vincent Guittot , Frank Rowand , Bjorn Andersson , Rob Herring , Rob Herring Subject: [PATCH v2 4/4] mailbox: arm_mhu: Add ARM MHU doorbell driver Date: Thu, 8 Oct 2020 20:14:52 +0100 Message-Id: <20201008191452.38672-5-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201008191452.38672-1-sudeep.holla@arm.com> References: <20201008191452.38672-1-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The MHU drives the signal using a 32-bit register, with all 32 bits logically ORed together. The MHU provides a set of registers to enable software to set, clear, and check the status of each of the bits of this register independently. The use of 32 bits for each interrupt line enables software to provide more information about the source of the interrupt. For example, each bit of the register can be associated with a type of event that can contribute to raising the interrupt. This patch adds a separate the MHU controller driver for doorbel mode of operation using the extended DT binding to add support the same. Signed-off-by: Sudeep Holla --- drivers/mailbox/Makefile | 2 +- drivers/mailbox/arm_mhu_db.c | 354 +++++++++++++++++++++++++++++++++++ 2 files changed, 355 insertions(+), 1 deletion(-) create mode 100644 drivers/mailbox/arm_mhu_db.c -- 2.17.1 diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 60d224b723a1..2e06e02b2e03 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_MAILBOX) += mailbox.o obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o -obj-$(CONFIG_ARM_MHU) += arm_mhu.o +obj-$(CONFIG_ARM_MHU) += arm_mhu.o arm_mhu_db.o obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o diff --git a/drivers/mailbox/arm_mhu_db.c b/drivers/mailbox/arm_mhu_db.c new file mode 100644 index 000000000000..275efe4cca0c --- /dev/null +++ b/drivers/mailbox/arm_mhu_db.c @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd. + * Copyright (C) 2015 Linaro Ltd. + * Based on ARM MHU driver by Jassi Brar + * Copyright (C) 2020 ARM Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define INTR_STAT_OFS 0x0 +#define INTR_SET_OFS 0x8 +#define INTR_CLR_OFS 0x10 + +#define MHU_LP_OFFSET 0x0 +#define MHU_HP_OFFSET 0x20 +#define MHU_SEC_OFFSET 0x200 +#define TX_REG_OFFSET 0x100 + +#define MHU_CHANS 3 /* Secure, Non-Secure High and Low Priority */ +#define MHU_CHAN_MAX 20 /* Max channels to save on unused RAM */ +#define MHU_NUM_DOORBELLS 32 + +struct mhu_db_link { + unsigned int irq; + void __iomem *tx_reg; + void __iomem *rx_reg; +}; + +struct arm_mhu { + void __iomem *base; + struct mhu_db_link mlink[MHU_CHANS]; + struct mbox_controller mbox; + struct device *dev; +}; + +/** + * ARM MHU Mailbox allocated channel information + * + * @mhu: Pointer to parent mailbox device + * @pchan: Physical channel within which this doorbell resides in + * @doorbell: doorbell number pertaining to this channel + */ +struct mhu_db_channel { + struct arm_mhu *mhu; + unsigned int pchan; + unsigned int doorbell; +}; + +static inline struct mbox_chan * +mhu_db_mbox_to_channel(struct mbox_controller *mbox, unsigned int pchan, + unsigned int doorbell) +{ + int i; + struct mhu_db_channel *chan_info; + + for (i = 0; i < mbox->num_chans; i++) { + chan_info = mbox->chans[i].con_priv; + if (chan_info && chan_info->pchan == pchan && + chan_info->doorbell == doorbell) + return &mbox->chans[i]; + } + + return NULL; +} + +static void mhu_db_mbox_clear_irq(struct mbox_chan *chan) +{ + struct mhu_db_channel *chan_info = chan->con_priv; + void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].rx_reg; + + writel_relaxed(BIT(chan_info->doorbell), base + INTR_CLR_OFS); +} + +static unsigned int mhu_db_mbox_irq_to_pchan_num(struct arm_mhu *mhu, int irq) +{ + unsigned int pchan; + + for (pchan = 0; pchan < MHU_CHANS; pchan++) + if (mhu->mlink[pchan].irq == irq) + break; + return pchan; +} + +static struct mbox_chan * +mhu_db_mbox_irq_to_channel(struct arm_mhu *mhu, unsigned int pchan) +{ + unsigned long bits; + unsigned int doorbell; + struct mbox_chan *chan = NULL; + struct mbox_controller *mbox = &mhu->mbox; + void __iomem *base = mhu->mlink[pchan].rx_reg; + + bits = readl_relaxed(base + INTR_STAT_OFS); + if (!bits) + /* No IRQs fired in specified physical channel */ + return NULL; + + /* An IRQ has fired, find the associated channel */ + for (doorbell = 0; bits; doorbell++) { + if (!test_and_clear_bit(doorbell, &bits)) + continue; + + chan = mhu_db_mbox_to_channel(mbox, pchan, doorbell); + if (chan) + break; + dev_err(mbox->dev, + "Channel not registered: pchan: %d doorbell: %d\n", + pchan, doorbell); + } + + return chan; +} + +static irqreturn_t mhu_db_mbox_rx_handler(int irq, void *data) +{ + struct mbox_chan *chan; + struct arm_mhu *mhu = data; + unsigned int pchan = mhu_db_mbox_irq_to_pchan_num(mhu, irq); + + while (NULL != (chan = mhu_db_mbox_irq_to_channel(mhu, pchan))) { + mbox_chan_received_data(chan, NULL); + mhu_db_mbox_clear_irq(chan); + } + + return IRQ_HANDLED; +} + +static bool mhu_db_last_tx_done(struct mbox_chan *chan) +{ + struct mhu_db_channel *chan_info = chan->con_priv; + void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].tx_reg; + + if (readl_relaxed(base + INTR_STAT_OFS) & BIT(chan_info->doorbell)) + return false; + + return true; +} + +static int mhu_db_send_data(struct mbox_chan *chan, void *data) +{ + struct mhu_db_channel *chan_info = chan->con_priv; + void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].tx_reg; + + /* Send event to co-processor */ + writel_relaxed(BIT(chan_info->doorbell), base + INTR_SET_OFS); + + return 0; +} + +static int mhu_db_startup(struct mbox_chan *chan) +{ + mhu_db_mbox_clear_irq(chan); + return 0; +} + +static void mhu_db_shutdown(struct mbox_chan *chan) +{ + struct mhu_db_channel *chan_info = chan->con_priv; + struct mbox_controller *mbox = &chan_info->mhu->mbox; + int i; + + for (i = 0; i < mbox->num_chans; i++) + if (chan == &mbox->chans[i]) + break; + + if (mbox->num_chans == i) { + dev_warn(mbox->dev, "Request to free non-existent channel\n"); + return; + } + + /* Reset channel */ + mhu_db_mbox_clear_irq(chan); + kfree(chan->con_priv); + chan->con_priv = NULL; +} + +static struct mbox_chan *mhu_db_mbox_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *spec) +{ + struct arm_mhu *mhu = dev_get_drvdata(mbox->dev); + struct mhu_db_channel *chan_info; + struct mbox_chan *chan; + unsigned int pchan = spec->args[0]; + unsigned int doorbell = spec->args[1]; + int i; + + /* Bounds checking */ + if (pchan >= MHU_CHANS || doorbell >= MHU_NUM_DOORBELLS) { + dev_err(mbox->dev, + "Invalid channel requested pchan: %d doorbell: %d\n", + pchan, doorbell); + return ERR_PTR(-EINVAL); + } + + /* Is requested channel free? */ + chan = mhu_db_mbox_to_channel(mbox, pchan, doorbell); + if (chan) { + dev_err(mbox->dev, "Channel in use: pchan: %d doorbell: %d\n", + pchan, doorbell); + return ERR_PTR(-EBUSY); + } + + /* Find the first free slot */ + for (i = 0; i < mbox->num_chans; i++) + if (!mbox->chans[i].con_priv) + break; + + if (mbox->num_chans == i) { + dev_err(mbox->dev, "No free channels left\n"); + return ERR_PTR(-EBUSY); + } + + chan = &mbox->chans[i]; + + chan_info = devm_kzalloc(mbox->dev, sizeof(*chan_info), GFP_KERNEL); + if (!chan_info) + return ERR_PTR(-ENOMEM); + + chan_info->mhu = mhu; + chan_info->pchan = pchan; + chan_info->doorbell = doorbell; + + chan->con_priv = chan_info; + + dev_dbg(mbox->dev, "mbox: created channel phys: %d doorbell: %d\n", + pchan, doorbell); + + return chan; +} + +static const struct mbox_chan_ops mhu_db_ops = { + .send_data = mhu_db_send_data, + .startup = mhu_db_startup, + .shutdown = mhu_db_shutdown, + .last_tx_done = mhu_db_last_tx_done, +}; + +static int mhu_db_probe(struct amba_device *adev, const struct amba_id *id) +{ + u32 cell_count; + int i, err, max_chans; + struct arm_mhu *mhu; + struct mbox_chan *chans; + struct device *dev = &adev->dev; + struct device_node *np = dev->of_node; + int mhu_reg[MHU_CHANS] = { + MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET, + }; + + if (!of_device_is_compatible(np, "arm,mhu-doorbell")) + return -ENODEV; + + err = of_property_read_u32(np, "#mbox-cells", &cell_count); + if (err) { + dev_err(dev, "failed to read #mbox-cells in '%pOF'\n", np); + return err; + } + + if (cell_count == 2) { + max_chans = MHU_CHAN_MAX; + } else { + dev_err(dev, "incorrect value of #mbox-cells in '%pOF'\n", np); + return -EINVAL; + } + + mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL); + if (!mhu) + return -ENOMEM; + + mhu->base = devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(mhu->base)) { + dev_err(dev, "ioremap failed\n"); + return PTR_ERR(mhu->base); + } + + chans = devm_kcalloc(dev, max_chans, sizeof(*chans), GFP_KERNEL); + if (!chans) + return -ENOMEM; + + mhu->dev = dev; + mhu->mbox.dev = dev; + mhu->mbox.chans = chans; + mhu->mbox.num_chans = max_chans; + mhu->mbox.txdone_irq = false; + mhu->mbox.txdone_poll = true; + mhu->mbox.txpoll_period = 1; + + mhu->mbox.of_xlate = mhu_db_mbox_xlate; + amba_set_drvdata(adev, mhu); + + mhu->mbox.ops = &mhu_db_ops; + + err = devm_mbox_controller_register(dev, &mhu->mbox); + if (err) { + dev_err(dev, "Failed to register mailboxes %d\n", err); + return err; + } + + for (i = 0; i < MHU_CHANS; i++) { + int irq = mhu->mlink[i].irq = adev->irq[i]; + + if (irq <= 0) { + dev_dbg(dev, "No IRQ found for Channel %d\n", i); + continue; + } + + mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i]; + mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET; + + err = devm_request_threaded_irq(dev, irq, NULL, + mhu_db_mbox_rx_handler, + IRQF_ONESHOT, "mhu_db_link", mhu); + if (err) { + dev_err(dev, "Can't claim IRQ %d\n", irq); + mbox_controller_unregister(&mhu->mbox); + return err; + } + } + + dev_info(dev, "ARM MHU Doorbell mailbox registered\n"); + return 0; +} + +static struct amba_id mhu_ids[] = { + { + .id = 0x1bb098, + .mask = 0xffffff, + }, + { 0, 0 }, +}; +MODULE_DEVICE_TABLE(amba, mhu_ids); + +static struct amba_driver arm_mhu_db_driver = { + .drv = { + .name = "mhu-doorbell", + }, + .id_table = mhu_ids, + .probe = mhu_db_probe, +}; +module_amba_driver(arm_mhu_db_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("ARM MHU Doorbell Driver"); +MODULE_AUTHOR("Sudeep Holla ");