From patchwork Fri Oct 30 00:08:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB7FBC2D0A3 for ; Fri, 30 Oct 2020 00:13:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 47DE020756 for ; Fri, 30 Oct 2020 00:13:07 +0000 (UTC) Authentication-Results: mail.kernel.org; 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envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add Taylor Simpson as the Hexagon target maintainer Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8c744a9..ba93512 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -184,6 +184,14 @@ F: include/hw/cris/ F: tests/tcg/cris/ F: disas/cris.c +Hexagon TCG CPUs +M: Taylor Simpson +S: Supported +F: target/hexagon/ +F: linux-user/hexagon/ +F: disas/hexagon.c +F: default-configs/hexagon-linux-user.mak + HPPA (PA-RISC) TCG CPUs M: Richard Henderson S: Maintained From patchwork Fri Oct 30 00:08:12 2020 Content-Type: text/plain; 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bh=3oQkrRpo7U0k1j06uRl+Ko8wJbT7hHLbi+yTj6D9sHY=; b=e967mHyH3hjwOCj46O7qwrkpmm2ba4FOZcBabmDAy0/fWFngSZCzZ6F9 JAv8W3+k5Mc1sGGrl+HM8G1cG17AdmDpwf6PpqiMX3EvYZM8ad2rUTH35 C2ZxbB9RcKCw7jjvtTvBhyprzCs7QW3x1f+FMF3rW1zHE/gVonSvMJQtB E=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 29 Oct 2020 17:08:44 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg04-sd.qualcomm.com with ESMTP; 29 Oct 2020 17:08:44 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 745E3411D; Thu, 29 Oct 2020 19:08:43 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 06/33] Hexagon (target/hexagon) register names Date: Thu, 29 Oct 2020 19:08:12 -0500 Message-Id: <1604016519-28065-7-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/hex_regs.h | 83 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 target/hexagon/hex_regs.h diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h new file mode 100644 index 0000000..3b4249a --- /dev/null +++ b/target/hexagon/hex_regs.h @@ -0,0 +1,83 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_REGS_H +#define HEXAGON_REGS_H + +enum { + HEX_REG_R00 = 0, + HEX_REG_R01 = 1, + HEX_REG_R02 = 2, + HEX_REG_R03 = 3, + HEX_REG_R04 = 4, + HEX_REG_R05 = 5, + HEX_REG_R06 = 6, + HEX_REG_R07 = 7, + HEX_REG_R08 = 8, + HEX_REG_R09 = 9, + HEX_REG_R10 = 10, + HEX_REG_R11 = 11, + HEX_REG_R12 = 12, + HEX_REG_R13 = 13, + HEX_REG_R14 = 14, + HEX_REG_R15 = 15, + HEX_REG_R16 = 16, + HEX_REG_R17 = 17, + HEX_REG_R18 = 18, + HEX_REG_R19 = 19, + HEX_REG_R20 = 20, + HEX_REG_R21 = 21, + HEX_REG_R22 = 22, + HEX_REG_R23 = 23, + HEX_REG_R24 = 24, + HEX_REG_R25 = 25, + HEX_REG_R26 = 26, + HEX_REG_R27 = 27, + HEX_REG_R28 = 28, + HEX_REG_R29 = 29, + HEX_REG_SP = 29, + HEX_REG_FP = 30, + HEX_REG_R30 = 30, + HEX_REG_LR = 31, + HEX_REG_R31 = 31, + HEX_REG_SA0 = 32, + HEX_REG_LC0 = 33, + HEX_REG_SA1 = 34, + HEX_REG_LC1 = 35, + HEX_REG_P3_0 = 36, + HEX_REG_M0 = 38, + HEX_REG_M1 = 39, + HEX_REG_USR = 40, + HEX_REG_PC = 41, + HEX_REG_UGP = 42, + HEX_REG_GP = 43, + HEX_REG_CS0 = 44, + HEX_REG_CS1 = 45, + HEX_REG_UPCYCLELO = 46, + HEX_REG_UPCYCLEHI = 47, + HEX_REG_FRAMELIMIT = 48, + HEX_REG_FRAMEKEY = 49, + HEX_REG_PKTCNTLO = 50, + HEX_REG_PKTCNTHI = 51, + /* Use reserved control registers for qemu execution counts */ + HEX_REG_QEMU_PKT_CNT = 52, + HEX_REG_QEMU_INSN_CNT = 53, + HEX_REG_UTIMERLO = 62, + HEX_REG_UTIMERHI = 63, +}; + +#endif From patchwork Fri Oct 30 00:08:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A627C2D0A3 for ; Fri, 30 Oct 2020 00:42:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8263320691 for ; Fri, 30 Oct 2020 00:42:31 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 29 Oct 2020 20:09:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1604016535; x=1635552535; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R3q9GIbeVnVM9QC3wyACZHw3p76H9oXLdeGRHiAPy5c=; b=Bvf6rj+X+0gW27QyxxB/H9/pAuvwj5oueZnb2T+r7/482VOlG5+RVN6K +9qO3dSsJC5I10diVC1ABUXUjMkBt5wKK+drcahGROQknKdY8F69Rz5hx 3LCnHOW6W+s0u5ryLjjXqeZRTwl7ZrcB7baHOwOmTlvYFcltsWbVe/2m5 w=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 29 Oct 2020 17:08:44 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg04-sd.qualcomm.com with ESMTP; 29 Oct 2020 17:08:44 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 9370E411F; Thu, 29 Oct 2020 19:08:43 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 07/33] Hexagon (target/hexagon) scalar core helpers Date: Thu, 29 Oct 2020 19:08:13 -0500 Message-Id: <1604016519-28065-8-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The majority of helpers are generated. Define the helper functions needed then include the generated file Signed-off-by: Taylor Simpson --- target/hexagon/helper.h | 85 ++++ target/hexagon/op_helper.c | 971 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 1056 insertions(+) create mode 100644 target/hexagon/helper.h create mode 100644 target/hexagon/op_helper.c diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h new file mode 100644 index 0000000..9246b28 --- /dev/null +++ b/target/hexagon/helper.h @@ -0,0 +1,85 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32) +DEF_HELPER_1(debug_start_packet, void, env) +DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, void, env, int, int) +DEF_HELPER_2(commit_store, void, env, int) +DEF_HELPER_FLAGS_3(debug_commit_end, TCG_CALL_NO_WG, void, env, int, int) +DEF_HELPER_4(fcircadd, s32, s32, s32, s32, s32) + +/* Floating point */ +DEF_HELPER_2(conv_sf2df, f64, env, f32) +DEF_HELPER_2(conv_df2sf, f32, env, f64) +DEF_HELPER_2(conv_uw2sf, f32, env, s32) +DEF_HELPER_2(conv_uw2df, f64, env, s32) +DEF_HELPER_2(conv_w2sf, f32, env, s32) +DEF_HELPER_2(conv_w2df, f64, env, s32) +DEF_HELPER_2(conv_ud2sf, f32, env, s64) +DEF_HELPER_2(conv_ud2df, f64, env, s64) +DEF_HELPER_2(conv_d2sf, f32, env, s64) +DEF_HELPER_2(conv_d2df, f64, env, s64) +DEF_HELPER_2(conv_sf2uw, s32, env, f32) +DEF_HELPER_2(conv_sf2w, s32, env, f32) +DEF_HELPER_2(conv_sf2ud, s64, env, f32) +DEF_HELPER_2(conv_sf2d, s64, env, f32) +DEF_HELPER_2(conv_df2uw, s32, env, f64) +DEF_HELPER_2(conv_df2w, s32, env, f64) +DEF_HELPER_2(conv_df2ud, s64, env, f64) +DEF_HELPER_2(conv_df2d, s64, env, f64) +DEF_HELPER_2(conv_sf2uw_chop, s32, env, f32) +DEF_HELPER_2(conv_sf2w_chop, s32, env, f32) +DEF_HELPER_2(conv_sf2ud_chop, s64, env, f32) +DEF_HELPER_2(conv_sf2d_chop, s64, env, f32) +DEF_HELPER_2(conv_df2uw_chop, s32, env, f64) +DEF_HELPER_2(conv_df2w_chop, s32, env, f64) +DEF_HELPER_2(conv_df2ud_chop, s64, env, f64) +DEF_HELPER_2(conv_df2d_chop, s64, env, f64) +DEF_HELPER_3(sfadd, f32, env, f32, f32) +DEF_HELPER_3(sfsub, f32, env, f32, f32) +DEF_HELPER_3(sfcmpeq, s32, env, f32, f32) +DEF_HELPER_3(sfcmpgt, s32, env, f32, f32) +DEF_HELPER_3(sfcmpge, s32, env, f32, f32) +DEF_HELPER_3(sfcmpuo, s32, env, f32, f32) +DEF_HELPER_3(sfmax, f32, env, f32, f32) +DEF_HELPER_3(sfmin, f32, env, f32, f32) +DEF_HELPER_3(sfclass, s32, env, f32, s32) +DEF_HELPER_3(sffixupn, f32, env, f32, f32) +DEF_HELPER_3(sffixupd, f32, env, f32, f32) +DEF_HELPER_2(sffixupr, f32, env, f32) + +DEF_HELPER_3(dfadd, f64, env, f64, f64) +DEF_HELPER_3(dfsub, f64, env, f64, f64) +DEF_HELPER_3(dfmax, f64, env, f64, f64) +DEF_HELPER_3(dfmin, f64, env, f64, f64) +DEF_HELPER_3(dfcmpeq, s32, env, f64, f64) +DEF_HELPER_3(dfcmpgt, s32, env, f64, f64) +DEF_HELPER_3(dfcmpge, s32, env, f64, f64) +DEF_HELPER_3(dfcmpuo, s32, env, f64, f64) +DEF_HELPER_3(dfclass, s32, env, f64, s32) + +DEF_HELPER_3(sfmpy, f32, env, f32, f32) +DEF_HELPER_4(sffma, f32, env, f32, f32, f32) +DEF_HELPER_5(sffma_sc, f32, env, f32, f32, f32, f32) +DEF_HELPER_4(sffms, f32, env, f32, f32, f32) +DEF_HELPER_4(sffma_lib, f32, env, f32, f32, f32) +DEF_HELPER_4(sffms_lib, f32, env, f32, f32, f32) + +DEF_HELPER_3(dfmpyfix, f64, env, f64, f64) +DEF_HELPER_4(dfmpyhh, f64, env, f64, f64, f64) + +#include "helper_protos_generated.h" diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c new file mode 100644 index 0000000..122a18d --- /dev/null +++ b/target/hexagon/op_helper.c @@ -0,0 +1,971 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "exec/helper-proto.h" +#include "fpu/softfloat.h" +#include "cpu.h" +#include "internal.h" +#include "macros.h" +#include "arch.h" +#include "hex_arch_types.h" +#include "fma_emu.h" +#include "conv_emu.h" + +#define SF_BIAS 127 +#define SF_MANTBITS 23 + +/* Exceptions processing helpers */ +static void QEMU_NORETURN do_raise_exception_err(CPUHexagonState *env, + uint32_t exception, + uintptr_t pc) +{ + CPUState *cs = CPU(hexagon_env_get_cpu(env)); + qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); + cs->exception_index = exception; + cpu_loop_exit_restore(cs, pc); +} + +void QEMU_NORETURN HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp) +{ + do_raise_exception_err(env, excp, 0); +} + +static inline void log_reg_write(CPUHexagonState *env, int rnum, + target_ulong val, uint32_t slot) +{ + HEX_DEBUG_LOG("log_reg_write[%d] = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")", + rnum, val, val); + if (env->slot_cancelled & (1 << slot)) { + HEX_DEBUG_LOG(" CANCELLED"); + } + if (val == env->gpr[rnum]) { + HEX_DEBUG_LOG(" NO CHANGE"); + } + HEX_DEBUG_LOG("\n"); + if (!(env->slot_cancelled & (1 << slot))) { + env->new_value[rnum] = val; +#if HEX_DEBUG + /* Do this so HELPER(debug_commit_end) will know */ + env->reg_written[rnum] = 1; +#endif + } +} + +static __attribute__((unused)) +inline void log_reg_write_pair(CPUHexagonState *env, int rnum, + int64_t val, uint32_t slot) +{ + HEX_DEBUG_LOG("log_reg_write_pair[%d:%d] = %ld\n", rnum + 1, rnum, val); + log_reg_write(env, rnum, val & 0xFFFFFFFF, slot); + log_reg_write(env, rnum + 1, (val >> 32) & 0xFFFFFFFF, slot); +} + +static inline void log_pred_write(CPUHexagonState *env, int pnum, + target_ulong val) +{ + HEX_DEBUG_LOG("log_pred_write[%d] = " TARGET_FMT_ld + " (0x" TARGET_FMT_lx ")\n", + pnum, val, val); + + /* Multiple writes to the same preg are and'ed together */ + if (env->pred_written & (1 << pnum)) { + env->new_pred_value[pnum] &= val & 0xff; + } else { + env->new_pred_value[pnum] = val & 0xff; + env->pred_written |= 1 << pnum; + } +} + +static inline void log_store32(CPUHexagonState *env, target_ulong addr, + target_ulong val, int width, int slot) +{ + HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", " TARGET_FMT_ld + " [0x" TARGET_FMT_lx "])\n", + width, addr, val, val); + env->mem_log_stores[slot].va = addr; + env->mem_log_stores[slot].width = width; + env->mem_log_stores[slot].data32 = val; +} + +static inline void log_store64(CPUHexagonState *env, target_ulong addr, + int64_t val, int width, int slot) +{ + HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %ld [0x%lx])\n", + width, addr, val, val); + env->mem_log_stores[slot].va = addr; + env->mem_log_stores[slot].width = width; + env->mem_log_stores[slot].data64 = val; +} + +static inline void write_new_pc(CPUHexagonState *env, target_ulong addr) +{ + HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr); + + /* + * If more than one branch is taken in a packet, only the first one + * is actually done. + */ + if (env->branch_taken) { + HEX_DEBUG_LOG("INFO: multiple branches taken in same packet, " + "ignoring the second one\n"); + } else { + fCHECK_PCALIGN(addr); + env->branch_taken = 1; + env->next_PC = addr; + } +} + +/* Handy place to set a breakpoint */ +void HELPER(debug_start_packet)(CPUHexagonState *env) +{ + HEX_DEBUG_LOG("Start packet: pc = 0x" TARGET_FMT_lx "\n", + env->gpr[HEX_REG_PC]); + + int i; + for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + env->reg_written[i] = 0; + } +} + +static inline int32_t new_pred_value(CPUHexagonState *env, int pnum) +{ + return env->new_pred_value[pnum]; +} + +/* Checks for bookkeeping errors between disassembly context and runtime */ +void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check) +{ + if (env->mem_log_stores[slot].width != check) { + HEX_DEBUG_LOG("ERROR: %d != %d\n", + env->mem_log_stores[slot].width, check); + g_assert_not_reached(); + } +} + +void HELPER(commit_store)(CPUHexagonState *env, int slot_num) +{ + switch (env->mem_log_stores[slot_num].width) { + case 1: + put_user_u8(env->mem_log_stores[slot_num].data32, + env->mem_log_stores[slot_num].va); + break; + case 2: + put_user_u16(env->mem_log_stores[slot_num].data32, + env->mem_log_stores[slot_num].va); + break; + case 4: + put_user_u32(env->mem_log_stores[slot_num].data32, + env->mem_log_stores[slot_num].va); + break; + case 8: + put_user_u64(env->mem_log_stores[slot_num].data64, + env->mem_log_stores[slot_num].va); + break; + default: + g_assert_not_reached(); + } +} + +static void print_store(CPUHexagonState *env, int slot) +{ + if (!(env->slot_cancelled & (1 << slot))) { + uint8_t width = env->mem_log_stores[slot].width; + if (width == 1) { + uint32_t data = env->mem_log_stores[slot].data32 & 0xff; + HEX_DEBUG_LOG("\tmemb[0x" TARGET_FMT_lx "] = %d (0x%02x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 2) { + uint32_t data = env->mem_log_stores[slot].data32 & 0xffff; + HEX_DEBUG_LOG("\tmemh[0x" TARGET_FMT_lx "] = %d (0x%04x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 4) { + uint32_t data = env->mem_log_stores[slot].data32; + HEX_DEBUG_LOG("\tmemw[0x" TARGET_FMT_lx "] = %d (0x%08x)\n", + env->mem_log_stores[slot].va, data, data); + } else if (width == 8) { + HEX_DEBUG_LOG("\tmemd[0x" TARGET_FMT_lx "] = %lu (0x%016lx)\n", + env->mem_log_stores[slot].va, + env->mem_log_stores[slot].data64, + env->mem_log_stores[slot].data64); + } else { + HEX_DEBUG_LOG("\tBad store width %d\n", width); + g_assert_not_reached(); + } + } +} + +/* This function is a handy place to set a breakpoint */ +void HELPER(debug_commit_end)(CPUHexagonState *env, int has_st0, int has_st1) +{ + bool reg_printed = false; + bool pred_printed = false; + int i; + + HEX_DEBUG_LOG("Packet committed: pc = 0x" TARGET_FMT_lx "\n", + env->this_PC); + HEX_DEBUG_LOG("slot_cancelled = %d\n", env->slot_cancelled); + + for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + if (env->reg_written[i]) { + if (!reg_printed) { + HEX_DEBUG_LOG("Regs written\n"); + reg_printed = true; + } + HEX_DEBUG_LOG("\tr%d = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")\n", + i, env->new_value[i], env->new_value[i]); + } + } + + for (i = 0; i < NUM_PREGS; i++) { + if (env->pred_written & (1 << i)) { + if (!pred_printed) { + HEX_DEBUG_LOG("Predicates written\n"); + pred_printed = true; + } + HEX_DEBUG_LOG("\tp%d = 0x" TARGET_FMT_lx "\n", + i, env->new_pred_value[i]); + } + } + + if (has_st0 || has_st1) { + HEX_DEBUG_LOG("Stores\n"); + if (has_st0) { + print_store(env, 0); + } + if (has_st1) { + print_store(env, 1); + } + } + + HEX_DEBUG_LOG("Next PC = 0x%x\n", env->next_PC); + HEX_DEBUG_LOG("Exec counters: pkt = " TARGET_FMT_lx + ", insn = " TARGET_FMT_lx + "\n", + env->gpr[HEX_REG_QEMU_PKT_CNT], + env->gpr[HEX_REG_QEMU_INSN_CNT]); + +} + +static int32_t fcircadd_v4(int32_t RxV, int32_t offset, int32_t M, int32_t CS) +{ + int32_t length = M & 0x0001ffff; + uint32_t new_ptr = RxV + offset; + uint32_t start_addr = CS; + uint32_t end_addr = start_addr + length; + + if (new_ptr >= end_addr) { + new_ptr -= length; + } else if (new_ptr < start_addr) { + new_ptr += length; + } + + return new_ptr; +} + +int32_t HELPER(fcircadd)(int32_t RxV, int32_t offset, int32_t M, int32_t CS) +{ + int32_t K_const = (M >> 24) & 0xf; + int32_t length = M & 0x1ffff; + int32_t mask = (1 << (K_const + 2)) - 1; + uint32_t new_ptr = RxV + offset; + uint32_t start_addr = RxV & (~mask); + uint32_t end_addr = start_addr | length; + + if (K_const == 0 && length >= 4) { + return fcircadd_v4(RxV, offset, M, CS); + } + + if (new_ptr >= end_addr) { + new_ptr -= length; + } else if (new_ptr < start_addr) { + new_ptr += length; + } + + return new_ptr; +} + +/* + * mem_noshuf + * Section 5.5 of the Hexagon V67 Programmer's Reference Manual + * + * If the load is in slot 0 and there is a store in slot1 (that + * wasn't cancelled), we have to do the store first. + */ +static void check_noshuf(CPUHexagonState *env, uint32_t slot) +{ + if (slot == 0 && env->pkt_has_store_s1 && + ((env->slot_cancelled & (1 << 1)) == 0)) { + HELPER(commit_store)(env, 1); + } +} + +static inline uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint8_t retval; + check_noshuf(env, slot); + get_user_u8(retval, vaddr); + return retval; +} + +static inline uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint16_t retval; + check_noshuf(env, slot); + get_user_u16(retval, vaddr); + return retval; +} + +static inline uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint32_t retval; + check_noshuf(env, slot); + get_user_u32(retval, vaddr); + return retval; +} + +static inline uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) +{ + uint64_t retval; + check_noshuf(env, slot); + get_user_u64(retval, vaddr); + return retval; +} + +/* Floating point */ +float64 HELPER(conv_sf2df)(CPUHexagonState *env, float32 RsV) +{ + arch_fpop_start(env); + float64 out_f64 = float32_to_float64(RsV, &env->fp_status); + if (float64_is_any_nan(out_f64)) { + out_f64 = make_float64(0xFFFFFFFFFFFFFFFFULL); + } + arch_fpop_end(env); + return out_f64; +} + +float32 HELPER(conv_df2sf)(CPUHexagonState *env, float64 RssV) +{ + arch_fpop_start(env); + float32 out_f32 = float64_to_float32(RssV, &env->fp_status); + arch_fpop_end(env); + return out_f32; +} + +float32 HELPER(conv_uw2sf)(CPUHexagonState *env, int32_t RsV) +{ + arch_fpop_start(env); + float32 RdV = uint32_to_float32(RsV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +float64 HELPER(conv_uw2df)(CPUHexagonState *env, int32_t RsV) +{ + arch_fpop_start(env); + float64 RddV = uint32_to_float64(RsV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +float32 HELPER(conv_w2sf)(CPUHexagonState *env, int32_t RsV) +{ + arch_fpop_start(env); + float32 RdV = int32_to_float32(RsV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +float64 HELPER(conv_w2df)(CPUHexagonState *env, int32_t RsV) +{ + arch_fpop_start(env); + float64 RddV = int32_to_float64(RsV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +float32 HELPER(conv_ud2sf)(CPUHexagonState *env, int64_t RssV) +{ + arch_fpop_start(env); + float32 RdV = uint64_to_float32(RssV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +float64 HELPER(conv_ud2df)(CPUHexagonState *env, int64_t RssV) +{ + arch_fpop_start(env); + float64 RddV = uint64_to_float64(RssV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +float32 HELPER(conv_d2sf)(CPUHexagonState *env, int64_t RssV) +{ + arch_fpop_start(env); + float32 RdV = int64_to_float32(RssV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +float64 HELPER(conv_d2df)(CPUHexagonState *env, int64_t RssV) +{ + arch_fpop_start(env); + float64 RddV = int64_to_float64(RssV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +int32_t HELPER(conv_sf2uw)(CPUHexagonState *env, float32 RsV) +{ + arch_fpop_start(env); + int32_t RdV = conv_sf_to_4u(RsV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +int32_t HELPER(conv_sf2w)(CPUHexagonState *env, float32 RsV) +{ + arch_fpop_start(env); + int32_t RdV = conv_sf_to_4s(RsV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +int64_t HELPER(conv_sf2ud)(CPUHexagonState *env, float32 RsV) +{ + arch_fpop_start(env); + int64_t RddV = conv_sf_to_8u(RsV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +int64_t HELPER(conv_sf2d)(CPUHexagonState *env, float32 RsV) +{ + arch_fpop_start(env); + int64_t RddV = conv_sf_to_8s(RsV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +int32_t HELPER(conv_df2uw)(CPUHexagonState *env, float64 RssV) +{ + arch_fpop_start(env); + int32_t RdV = conv_df_to_4u(RssV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +int32_t HELPER(conv_df2w)(CPUHexagonState *env, float64 RssV) +{ + arch_fpop_start(env); + int32_t RdV = conv_df_to_4s(RssV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +int64_t HELPER(conv_df2ud)(CPUHexagonState *env, float64 RssV) +{ + arch_fpop_start(env); + int64_t RddV = conv_df_to_8u(RssV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +int64_t HELPER(conv_df2d)(CPUHexagonState *env, float64 RssV) +{ + arch_fpop_start(env); + int64_t RddV = conv_df_to_8s(RssV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +int32_t HELPER(conv_sf2uw_chop)(CPUHexagonState *env, float32 RsV) +{ + arch_fpop_start(env); + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + int32_t RdV = conv_sf_to_4u(RsV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +int32_t HELPER(conv_sf2w_chop)(CPUHexagonState *env, float32 RsV) +{ + arch_fpop_start(env); + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + int32_t RdV = conv_sf_to_4s(RsV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +int64_t HELPER(conv_sf2ud_chop)(CPUHexagonState *env, float32 RsV) +{ + arch_fpop_start(env); + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + int64_t RddV = conv_sf_to_8u(RsV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +int64_t HELPER(conv_sf2d_chop)(CPUHexagonState *env, float32 RsV) +{ + arch_fpop_start(env); + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + int64_t RddV = conv_sf_to_8s(RsV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +int32_t HELPER(conv_df2uw_chop)(CPUHexagonState *env, float64 RssV) +{ + arch_fpop_start(env); + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + int32_t RdV = conv_df_to_4u(RssV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +int32_t HELPER(conv_df2w_chop)(CPUHexagonState *env, float64 RssV) +{ + arch_fpop_start(env); + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + int32_t RdV = conv_df_to_4s(RssV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +int64_t HELPER(conv_df2ud_chop)(CPUHexagonState *env, float64 RssV) +{ + arch_fpop_start(env); + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + int64_t RddV = conv_df_to_8u(RssV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +int64_t HELPER(conv_df2d_chop)(CPUHexagonState *env, float64 RssV) +{ + arch_fpop_start(env); + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + int64_t RddV = conv_df_to_8s(RssV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +float32 HELPER(sfadd)(CPUHexagonState *env, float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + float32 RdV = float32_add(RsV, RtV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +float32 HELPER(sfsub)(CPUHexagonState *env, float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + float32 RdV = float32_sub(RsV, RtV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +int32_t HELPER(sfcmpeq)(CPUHexagonState *env, float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + int32_t PdV = f8BITSOF(float32_eq(RsV, RtV, &env->fp_status)); + arch_fpop_end(env); + return PdV; +} + +int32_t HELPER(sfcmpgt)(CPUHexagonState *env, float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + int cmp = float32_compare(RsV, RtV, &env->fp_status); + int32_t PdV = f8BITSOF(cmp == float_relation_greater); + arch_fpop_end(env); + return PdV; +} + +int32_t HELPER(sfcmpge)(CPUHexagonState *env, float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + int cmp = float32_compare(RsV, RtV, &env->fp_status); + int32_t PdV = f8BITSOF(cmp == float_relation_greater || + cmp == float_relation_equal); + arch_fpop_end(env); + return PdV; +} + +int32_t HELPER(sfcmpuo)(CPUHexagonState *env, float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + int32_t PdV = f8BITSOF(float32_is_any_nan(RsV) || + float32_is_any_nan(RtV)); + arch_fpop_end(env); + return PdV; +} + +float32 HELPER(sfmax)(CPUHexagonState *env, float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + float32 RdV = float32_max(RsV, RtV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +float32 HELPER(sfmin)(CPUHexagonState *env, float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + float32 RdV = float32_min(RsV, RtV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +int32_t HELPER(sfclass)(CPUHexagonState *env, float32 RsV, int32_t uiV) +{ + arch_fpop_start(env); + int32_t PdV = 0; + if (fGETBIT(0, uiV) && float32_is_zero(RsV)) { + PdV = 0xff; + } + if (fGETBIT(1, uiV) && float32_is_normal(RsV)) { + PdV = 0xff; + } + if (fGETBIT(2, uiV) && float32_is_denormal(RsV)) { + PdV = 0xff; + } + if (fGETBIT(3, uiV) && float32_is_infinity(RsV)) { + PdV = 0xff; + } + if (fGETBIT(4, uiV) && float32_is_any_nan(RsV)) { + PdV = 0xff; + } + set_float_exception_flags(0, &env->fp_status); + arch_fpop_end(env); + return PdV; +} + +float32 HELPER(sffixupn)(CPUHexagonState *env, float32 RsV, float32 RtV) +{ + float32 RdV = 0; + arch_fpop_start(env); + int adjust; + arch_sf_recip_common(&RsV, &RtV, &RdV, &adjust, &env->fp_status); + RdV = RsV; + arch_fpop_end(env); + return RdV; +} + +float32 HELPER(sffixupd)(CPUHexagonState *env, float32 RsV, float32 RtV) +{ + float32 RdV = 0; + arch_fpop_start(env); + int adjust; + arch_sf_recip_common(&RsV, &RtV, &RdV, &adjust, &env->fp_status); + RdV = RtV; + arch_fpop_end(env); + return RdV; +} + +float32 HELPER(sffixupr)(CPUHexagonState *env, float32 RsV) +{ + float32 RdV = 0; + arch_fpop_start(env); + int adjust; + arch_sf_invsqrt_common(&RsV, &RdV, &adjust, &env->fp_status); + RdV = RsV; + arch_fpop_end(env); + return RdV; +} + +float64 HELPER(dfadd)(CPUHexagonState *env, float64 RssV, float64 RttV) +{ + arch_fpop_start(env); + float64 RddV = float64_add(RssV, RttV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +float64 HELPER(dfsub)(CPUHexagonState *env, float64 RssV, float64 RttV) +{ + arch_fpop_start(env); + float64 RddV = float64_sub(RssV, RttV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +float64 HELPER(dfmax)(CPUHexagonState *env, float64 RssV, float64 RttV) +{ + arch_fpop_start(env); + float64 RddV = float64_max(RssV, RttV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +float64 HELPER(dfmin)(CPUHexagonState *env, float64 RssV, float64 RttV) +{ + arch_fpop_start(env); + float64 RddV = float64_min(RssV, RttV, &env->fp_status); + arch_fpop_end(env); + return RddV; +} + +int32_t HELPER(dfcmpeq)(CPUHexagonState *env, float64 RssV, float64 RttV) +{ + arch_fpop_start(env); + int32_t PdV = f8BITSOF(float64_eq(RssV, RttV, &env->fp_status)); + arch_fpop_end(env); + return PdV; +} + +int32_t HELPER(dfcmpgt)(CPUHexagonState *env, float64 RssV, float64 RttV) +{ + arch_fpop_start(env); + int cmp = float64_compare(RssV, RttV, &env->fp_status); + int32_t PdV = f8BITSOF(cmp == float_relation_greater); + arch_fpop_end(env); + return PdV; +} + +int32_t HELPER(dfcmpge)(CPUHexagonState *env, float64 RssV, float64 RttV) +{ + arch_fpop_start(env); + int cmp = float64_compare(RssV, RttV, &env->fp_status); + int32_t PdV = f8BITSOF(cmp == float_relation_greater || + cmp == float_relation_equal); + arch_fpop_end(env); + return PdV; +} + +int32_t HELPER(dfcmpuo)(CPUHexagonState *env, float64 RssV, float64 RttV) +{ + arch_fpop_start(env); + int32_t PdV = f8BITSOF(float64_is_any_nan(RssV) || + float64_is_any_nan(RttV)); + arch_fpop_end(env); + return PdV; +} + +int32_t HELPER(dfclass)(CPUHexagonState *env, float64 RssV, int32_t uiV) +{ + arch_fpop_start(env); + int32_t PdV = 0; + if (fGETBIT(0, uiV) && float64_is_zero(RssV)) { + PdV = 0xff; + } + if (fGETBIT(1, uiV) && float64_is_normal(RssV)) { + PdV = 0xff; + } + if (fGETBIT(2, uiV) && float64_is_denormal(RssV)) { + PdV = 0xff; + } + if (fGETBIT(3, uiV) && float64_is_infinity(RssV)) { + PdV = 0xff; + } + if (fGETBIT(4, uiV) && float64_is_any_nan(RssV)) { + PdV = 0xff; + } + set_float_exception_flags(0, &env->fp_status); + arch_fpop_end(env); + return PdV; +} + +float32 HELPER(sfmpy)(CPUHexagonState *env, float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + float32 RdV = internal_mpyf(RsV, RtV, &env->fp_status); + arch_fpop_end(env); + return RdV; +} + +float32 HELPER(sffma)(CPUHexagonState *env, float32 RxV, + float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + RxV = internal_fmafx(RsV, RtV, RxV, 0, &env->fp_status); + arch_fpop_end(env); + return RxV; +} + +static bool isfinite(float32 x) +{ + return !float32_is_any_nan(x) && !float32_is_infinity(x); +} + +static bool is_zero_prod(float32 a, float32 b) +{ + return ((float32_is_zero(a) && isfinite(b)) || + (float32_is_zero(b) && isfinite(a))); +} + +static float32 check_nan(float32 dst, float32 x, float_status *fp_status) +{ + float32 ret = dst; + if (float32_is_any_nan(x)) { + if (extract32(x, 22, 1) == 0) { + float_raise(float_flag_invalid, fp_status); + } + ret = make_float32(0xffffffff); /* nan */ + } + return ret; +} + +float32 HELPER(sffma_sc)(CPUHexagonState *env, float32 RxV, + float32 RsV, float32 RtV, float32 PuV) +{ + arch_fpop_start(env); + size4s_t tmp; + RxV = check_nan(RxV, RxV, &env->fp_status); + RxV = check_nan(RxV, RsV, &env->fp_status); + RxV = check_nan(RxV, RtV, &env->fp_status); + tmp = internal_fmafx(RsV, RtV, RxV, fSXTN(8, 64, PuV), &env->fp_status); + if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { + RxV = tmp; + } + arch_fpop_end(env); + return RxV; +} + +float32 HELPER(sffms)(CPUHexagonState *env, float32 RxV, + float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + float32 neg_RsV = float32_sub(float32_zero, RsV, &env->fp_status); + RxV = internal_fmafx(neg_RsV, RtV, RxV, 0, &env->fp_status); + arch_fpop_end(env); + return RxV; +} + +static inline bool is_inf_prod(int32_t a, int32_t b) +{ + return (float32_is_infinity(a) && float32_is_infinity(b)) || + (float32_is_infinity(a) && isfinite(b) && !float32_is_zero(b)) || + (float32_is_infinity(b) && isfinite(a) && !float32_is_zero(a)); +} + +float32 HELPER(sffma_lib)(CPUHexagonState *env, float32 RxV, + float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + set_float_rounding_mode(float_round_nearest_even, &env->fp_status); + int infinp; + int infminusinf; + float32 tmp; + infminusinf = float32_is_infinity(RxV) && + is_inf_prod(RsV, RtV) && + (fGETBIT(31, RsV ^ RxV ^ RtV) != 0); + infinp = float32_is_infinity(RxV) || + float32_is_infinity(RtV) || + float32_is_infinity(RsV); + RxV = check_nan(RxV, RxV, &env->fp_status); + RxV = check_nan(RxV, RsV, &env->fp_status); + RxV = check_nan(RxV, RtV, &env->fp_status); + tmp = internal_fmafx(RsV, RtV, RxV, 0, &env->fp_status); + if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { + RxV = tmp; + } + set_float_exception_flags(0, &env->fp_status); + if (float32_is_infinity(RxV) && !infinp) { + RxV = RxV - 1; + } + if (infminusinf) { + RxV = 0; + } + arch_fpop_end(env); + return RxV; +} + +float32 HELPER(sffms_lib)(CPUHexagonState *env, float32 RxV, + float32 RsV, float32 RtV) +{ + arch_fpop_start(env); + set_float_rounding_mode(float_round_nearest_even, &env->fp_status); + int infinp; + int infminusinf; + float32 tmp; + infminusinf = float32_is_infinity(RxV) && + is_inf_prod(RsV, RtV) && + (fGETBIT(31, RsV ^ RxV ^ RtV) == 0); + infinp = float32_is_infinity(RxV) || + float32_is_infinity(RtV) || + float32_is_infinity(RsV); + RxV = check_nan(RxV, RxV, &env->fp_status); + RxV = check_nan(RxV, RsV, &env->fp_status); + RxV = check_nan(RxV, RtV, &env->fp_status); + float32 minus_RsV = float32_sub(float32_zero, RsV, &env->fp_status); + tmp = internal_fmafx(minus_RsV, RtV, RxV, 0, &env->fp_status); + if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { + RxV = tmp; + } + set_float_exception_flags(0, &env->fp_status); + if (float32_is_infinity(RxV) && !infinp) { + RxV = RxV - 1; + } + if (infminusinf) { + RxV = 0; + } + arch_fpop_end(env); + return RxV; +} + +float64 HELPER(dfmpyfix)(CPUHexagonState *env, float64 RssV, float64 RttV) +{ + int64_t RddV; + if (float64_is_denormal(RssV) && + (float64_getexp(RttV) >= 512) && + float64_is_normal(RttV)) { + RddV = float64_mul(RssV, make_float64(0x4330000000000000), + &env->fp_status); + } else if (float64_is_denormal(RttV) && + (float64_getexp(RssV) >= 512) && + float64_is_normal(RssV)) { + RddV = float64_mul(RssV, make_float64(0x3cb0000000000000), + &env->fp_status); + } else { + RddV = RssV; + } + arch_fpop_end(env); + return RddV; +} + +float64 HELPER(dfmpyhh)(CPUHexagonState *env, float64 RxxV, + float64 RssV, float64 RttV) +{ + arch_fpop_start(env); + RxxV = internal_mpyhh(RssV, RttV, RxxV, &env->fp_status); + arch_fpop_end(env); + return RxxV; +} + +static void cancel_slot(CPUHexagonState *env, uint32_t slot) +{ + HEX_DEBUG_LOG("Slot %d cancelled\n", slot); + env->slot_cancelled |= (1 << slot); +} + +/* These macros can be referenced in the generated helper functions */ +#define warn(...) /* Nothing */ +#define fatal(...) g_assert_not_reached(); + +#define BOGUS_HELPER(tag) \ + printf("ERROR: bogus helper: " #tag "\n") + +#include "helper_funcs_generated.h" From patchwork Fri Oct 30 00:08:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFA22C2D0A3 for ; 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29 Oct 2020 17:08:44 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 04E2C411E; Thu, 29 Oct 2020 19:08:44 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 11/33] Hexagon (target/hexagon) register fields Date: Thu, 29 Oct 2020 19:08:17 -0500 Message-Id: <1604016519-28065-12-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Declare bitfields within registers such as user status register (USR) Signed-off-by: Taylor Simpson --- target/hexagon/reg_fields.h | 36 ++++++++++++++++++++++++++++++++++++ target/hexagon/reg_fields_def.h | 41 +++++++++++++++++++++++++++++++++++++++++ target/hexagon/reg_fields.c | 27 +++++++++++++++++++++++++++ 3 files changed, 104 insertions(+) create mode 100644 target/hexagon/reg_fields.h create mode 100644 target/hexagon/reg_fields_def.h create mode 100644 target/hexagon/reg_fields.c diff --git a/target/hexagon/reg_fields.h b/target/hexagon/reg_fields.h new file mode 100644 index 0000000..4ec7d7c --- /dev/null +++ b/target/hexagon/reg_fields.h @@ -0,0 +1,36 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_REG_FIELDS_H +#define HEXAGON_REG_FIELDS_H + +typedef struct { + int offset; + int width; +} RegField; + +extern const RegField reg_field_info[]; + +enum { +#define DEF_REG_FIELD(TAG, START, WIDTH) \ + TAG, +#include "reg_fields_def.h" + NUM_REG_FIELDS +#undef DEF_REG_FIELD +}; + +#endif diff --git a/target/hexagon/reg_fields_def.h b/target/hexagon/reg_fields_def.h new file mode 100644 index 0000000..27b2231 --- /dev/null +++ b/target/hexagon/reg_fields_def.h @@ -0,0 +1,41 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * For registers that have individual fields, explain them here + * DEF_REG_FIELD(tag, + * bit start offset, + * width + */ + +/* USR fields */ +DEF_REG_FIELD(USR_OVF, 0, 1) +DEF_REG_FIELD(USR_FPINVF, 1, 1) +DEF_REG_FIELD(USR_FPDBZF, 2, 1) +DEF_REG_FIELD(USR_FPOVFF, 3, 1) +DEF_REG_FIELD(USR_FPUNFF, 4, 1) +DEF_REG_FIELD(USR_FPINPF, 5, 1) + +DEF_REG_FIELD(USR_LPCFG, 8, 2) + +DEF_REG_FIELD(USR_FPRND, 22, 2) + +DEF_REG_FIELD(USR_FPINVE, 25, 1) +DEF_REG_FIELD(USR_FPDBZE, 26, 1) +DEF_REG_FIELD(USR_FPOVFE, 27, 1) +DEF_REG_FIELD(USR_FPUNFE, 28, 1) +DEF_REG_FIELD(USR_FPINPE, 29, 1) diff --git a/target/hexagon/reg_fields.c b/target/hexagon/reg_fields.c new file mode 100644 index 0000000..65905d5 --- /dev/null +++ b/target/hexagon/reg_fields.c @@ -0,0 +1,27 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "reg_fields.h" + +const RegField reg_field_info[] = { +#define DEF_REG_FIELD(TAG, START, WIDTH) \ + { START, WIDTH }, +#include "reg_fields_def.h" + { 0, 0 } +#undef DEF_REG_FIELD +}; From patchwork Fri Oct 30 00:08:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81C8FC2D0A3 for ; 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29 Oct 2020 17:08:44 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 43E914125; Thu, 29 Oct 2020 19:08:44 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 13/33] Hexagon (target/hexagon) instruction/packet decode Date: Thu, 29 Oct 2020 19:08:19 -0500 Message-Id: <1604016519-28065-14-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Take the words from instruction memory and build a packet_t for TCG code generation The following operations are performed Convert the .new encoded offset to the register number of the producer Reorder the packet so .new producer is before consumer Apply constant extenders Separate subinsn's into two instructions Break compare-jumps into two instructions Create instructions for :endloop Signed-off-by: Taylor Simpson --- target/hexagon/decode.h | 32 +++ target/hexagon/decode.c | 581 ++++++++++++++++++++++++++++++++++++++++++++ target/hexagon/q6v_decode.c | 385 +++++++++++++++++++++++++++++ 3 files changed, 998 insertions(+) create mode 100644 target/hexagon/decode.h create mode 100644 target/hexagon/decode.c create mode 100644 target/hexagon/q6v_decode.c diff --git a/target/hexagon/decode.h b/target/hexagon/decode.h new file mode 100644 index 0000000..38f597c --- /dev/null +++ b/target/hexagon/decode.h @@ -0,0 +1,32 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_DECODE_H +#define HEXAGON_DECODE_H + +#include "cpu.h" +#include "opcodes.h" +#include "insn.h" + +extern void decode_init(void); + +extern void decode_send_insn_to(Packet *packet, int start, int newloc); + +extern int decode_packet(int max_words, const uint32_t *words, Packet *pkt, + bool disas_only); + +#endif diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c new file mode 100644 index 0000000..26c661c --- /dev/null +++ b/target/hexagon/decode.c @@ -0,0 +1,581 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "iclass.h" +#include "opcodes.h" +#include "genptr.h" +#include "decode.h" +#include "insn.h" +#include "printinsn.h" + +#define fZXTN(N, M, VAL) ((VAL) & ((1LL << (N)) - 1)) + +enum { + EXT_IDX_noext = 0, + EXT_IDX_noext_AFTER = 4, + EXT_IDX_mmvec = 4, + EXT_IDX_mmvec_AFTER = 8, + XX_LAST_EXT_IDX +}; + +/* + * Certain operand types represent a non-contiguous set of values. + * For example, the compound compare-and-jump instruction can only access + * registers R0-R7 and R16-23. + * This table represents the mapping from the encoding to the actual values. + */ + +#define DEF_REGMAP(NAME, ELEMENTS, ...) \ + static const unsigned int DECODE_REGISTER_##NAME[ELEMENTS] = \ + { __VA_ARGS__ }; + /* Name Num Table */ +DEF_REGMAP(R_16, 16, 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23) +DEF_REGMAP(R__8, 8, 0, 2, 4, 6, 16, 18, 20, 22) + +#define DECODE_MAPPED_REG(REGNO, NAME) \ + insn->regno[REGNO] = DECODE_REGISTER_##NAME[insn->regno[REGNO]]; + +typedef struct { + const struct DectreeTable *table_link; + const struct DectreeTable *table_link_b; + Opcode opcode; + enum { + DECTREE_ENTRY_INVALID, + DECTREE_TABLE_LINK, + DECTREE_SUBINSNS, + DECTREE_EXTSPACE, + DECTREE_TERMINAL + } type; +} DectreeEntry; + +typedef struct DectreeTable { + unsigned int (*lookup_function)(int startbit, int width, uint32_t opcode); + unsigned int size; + unsigned int startbit; + unsigned int width; + const DectreeEntry table[]; +} DectreeTable; + +#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) \ + static const DectreeTable dectree_table_##TAG; +#define TABLE_LINK(TABLE) /* NOTHING */ +#define TERMINAL(TAG, ENC) /* NOTHING */ +#define SUBINSNS(TAG, CLASSA, CLASSB, ENC) /* NOTHING */ +#define EXTSPACE(TAG, ENC) /* NOTHING */ +#define INVALID() /* NOTHING */ +#define DECODE_END_TABLE(...) /* NOTHING */ +#define DECODE_MATCH_INFO(...) /* NOTHING */ +#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */ +#define DECODE_OPINFO(...) /* NOTHING */ + +#include "dectree_generated.h" + +#undef DECODE_OPINFO +#undef DECODE_MATCH_INFO +#undef DECODE_LEGACY_MATCH_INFO +#undef DECODE_END_TABLE +#undef INVALID +#undef TERMINAL +#undef SUBINSNS +#undef EXTSPACE +#undef TABLE_LINK +#undef DECODE_NEW_TABLE +#undef DECODE_SEPARATOR_BITS + +#define DECODE_SEPARATOR_BITS(START, WIDTH) NULL, START, WIDTH +#define DECODE_NEW_TABLE_HELPER(TAG, SIZE, FN, START, WIDTH) \ + static const DectreeTable dectree_table_##TAG = { \ + .size = SIZE, \ + .lookup_function = FN, \ + .startbit = START, \ + .width = WIDTH, \ + .table = { +#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) \ + DECODE_NEW_TABLE_HELPER(TAG, SIZE, WHATNOT) + +#define TABLE_LINK(TABLE) \ + { .type = DECTREE_TABLE_LINK, .table_link = &dectree_table_##TABLE }, +#define TERMINAL(TAG, ENC) \ + { .type = DECTREE_TERMINAL, .opcode = TAG }, +#define SUBINSNS(TAG, CLASSA, CLASSB, ENC) \ + { \ + .type = DECTREE_SUBINSNS, \ + .table_link = &dectree_table_DECODE_SUBINSN_##CLASSA, \ + .table_link_b = &dectree_table_DECODE_SUBINSN_##CLASSB \ + }, +#define EXTSPACE(TAG, ENC) { .type = DECTREE_EXTSPACE }, +#define INVALID() { .type = DECTREE_ENTRY_INVALID, .opcode = XX_LAST_OPCODE }, + +#define DECODE_END_TABLE(...) } }; + +#define DECODE_MATCH_INFO(...) /* NOTHING */ +#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */ +#define DECODE_OPINFO(...) /* NOTHING */ + +#include "dectree_generated.h" + +#undef DECODE_OPINFO +#undef DECODE_MATCH_INFO +#undef DECODE_LEGACY_MATCH_INFO +#undef DECODE_END_TABLE +#undef INVALID +#undef TERMINAL +#undef SUBINSNS +#undef EXTSPACE +#undef TABLE_LINK +#undef DECODE_NEW_TABLE +#undef DECODE_NEW_TABLE_HELPER +#undef DECODE_SEPARATOR_BITS + +static const DectreeTable dectree_table_DECODE_EXT_EXT_noext = { + .size = 1, .lookup_function = NULL, .startbit = 0, .width = 0, + .table = { + { .type = DECTREE_ENTRY_INVALID, .opcode = XX_LAST_OPCODE }, + } +}; + +static const DectreeTable *ext_trees[XX_LAST_EXT_IDX]; + +static void decode_ext_init(void) +{ + int i; + for (i = EXT_IDX_noext; i < EXT_IDX_noext_AFTER; i++) { + ext_trees[i] = &dectree_table_DECODE_EXT_EXT_noext; + } +} + +typedef struct { + uint32_t mask; + uint32_t match; +} DecodeITableEntry; + +#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) /* NOTHING */ +#define TABLE_LINK(TABLE) /* NOTHING */ +#define TERMINAL(TAG, ENC) /* NOTHING */ +#define SUBINSNS(TAG, CLASSA, CLASSB, ENC) /* NOTHING */ +#define EXTSPACE(TAG, ENC) /* NOTHING */ +#define INVALID() /* NOTHING */ +#define DECODE_END_TABLE(...) /* NOTHING */ +#define DECODE_OPINFO(...) /* NOTHING */ + +#define DECODE_MATCH_INFO_NORMAL(TAG, MASK, MATCH) \ + [TAG] = { \ + .mask = MASK, \ + .match = MATCH, \ + }, + +#define DECODE_MATCH_INFO_NULL(TAG, MASK, MATCH) \ + [TAG] = { .match = ~0 }, + +#define DECODE_MATCH_INFO(...) DECODE_MATCH_INFO_NORMAL(__VA_ARGS__) +#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */ + +static const DecodeITableEntry decode_itable[XX_LAST_OPCODE] = { +#include "dectree_generated.h" +}; + +#undef DECODE_MATCH_INFO +#define DECODE_MATCH_INFO(...) DECODE_MATCH_INFO_NULL(__VA_ARGS__) + +#undef DECODE_LEGACY_MATCH_INFO +#define DECODE_LEGACY_MATCH_INFO(...) DECODE_MATCH_INFO_NORMAL(__VA_ARGS__) + +static const DecodeITableEntry decode_legacy_itable[XX_LAST_OPCODE] = { +#include "dectree_generated.h" +}; + +#undef DECODE_OPINFO +#undef DECODE_MATCH_INFO +#undef DECODE_LEGACY_MATCH_INFO +#undef DECODE_END_TABLE +#undef INVALID +#undef TERMINAL +#undef SUBINSNS +#undef EXTSPACE +#undef TABLE_LINK +#undef DECODE_NEW_TABLE +#undef DECODE_SEPARATOR_BITS + +void decode_init(void) +{ + decode_ext_init(); +} + +void decode_send_insn_to(Packet *packet, int start, int newloc) +{ + Insn tmpinsn; + int direction; + int i; + if (start == newloc) { + return; + } + if (start < newloc) { + /* Move towards end */ + direction = 1; + } else { + /* move towards beginning */ + direction = -1; + } + for (i = start; i != newloc; i += direction) { + tmpinsn = packet->insn[i]; + packet->insn[i] = packet->insn[i + direction]; + packet->insn[i + direction] = tmpinsn; + } +} + +/* Fill newvalue registers with the correct regno */ +static void +decode_fill_newvalue_regno(Packet *packet) +{ + int i, use_regidx, def_idx; + uint16_t def_opcode, use_opcode; + char *dststr; + + for (i = 1; i < packet->num_insns; i++) { + if (GET_ATTRIB(packet->insn[i].opcode, A_DOTNEWVALUE) && + !GET_ATTRIB(packet->insn[i].opcode, A_EXTENSION)) { + use_opcode = packet->insn[i].opcode; + + /* It's a store, so we're adjusting the Nt field */ + if (GET_ATTRIB(use_opcode, A_STORE)) { + use_regidx = strchr(opcode_reginfo[use_opcode], 't') - + opcode_reginfo[use_opcode]; + } else { /* It's a Jump, so we're adjusting the Ns field */ + use_regidx = strchr(opcode_reginfo[use_opcode], 's') - + opcode_reginfo[use_opcode]; + } + + /* + * What's encoded at the N-field is the offset to who's producing + * the value. Shift off the LSB which indicates odd/even register. + */ + def_idx = i - ((packet->insn[i].regno[use_regidx]) >> 1); + + /* + * Check for a badly encoded N-field which points to an instruction + * out-of-range + */ + g_assert(!((def_idx < 0) || (def_idx > (packet->num_insns - 1)))); + + /* + * packet->insn[def_idx] is the producer + * Figure out which type of destination it produces + * and the corresponding index in the reginfo + */ + def_opcode = packet->insn[def_idx].opcode; + dststr = strstr(opcode_wregs[def_opcode], "Rd"); + if (dststr) { + dststr = strchr(opcode_reginfo[def_opcode], 'd'); + } else { + dststr = strstr(opcode_wregs[def_opcode], "Rx"); + if (dststr) { + dststr = strchr(opcode_reginfo[def_opcode], 'x'); + } else { + dststr = strstr(opcode_wregs[def_opcode], "Re"); + if (dststr) { + dststr = strchr(opcode_reginfo[def_opcode], 'e'); + } else { + dststr = strstr(opcode_wregs[def_opcode], "Ry"); + if (dststr) { + dststr = strchr(opcode_reginfo[def_opcode], 'y'); + } else { + g_assert_not_reached(); + } + } + } + } + g_assert(dststr != NULL); + + /* Now patch up the consumer with the register number */ + int dst_idx = dststr - opcode_reginfo[def_opcode]; + packet->insn[i].regno[use_regidx] = + packet->insn[def_idx].regno[dst_idx]; + /* + * We need to remember who produces this value to later + * check if it was dynamically cancelled + */ + packet->insn[i].new_value_producer_slot = + packet->insn[def_idx].slot; + } + } +} + +/* Split CJ into a compare and a jump */ +static void decode_split_cmpjump(Packet *pkt) +{ + int last, i; + int numinsns = pkt->num_insns; + + /* + * First, split all compare-jumps. + * The compare is sent to the end as a new instruction. + * Do it this way so we don't reorder dual jumps. Those need to stay in + * original order. + */ + for (i = 0; i < numinsns; i++) { + /* It's a cmp-jump */ + if (GET_ATTRIB(pkt->insn[i].opcode, A_NEWCMPJUMP)) { + last = pkt->num_insns; + pkt->insn[last] = pkt->insn[i]; /* copy the instruction */ + pkt->insn[last].part1 = 1; /* last instruction does the CMP */ + pkt->insn[i].part1 = 0; /* existing instruction does the JUMP */ + pkt->num_insns++; + } + } + + /* Now re-shuffle all the compares back to the beginning */ + for (i = 0; i < pkt->num_insns; i++) { + if (pkt->insn[i].part1) { + decode_send_insn_to(pkt, i, 0); + } + } +} + +static inline int decode_opcode_can_jump(int opcode) +{ + if ((GET_ATTRIB(opcode, A_JUMP)) || + (GET_ATTRIB(opcode, A_CALL)) || + (opcode == J2_trap0)) { + /* Exception to A_JUMP attribute */ + if (opcode == J4_hintjumpr) { + return 0; + } + return 1; + } + + return 0; +} + +static inline int decode_opcode_ends_loop(int opcode) +{ + return GET_ATTRIB(opcode, A_HWLOOP0_END) || + GET_ATTRIB(opcode, A_HWLOOP1_END); +} + +/* Set the is_* fields in each instruction */ +static void decode_set_insn_attr_fields(Packet *pkt) +{ + int i; + int numinsns = pkt->num_insns; + uint16_t opcode; + + pkt->pkt_has_cof = 0; + pkt->pkt_has_endloop = 0; + pkt->pkt_has_dczeroa = 0; + + for (i = 0; i < numinsns; i++) { + opcode = pkt->insn[i].opcode; + if (pkt->insn[i].part1) { + continue; /* Skip compare of cmp-jumps */ + } + + if (GET_ATTRIB(opcode, A_DCZEROA)) { + pkt->pkt_has_dczeroa = 1; + } + + if (GET_ATTRIB(opcode, A_STORE)) { + if (pkt->insn[i].slot == 0) { + pkt->pkt_has_store_s0 = 1; + } else { + pkt->pkt_has_store_s1 = 1; + } + } + + pkt->pkt_has_cof |= decode_opcode_can_jump(opcode); + + pkt->insn[i].is_endloop = decode_opcode_ends_loop(opcode); + + pkt->pkt_has_endloop |= pkt->insn[i].is_endloop; + + pkt->pkt_has_cof |= pkt->pkt_has_endloop; + } +} + +/* + * Shuffle for execution + * Move stores to end (in same order as encoding) + * Move compares to beginning (for use by .new insns) + */ +static void decode_shuffle_for_execution(Packet *packet) +{ + int changed = 0; + int i; + int flag; /* flag means we've seen a non-memory instruction */ + int n_mems; + int last_insn = packet->num_insns - 1; + + /* + * Skip end loops, somehow an end loop is getting in and messing + * up the order + */ + if (decode_opcode_ends_loop(packet->insn[last_insn].opcode)) { + last_insn--; + } + + do { + changed = 0; + /* + * Stores go last, must not reorder. + * Cannot shuffle stores past loads, either. + * Iterate backwards. If we see a non-memory instruction, + * then a store, shuffle the store to the front. Don't shuffle + * stores wrt each other or a load. + */ + for (flag = n_mems = 0, i = last_insn; i >= 0; i--) { + int opcode = packet->insn[i].opcode; + + if (flag && GET_ATTRIB(opcode, A_STORE)) { + decode_send_insn_to(packet, i, last_insn - n_mems); + n_mems++; + changed = 1; + } else if (GET_ATTRIB(opcode, A_STORE)) { + n_mems++; + } else if (GET_ATTRIB(opcode, A_LOAD)) { + /* + * Don't set flag, since we don't want to shuffle a + * store past a load + */ + n_mems++; + } else if (GET_ATTRIB(opcode, A_DOTNEWVALUE)) { + /* + * Don't set flag, since we don't want to shuffle past + * a .new value + */ + } else { + flag = 1; + } + } + + if (changed) { + continue; + } + /* Compares go first, may be reordered wrt each other */ + for (flag = 0, i = 0; i < last_insn + 1; i++) { + int opcode = packet->insn[i].opcode; + + if ((strstr(opcode_wregs[opcode], "Pd4") || + strstr(opcode_wregs[opcode], "Pe4")) && + GET_ATTRIB(opcode, A_STORE) == 0) { + /* This should be a compare (not a store conditional) */ + if (flag) { + decode_send_insn_to(packet, i, 0); + changed = 1; + continue; + } + } else if (GET_ATTRIB(opcode, A_IMPLICIT_WRITES_P3) && + !decode_opcode_ends_loop(packet->insn[i].opcode)) { + /* + * spNloop instruction + * Don't reorder endloops; they are not valid for .new uses, + * and we want to match HW + */ + if (flag) { + decode_send_insn_to(packet, i, 0); + changed = 1; + continue; + } + } else if (GET_ATTRIB(opcode, A_IMPLICIT_WRITES_P0) && + !GET_ATTRIB(opcode, A_NEWCMPJUMP)) { + if (flag) { + decode_send_insn_to(packet, i, 0); + changed = 1; + continue; + } + } else { + flag = 1; + } + } + if (changed) { + continue; + } + } while (changed); + + /* + * If we have a .new register compare/branch, move that to the very + * very end, past stores + */ + for (i = 0; i < last_insn; i++) { + if (GET_ATTRIB(packet->insn[i].opcode, A_DOTNEWVALUE)) { + decode_send_insn_to(packet, i, last_insn); + break; + } + } +} + +static void +apply_extender(Packet *pkt, int i, uint32_t extender) +{ + int immed_num; + uint32_t base_immed; + + immed_num = opcode_which_immediate_is_extended(pkt->insn[i].opcode); + base_immed = pkt->insn[i].immed[immed_num]; + + pkt->insn[i].immed[immed_num] = extender | fZXTN(6, 32, base_immed); +} + +static void decode_apply_extenders(Packet *packet) +{ + int i; + for (i = 0; i < packet->num_insns; i++) { + if (GET_ATTRIB(packet->insn[i].opcode, A_IT_EXTENDER)) { + packet->insn[i + 1].extension_valid = 1; + apply_extender(packet, i + 1, packet->insn[i].immed[0]); + } + } +} + +static void decode_remove_extenders(Packet *packet) +{ + int i, j; + for (i = 0; i < packet->num_insns; i++) { + if (GET_ATTRIB(packet->insn[i].opcode, A_IT_EXTENDER)) { + /* Remove this one by moving the remaining instructions down */ + for (j = i; + (j < packet->num_insns - 1) && (j < INSTRUCTIONS_MAX - 1); + j++) { + packet->insn[j] = packet->insn[j + 1]; + } + packet->num_insns--; + } + } +} + +static SlotMask get_valid_slots(const Packet *pkt, unsigned int slot) +{ + return find_iclass_slots(pkt->insn[slot].opcode, + pkt->insn[slot].iclass); +} + +#include "q6v_decode.c" + +/* Used for "-d in_asm" logging */ +int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, + char *buf, int bufsize) +{ + Packet pkt; + + if (decode_packet(nwords, words, &pkt, true) > 0) { + snprint_a_pkt_disas(buf, bufsize, &pkt, words, pc); + return pkt.encod_pkt_size_in_bytes; + } else { + snprintf(buf, bufsize, ""); + return 0; + } +} diff --git a/target/hexagon/q6v_decode.c b/target/hexagon/q6v_decode.c new file mode 100644 index 0000000..106b836 --- /dev/null +++ b/target/hexagon/q6v_decode.c @@ -0,0 +1,385 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#define DECODE_NEW_TABLE(TAG, SIZE, WHATNOT) /* NOTHING */ +#define TABLE_LINK(TABLE) /* NOTHING */ +#define TERMINAL(TAG, ENC) /* NOTHING */ +#define SUBINSNS(TAG, CLASSA, CLASSB, ENC) /* NOTHING */ +#define EXTSPACE(TAG, ENC) /* NOTHING */ +#define INVALID() /* NOTHING */ +#define DECODE_END_TABLE(...) /* NOTHING */ +#define DECODE_MATCH_INFO(...) /* NOTHING */ +#define DECODE_LEGACY_MATCH_INFO(...) /* NOTHING */ + +#define DECODE_REG(REGNO, WIDTH, STARTBIT) \ + insn->regno[REGNO] = ((encoding >> STARTBIT) & ((1 << WIDTH) - 1)); + +#define DECODE_IMPL_REG(REGNO, VAL) \ + insn->regno[REGNO] = VAL; + +#define DECODE_IMM(IMMNO, WIDTH, STARTBIT, VALSTART) \ + insn->immed[IMMNO] |= (((encoding >> STARTBIT) & ((1 << WIDTH) - 1))) << \ + (VALSTART); + +#define DECODE_IMM_SXT(IMMNO, WIDTH) \ + insn->immed[IMMNO] = ((((int32_t)insn->immed[IMMNO]) << (32 - WIDTH)) >> \ + (32 - WIDTH)); + +#define DECODE_IMM_NEG(IMMNO, WIDTH) \ + insn->immed[IMMNO] = -insn->immed[IMMNO]; + +#define DECODE_IMM_SHIFT(IMMNO, SHAMT) \ + if ((!insn->extension_valid) || \ + (insn->which_extended != IMMNO)) { \ + insn->immed[IMMNO] <<= SHAMT; \ + } + +#define DECODE_OPINFO(TAG, BEH) \ + case TAG: \ + { BEH } \ + break; \ + +/* + * Fill in the operands of the instruction + * dectree_generated.h had a DECODE_OPINFO entry for each opcode + * For example, + * DECODE_OPINFO(A2_addi, + * DECODE_REG(0,5,0) + * DECODE_REG(1,5,16) + * DECODE_IMM(0,7,21,9) + * DECODE_IMM(0,9,5,0) + * DECODE_IMM_SXT(0,16) + * with the macros defined above, we'll fill in a switch statement + * where each case is an opcode tag. + */ +static void +decode_op(Insn *insn, Opcode tag, uint32_t encoding) +{ + insn->immed[0] = 0; + insn->immed[1] = 0; + insn->opcode = tag; + if (insn->extension_valid) { + insn->which_extended = opcode_which_immediate_is_extended(tag); + } + + switch (tag) { +#include "dectree_generated.h" + default: + break; + } + + insn->generate = opcode_genptr[tag]; + + insn->iclass = iclass_bits(encoding); +} + +#undef DECODE_REG +#undef DECODE_IMPL_REG +#undef DECODE_IMM +#undef DECODE_IMM_SHIFT +#undef DECODE_OPINFO +#undef DECODE_MATCH_INFO +#undef DECODE_LEGACY_MATCH_INFO +#undef DECODE_END_TABLE +#undef INVALID +#undef TERMINAL +#undef SUBINSNS +#undef EXTSPACE +#undef TABLE_LINK +#undef DECODE_NEW_TABLE +#undef DECODE_SEPARATOR_BITS + +static unsigned int +decode_subinsn_tablewalk(Insn *insn, const DectreeTable *table, + uint32_t encoding) +{ + unsigned int i; + Opcode opc; + if (table->lookup_function) { + i = table->lookup_function(table->startbit, table->width, encoding); + } else { + i = extract32(encoding, table->startbit, table->width); + } + if (table->table[i].type == DECTREE_TABLE_LINK) { + return decode_subinsn_tablewalk(insn, table->table[i].table_link, + encoding); + } else if (table->table[i].type == DECTREE_TERMINAL) { + opc = table->table[i].opcode; + if ((encoding & decode_itable[opc].mask) != decode_itable[opc].match) { + return 0; + } + decode_op(insn, opc, encoding); + return 1; + } else { + return 0; + } +} + +static unsigned int get_insn_a(uint32_t encoding) +{ + return extract32(encoding, 0, 13); +} + +static unsigned int get_insn_b(uint32_t encoding) +{ + return extract32(encoding, 16, 13); +} + +static unsigned int +decode_insns_tablewalk(Insn *insn, const DectreeTable *table, + uint32_t encoding) +{ + unsigned int i; + unsigned int a, b; + Opcode opc; + if (table->lookup_function) { + i = table->lookup_function(table->startbit, table->width, encoding); + } else { + i = extract32(encoding, table->startbit, table->width); + } + if (table->table[i].type == DECTREE_TABLE_LINK) { + return decode_insns_tablewalk(insn, table->table[i].table_link, + encoding); + } else if (table->table[i].type == DECTREE_SUBINSNS) { + a = get_insn_a(encoding); + b = get_insn_b(encoding); + b = decode_subinsn_tablewalk(insn, table->table[i].table_link_b, b); + a = decode_subinsn_tablewalk(insn + 1, table->table[i].table_link, a); + if ((a == 0) || (b == 0)) { + return 0; + } + return 2; + } else if (table->table[i].type == DECTREE_TERMINAL) { + opc = table->table[i].opcode; + if ((encoding & decode_itable[opc].mask) != decode_itable[opc].match) { + if ((encoding & decode_legacy_itable[opc].mask) != + decode_legacy_itable[opc].match) { + return 0; + } + } + decode_op(insn, opc, encoding); + return 1; + } else { + return 0; + } +} + +static unsigned int +decode_insns(Insn *insn, uint32_t encoding) +{ + const DectreeTable *table; + if (parse_bits(encoding) != 0) { + /* Start with PP table - 32 bit instructions */ + table = &dectree_table_DECODE_ROOT_32; + } else { + /* start with EE table - duplex instructions */ + table = &dectree_table_DECODE_ROOT_EE; + } + return decode_insns_tablewalk(insn, table, encoding); +} + +static void decode_add_endloop_insn(Insn *insn, int loopnum) +{ + if (loopnum == 10) { + insn->opcode = J2_endloop01; + insn->generate = opcode_genptr[J2_endloop01]; + } else if (loopnum == 1) { + insn->opcode = J2_endloop1; + insn->generate = opcode_genptr[J2_endloop1]; + } else if (loopnum == 0) { + insn->opcode = J2_endloop0; + insn->generate = opcode_genptr[J2_endloop0]; + } else { + g_assert_not_reached(); + } +} + +static inline int decode_parsebits_is_loopend(uint32_t encoding32) +{ + uint32_t bits = parse_bits(encoding32); + return bits == 0x2; +} + +static void +decode_set_slot_number(Packet *pkt) +{ + int slot; + int i; + int hit_mem_insn = 0; + int hit_duplex = 0; + + /* + * The slots are encoded in reverse order + * For each instruction, count down until you find a suitable slot + */ + for (i = 0, slot = 3; i < pkt->num_insns; i++) { + SlotMask valid_slots = get_valid_slots(pkt, i); + + while (!(valid_slots & (1 << slot))) { + slot--; + } + pkt->insn[i].slot = slot; + if (slot) { + /* I've assigned the slot, now decrement it for the next insn */ + slot--; + } + } + + /* Fix the exceptions - mem insns to slot 0,1 */ + for (i = pkt->num_insns - 1; i >= 0; i--) { + /* First memory instruction always goes to slot 0 */ + if ((GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE) || + GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE_PACKET_RULES)) && + !hit_mem_insn) { + hit_mem_insn = 1; + pkt->insn[i].slot = 0; + continue; + } + + /* Next memory instruction always goes to slot 1 */ + if ((GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE) || + GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE_PACKET_RULES)) && + hit_mem_insn) { + pkt->insn[i].slot = 1; + } + } + + /* Fix the exceptions - duplex always slot 0,1 */ + for (i = pkt->num_insns - 1; i >= 0; i--) { + /* First subinsn always goes to slot 0 */ + if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN) && !hit_duplex) { + hit_duplex = 1; + pkt->insn[i].slot = 0; + continue; + } + + /* Next subinsn always goes to slot 1 */ + if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN) && hit_duplex) { + pkt->insn[i].slot = 1; + } + } + + /* Fix the exceptions - slot 1 is never empty, always aligns to slot 0 */ + int slot0_found = 0; + int slot1_found = 0; + int slot1_iidx = 0; + for (i = pkt->num_insns - 1; i >= 0; i--) { + /* Is slot0 used? */ + if (pkt->insn[i].slot == 0) { + int is_endloop = (pkt->insn[i].opcode == J2_endloop01); + is_endloop |= (pkt->insn[i].opcode == J2_endloop0); + is_endloop |= (pkt->insn[i].opcode == J2_endloop1); + + /* + * Make sure it's not endloop since, we're overloading + * slot0 for endloop + */ + if (!is_endloop) { + slot0_found = 1; + } + } + /* Is slot1 used? */ + if (pkt->insn[i].slot == 1) { + slot1_found = 1; + slot1_iidx = i; + } + } + /* Is slot0 empty and slot1 used? */ + if ((slot0_found == 0) && (slot1_found == 1)) { + /* Then push it to slot0 */ + pkt->insn[slot1_iidx].slot = 0; + } +} + +/* + * decode_packet + * Decodes packet with given words + * Returns 0 on insufficient words, + * or number of words used on success + */ + +int decode_packet(int max_words, const uint32_t *words, Packet *pkt, + bool disas_only) +{ + int num_insns = 0; + int words_read = 0; + int end_of_packet = 0; + int new_insns = 0; + uint32_t encoding32; + + /* Initialize */ + memset(pkt, 0, sizeof(*pkt)); + /* Try to build packet */ + while (!end_of_packet && (words_read < max_words)) { + encoding32 = words[words_read]; + end_of_packet = is_packet_end(encoding32); + new_insns = decode_insns(&pkt->insn[num_insns], encoding32); + /* + * If we saw an extender, mark next word extended so immediate + * decode works + */ + if (pkt->insn[num_insns].opcode == A4_ext) { + pkt->insn[num_insns + 1].extension_valid = 1; + } + num_insns += new_insns; + words_read++; + } + + pkt->num_insns = num_insns; + if (!end_of_packet) { + /* Ran out of words! */ + return 0; + } + pkt->encod_pkt_size_in_bytes = words_read * 4; + + /* + * Check for :endloop in the parse bits + * Section 10.6 of the Programmer's Reference describes the encoding + * The end of hardware loop 0 can be encoded with 2 words + * The end of hardware loop 1 needs 3 words + */ + if ((words_read == 2) && (decode_parsebits_is_loopend(words[0]))) { + decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 0); + } + if (words_read >= 3) { + uint32_t has_loop0, has_loop1; + has_loop0 = decode_parsebits_is_loopend(words[0]); + has_loop1 = decode_parsebits_is_loopend(words[1]); + if (has_loop0 && has_loop1) { + decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 10); + } else if (has_loop1) { + decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 1); + } else if (has_loop0) { + decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 0); + } + } + + decode_apply_extenders(pkt); + if (!disas_only) { + decode_remove_extenders(pkt); + } + decode_set_slot_number(pkt); + decode_fill_newvalue_regno(pkt); + + if (!disas_only) { + decode_shuffle_for_execution(pkt); + decode_split_cmpjump(pkt); + decode_set_insn_attr_fields(pkt); + } + + return words_read; +} From patchwork Fri Oct 30 00:08:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8ACF6C2D0A3 for ; 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29 Oct 2020 17:08:44 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 78A114129; Thu, 29 Oct 2020 19:08:44 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 15/33] Hexagon (target/hexagon/arch.[ch]) utility functions Date: Thu, 29 Oct 2020 19:08:21 -0500 Message-Id: <1604016519-28065-16-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Taylor Simpson --- target/hexagon/arch.h | 35 ++++++ target/hexagon/arch.c | 294 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 329 insertions(+) create mode 100644 target/hexagon/arch.h create mode 100644 target/hexagon/arch.c diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h new file mode 100644 index 0000000..cf14480 --- /dev/null +++ b/target/hexagon/arch.h @@ -0,0 +1,35 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_ARCH_H +#define HEXAGON_ARCH_H + +#include "qemu/osdep.h" +#include "qemu/int128.h" + +extern uint64_t interleave(uint32_t odd, uint32_t even); +extern uint64_t deinterleave(uint64_t src); +extern uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c); +extern int32_t conv_round(int32_t a, int n); +extern void arch_fpop_start(CPUHexagonState *env); +extern void arch_fpop_end(CPUHexagonState *env); +extern int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, + int *adjust, float_status *fp_status); +extern int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust, + float_status *fp_status); + +#endif diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c new file mode 100644 index 0000000..16002bf --- /dev/null +++ b/target/hexagon/arch.c @@ -0,0 +1,294 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "fpu/softfloat.h" +#include "cpu.h" +#include "fma_emu.h" +#include "arch.h" +#include "macros.h" + +#define SF_BIAS 127 +#define SF_MAXEXP 254 +#define SF_MANTBITS 23 +#define float32_nan make_float32(0xffffffff) + +#define BITS_MASK_8 0x5555555555555555ULL +#define PAIR_MASK_8 0x3333333333333333ULL +#define NYBL_MASK_8 0x0f0f0f0f0f0f0f0fULL +#define BYTE_MASK_8 0x00ff00ff00ff00ffULL +#define HALF_MASK_8 0x0000ffff0000ffffULL +#define WORD_MASK_8 0x00000000ffffffffULL + +uint64_t interleave(uint32_t odd, uint32_t even) +{ + /* Convert to long long */ + uint64_t myodd = odd; + uint64_t myeven = even; + /* First, spread bits out */ + myodd = (myodd | (myodd << 16)) & HALF_MASK_8; + myeven = (myeven | (myeven << 16)) & HALF_MASK_8; + myodd = (myodd | (myodd << 8)) & BYTE_MASK_8; + myeven = (myeven | (myeven << 8)) & BYTE_MASK_8; + myodd = (myodd | (myodd << 4)) & NYBL_MASK_8; + myeven = (myeven | (myeven << 4)) & NYBL_MASK_8; + myodd = (myodd | (myodd << 2)) & PAIR_MASK_8; + myeven = (myeven | (myeven << 2)) & PAIR_MASK_8; + myodd = (myodd | (myodd << 1)) & BITS_MASK_8; + myeven = (myeven | (myeven << 1)) & BITS_MASK_8; + /* Now OR together */ + return myeven | (myodd << 1); +} + +uint64_t deinterleave(uint64_t src) +{ + /* Get odd and even bits */ + uint64_t myodd = ((src >> 1) & BITS_MASK_8); + uint64_t myeven = (src & BITS_MASK_8); + + /* Unspread bits */ + myeven = (myeven | (myeven >> 1)) & PAIR_MASK_8; + myodd = (myodd | (myodd >> 1)) & PAIR_MASK_8; + myeven = (myeven | (myeven >> 2)) & NYBL_MASK_8; + myodd = (myodd | (myodd >> 2)) & NYBL_MASK_8; + myeven = (myeven | (myeven >> 4)) & BYTE_MASK_8; + myodd = (myodd | (myodd >> 4)) & BYTE_MASK_8; + myeven = (myeven | (myeven >> 8)) & HALF_MASK_8; + myodd = (myodd | (myodd >> 8)) & HALF_MASK_8; + myeven = (myeven | (myeven >> 16)) & WORD_MASK_8; + myodd = (myodd | (myodd >> 16)) & WORD_MASK_8; + + /* Return odd bits in upper half */ + return myeven | (myodd << 32); +} + +uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c) +{ + uint64_t tmpa, tmpb, tmpc; + tmpa = fGETUWORD(0, a); + tmpb = fGETUWORD(0, b); + tmpc = tmpa + tmpb + c; + tmpa = fGETUWORD(1, a); + tmpb = fGETUWORD(1, b); + tmpc = tmpa + tmpb + fGETUWORD(1, tmpc); + tmpc = fGETUWORD(1, tmpc); + return tmpc; +} + +int32_t conv_round(int32_t a, int n) +{ + int64_t val; + + if (n == 0) { + val = a; + } else if ((a & ((1 << (n - 1)) - 1)) == 0) { /* N-1..0 all zero? */ + /* Add LSB from int part */ + val = ((fSE32_64(a)) + (int64_t) (((uint32_t) ((1 << n) & a)) >> 1)); + } else { + val = ((fSE32_64(a)) + (1 << (n - 1))); + } + + val = val >> n; + return (int32_t)val; +} + +/* Floating Point Stuff */ + +static const int softfloat_roundingmodes[] = { + float_round_nearest_even, + float_round_to_zero, + float_round_down, + float_round_up, +}; + +void arch_fpop_start(CPUHexagonState *env) +{ + set_float_exception_flags(0, &env->fp_status); + set_float_rounding_mode( + softfloat_roundingmodes[fREAD_REG_FIELD(USR, USR_FPRND)], + &env->fp_status); +} + +#define RAISE_FP_EXCEPTION \ + do {} while (0) /* Not modelled in qemu user mode */ + +#define SOFTFLOAT_TEST_FLAG(FLAG, MYF, MYE) \ + do { \ + if (flags & FLAG) { \ + if (GET_USR_FIELD(USR_##MYF) == 0) { \ + SET_USR_FIELD(USR_##MYF, 1); \ + if (GET_USR_FIELD(USR_##MYE)) { \ + RAISE_FP_EXCEPTION; \ + } \ + } \ + } \ + } while (0) + +void arch_fpop_end(CPUHexagonState *env) +{ + int flags = get_float_exception_flags(&env->fp_status); + if (flags != 0) { + SOFTFLOAT_TEST_FLAG(float_flag_inexact, FPINPF, FPINPE); + SOFTFLOAT_TEST_FLAG(float_flag_divbyzero, FPDBZF, FPDBZE); + SOFTFLOAT_TEST_FLAG(float_flag_invalid, FPINVF, FPINVE); + SOFTFLOAT_TEST_FLAG(float_flag_overflow, FPOVFF, FPOVFE); + SOFTFLOAT_TEST_FLAG(float_flag_underflow, FPUNFF, FPUNFE); + } +} + +static float32 float32_mul_pow2(float32 a, uint32_t p, float_status *fp_status) +{ + float32 b = make_float32((SF_BIAS + p) << SF_MANTBITS); + return float32_mul(a, b, fp_status); +} + +int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust, + float_status *fp_status) +{ + int n_exp; + int d_exp; + int ret = 0; + float32 RsV, RtV, RdV; + int PeV = 0; + RsV = *Rs; + RtV = *Rt; + if (float32_is_any_nan(RsV) && float32_is_any_nan(RtV)) { + if (extract32(RsV & RtV, 22, 1)) { + float_raise(float_flag_invalid, fp_status); + } + RdV = RsV = RtV = float32_nan; + } else if (float32_is_any_nan(RsV)) { + if (extract32(RsV, 22, 1)) { + float_raise(float_flag_invalid, fp_status); + } + RdV = RsV = RtV = float32_nan; + } else if (float32_is_any_nan(RtV)) { + /* or put NaN in num/den fixup? */ + if (extract32(RtV, 22, 1)) { + float_raise(float_flag_invalid, fp_status); + } + RdV = RsV = RtV = float32_nan; + } else if (float32_is_infinity(RsV) && float32_is_infinity(RtV)) { + /* or put Inf in num fixup? */ + RdV = RsV = RtV = float32_nan; + float_raise(float_flag_invalid, fp_status); + } else if (float32_is_zero(RsV) && float32_is_zero(RtV)) { + /* or put zero in num fixup? */ + RdV = RsV = RtV = float32_nan; + float_raise(float_flag_invalid, fp_status); + } else if (float32_is_zero(RtV)) { + /* or put Inf in num fixup? */ + uint8_t RsV_sign = float32_is_neg(RsV); + uint8_t RtV_sign = float32_is_neg(RtV); + RsV = infinite_float32(RsV_sign ^ RtV_sign); + RtV = float32_one; + RdV = float32_one; + if (float32_is_infinity(RsV)) { + float_raise(float_flag_divbyzero, fp_status); + } + } else if (float32_is_infinity(RtV)) { + RsV = make_float32(0x80000000 & (RsV ^ RtV)); + RtV = float32_one; + RdV = float32_one; + } else if (float32_is_zero(RsV)) { + /* Does this just work itself out? */ + /* No, 0/Inf causes problems. */ + RsV = make_float32(0x80000000 & (RsV ^ RtV)); + RtV = float32_one; + RdV = float32_one; + } else if (float32_is_infinity(RsV)) { + uint8_t RsV_sign = float32_is_neg(RsV); + uint8_t RtV_sign = float32_is_neg(RtV); + RsV = infinite_float32(RsV_sign ^ RtV_sign); + RtV = float32_one; + RdV = float32_one; + } else { + PeV = 0x00; + /* Basic checks passed */ + n_exp = float32_getexp(RsV); + d_exp = float32_getexp(RtV); + if ((n_exp - d_exp + SF_BIAS) <= SF_MANTBITS) { + /* Near quotient underflow / inexact Q */ + PeV = 0x80; + RtV = float32_mul_pow2(RtV, -64, fp_status); + RsV = float32_mul_pow2(RsV, 64, fp_status); + } else if ((n_exp - d_exp + SF_BIAS) > (SF_MAXEXP - 24)) { + /* Near quotient overflow */ + PeV = 0x40; + RtV = float32_mul_pow2(RtV, 32, fp_status); + RsV = float32_mul_pow2(RsV, -32, fp_status); + } else if (n_exp <= SF_MANTBITS + 2) { + RtV = float32_mul_pow2(RtV, 64, fp_status); + RsV = float32_mul_pow2(RsV, 64, fp_status); + } else if (d_exp <= 1) { + RtV = float32_mul_pow2(RtV, 32, fp_status); + RsV = float32_mul_pow2(RsV, 32, fp_status); + } else if (d_exp > 252) { + RtV = float32_mul_pow2(RtV, -32, fp_status); + RsV = float32_mul_pow2(RsV, -32, fp_status); + } + RdV = 0; + ret = 1; + } + *Rs = RsV; + *Rt = RtV; + *Rd = RdV; + *adjust = PeV; + return ret; +} + +int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust, + float_status *fp_status) +{ + float32 RsV, RdV; + int PeV = 0; + int r_exp; + int ret = 0; + RsV = *Rs; + if (float32_is_infinity(RsV)) { + if (extract32(RsV, 22, 1) == 0) { + float_raise(float_flag_invalid, fp_status); + } + RdV = RsV = float32_nan; + } else if (float32_lt(RsV, float32_zero, fp_status)) { + /* Negative nonzero values are NaN */ + float_raise(float_flag_invalid, fp_status); + RsV = float32_nan; + RdV = float32_nan; + } else if (float32_is_infinity(RsV)) { + /* or put Inf in num fixup? */ + RsV = infinite_float32(1); + RdV = infinite_float32(1); + } else if (float32_is_zero(RsV)) { + /* or put zero in num fixup? */ + RdV = float32_one; + } else { + PeV = 0x00; + /* Basic checks passed */ + r_exp = float32_getexp(RsV); + if (r_exp <= 24) { + RsV = float32_mul_pow2(RsV, 64, fp_status); + PeV = 0xe0; + } + RdV = 0; + ret = 1; + } + *Rs = RsV; + *Rd = RdV; + *adjust = PeV; + return ret; +} From patchwork Fri Oct 30 00:08:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 221AFC2D0A3 for ; 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29 Oct 2020 17:08:45 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id B1D8F411F; Thu, 29 Oct 2020 19:08:44 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 17/33] Hexagon (target/hexagon/fma_emu.[ch]) utility functions Date: Thu, 29 Oct 2020 19:08:23 -0500 Message-Id: <1604016519-28065-18-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Taylor Simpson --- target/hexagon/fma_emu.h | 32 +++ target/hexagon/fma_emu.c | 706 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 738 insertions(+) create mode 100644 target/hexagon/fma_emu.h create mode 100644 target/hexagon/fma_emu.c diff --git a/target/hexagon/fma_emu.h b/target/hexagon/fma_emu.h new file mode 100644 index 0000000..4402d63 --- /dev/null +++ b/target/hexagon/fma_emu.h @@ -0,0 +1,32 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_FMA_EMU_H +#define HEXAGON_FMA_EMU_H + +extern int32_t float64_getexp(float64 f64); +extern int32_t float32_getexp(float32 f32); +extern float32 infinite_float32(uint8_t sign); +extern float32 internal_fmafx(float32 a, float32 b, float32 c, + int scale, float_status *fp_status); +extern float32 internal_mpyf(float32 a, float32 b, + float_status *fp_status); +extern float64 internal_mpyhh(float64 a, float64 b, + unsigned long long int accumulated, + float_status *fp_status); + +#endif diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c new file mode 100644 index 0000000..2318a6e --- /dev/null +++ b/target/hexagon/fma_emu.c @@ -0,0 +1,706 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/int128.h" +#include "fpu/softfloat.h" +#include "macros.h" +#include "conv_emu.h" +#include "fma_emu.h" + +#define DF_INF_EXP 0x7ff +#define DF_BIAS 1023 +#define DF_MANTBITS 52 +#define DF_NAN 0xffffffffffffffffULL +#define DF_INF 0x7ff0000000000000ULL +#define DF_MINUS_INF 0xfff0000000000000ULL +#define DF_MAXF 0x7fefffffffffffffULL +#define DF_MINUS_MAXF 0xffefffffffffffffULL + +#define SF_INF_EXP 0xff +#define SF_BIAS 127 +#define SF_MANTBITS 23 +#define SF_INF 0x7f800000 +#define SF_MINUS_INF 0xff800000 +#define SF_MAXF 0x7f7fffff +#define SF_MINUS_MAXF 0xff7fffff + +#define HF_INF_EXP 0x1f +#define HF_BIAS 15 + +#define WAY_BIG_EXP 4096 + +typedef union { + double f; + uint64_t i; + struct { + uint64_t mant:52; + uint64_t exp:11; + uint64_t sign:1; + }; +} Double; + +typedef union { + float f; + uint32_t i; + struct { + uint32_t mant:23; + uint32_t exp:8; + uint32_t sign:1; + }; +} Float; + +static inline uint64_t float64_getmant(float64 f64) +{ + Double a = { .i = f64 }; + if (float64_is_normal(f64)) { + return a.mant | 1ULL << 52; + } + if (float64_is_zero(f64)) { + return 0; + } + if (float64_is_denormal(f64)) { + return a.mant; + } + return ~0ULL; +} + +int32_t float64_getexp(float64 f64) +{ + Double a = { .i = f64 }; + if (float64_is_normal(f64)) { + return a.exp; + } + if (float64_is_denormal(f64)) { + return a.exp + 1; + } + return -1; +} + +static inline uint64_t float32_getmant(float32 f32) +{ + Float a = { .i = f32 }; + if (float32_is_normal(f32)) { + return a.mant | 1ULL << 23; + } + if (float32_is_zero(f32)) { + return 0; + } + if (float32_is_denormal(f32)) { + return a.mant; + } + return ~0ULL; +} + +int32_t float32_getexp(float32 f32) +{ + Float a = { .i = f32 }; + if (float32_is_normal(f32)) { + return a.exp; + } + if (float32_is_denormal(f32)) { + return a.exp + 1; + } + return -1; +} + +static inline uint32_t int128_getw0(Int128 x) +{ + return int128_getlo(x); +} + +static inline uint32_t int128_getw1(Int128 x) +{ + return int128_getlo(x) >> 32; +} + +static inline Int128 int128_mul_6464(uint64_t ai, uint64_t bi) +{ + Int128 a, b; + uint64_t pp0, pp1a, pp1b, pp1s, pp2; + + a = int128_make64(ai); + b = int128_make64(bi); + pp0 = (uint64_t)int128_getw0(a) * (uint64_t)int128_getw0(b); + pp1a = (uint64_t)int128_getw1(a) * (uint64_t)int128_getw0(b); + pp1b = (uint64_t)int128_getw1(b) * (uint64_t)int128_getw0(a); + pp2 = (uint64_t)int128_getw1(a) * (uint64_t)int128_getw1(b); + + pp1s = pp1a + pp1b; + if ((pp1s < pp1a) || (pp1s < pp1b)) { + pp2 += (1ULL << 32); + } + uint64_t ret_low = pp0 + (pp1s << 32); + if ((ret_low < pp0) || (ret_low < (pp1s << 32))) { + pp2 += 1; + } + + return int128_make128(ret_low, pp2 + (pp1s >> 32)); +} + +static inline Int128 int128_sub_borrow(Int128 a, Int128 b, int borrow) +{ + Int128 ret = int128_sub(a, b); + if (borrow != 0) { + ret = int128_sub(ret, int128_one()); + } + return ret; +} + +typedef struct { + Int128 mant; + int32_t exp; + uint8_t sign; + uint8_t guard; + uint8_t round; + uint8_t sticky; +} Accum; + +static inline void accum_init(Accum *p) +{ + p->mant = int128_zero(); + p->exp = 0; + p->sign = 0; + p->guard = 0; + p->round = 0; + p->sticky = 0; +} + +static inline Accum accum_norm_left(Accum a) +{ + a.exp--; + a.mant = int128_lshift(a.mant, 1); + a.mant = int128_or(a.mant, int128_make64(a.guard)); + a.guard = a.round; + a.round = a.sticky; + return a; +} + +static inline Accum accum_norm_right(Accum a, int amt) +{ + if (amt > 130) { + a.sticky |= + a.round | a.guard | int128_nz(a.mant); + a.guard = a.round = 0; + a.mant = int128_zero(); + a.exp += amt; + return a; + + } + while (amt >= 64) { + a.sticky |= a.round | a.guard | (int128_getlo(a.mant) != 0); + a.guard = (int128_getlo(a.mant) >> 63) & 1; + a.round = (int128_getlo(a.mant) >> 62) & 1; + a.mant = int128_make64(int128_gethi(a.mant)); + a.exp += 64; + amt -= 64; + } + while (amt > 0) { + a.exp++; + a.sticky |= a.round; + a.round = a.guard; + a.guard = int128_getlo(a.mant) & 1; + a.mant = int128_rshift(a.mant, 1); + amt--; + } + return a; +} + +/* + * On the add/sub, we need to be able to shift out lots of bits, but need a + * sticky bit for what was shifted out, I think. + */ +static Accum accum_add(Accum a, Accum b); + +static inline Accum accum_sub(Accum a, Accum b, int negate) +{ + Accum ret; + accum_init(&ret); + int borrow; + + if (a.sign != b.sign) { + b.sign = !b.sign; + return accum_add(a, b); + } + if (b.exp > a.exp) { + /* small - big == - (big - small) */ + return accum_sub(b, a, !negate); + } + if ((b.exp == a.exp) && (int128_gt(b.mant, a.mant))) { + /* small - big == - (big - small) */ + return accum_sub(b, a, !negate); + } + + while (a.exp > b.exp) { + /* Try to normalize exponents: shrink a exponent and grow mantissa */ + if (int128_gethi(a.mant) & (1ULL << 62)) { + /* Can't grow a any more */ + break; + } else { + a = accum_norm_left(a); + } + } + + while (a.exp > b.exp) { + /* Try to normalize exponents: grow b exponent and shrink mantissa */ + /* Keep around shifted out bits... we might need those later */ + b = accum_norm_right(b, a.exp - b.exp); + } + + if ((int128_gt(b.mant, a.mant))) { + return accum_sub(b, a, !negate); + } + + /* OK, now things should be normalized! */ + ret.sign = a.sign; + ret.exp = a.exp; + assert(!int128_gt(b.mant, a.mant)); + borrow = (b.round << 2) | (b.guard << 1) | b.sticky; + ret.mant = int128_sub_borrow(a.mant, b.mant, (borrow != 0)); + borrow = 0 - borrow; + ret.guard = (borrow >> 2) & 1; + ret.round = (borrow >> 1) & 1; + ret.sticky = (borrow >> 0) & 1; + if (negate) { + ret.sign = !ret.sign; + } + return ret; +} + +static Accum accum_add(Accum a, Accum b) +{ + Accum ret; + accum_init(&ret); + if (a.sign != b.sign) { + b.sign = !b.sign; + return accum_sub(a, b, 0); + } + if (b.exp > a.exp) { + /* small + big == (big + small) */ + return accum_add(b, a); + } + if ((b.exp == a.exp) && int128_gt(b.mant, a.mant)) { + /* small + big == (big + small) */ + return accum_add(b, a); + } + + while (a.exp > b.exp) { + /* Try to normalize exponents: shrink a exponent and grow mantissa */ + if (int128_gethi(a.mant) & (1ULL << 62)) { + /* Can't grow a any more */ + break; + } else { + a = accum_norm_left(a); + } + } + + while (a.exp > b.exp) { + /* Try to normalize exponents: grow b exponent and shrink mantissa */ + /* Keep around shifted out bits... we might need those later */ + b = accum_norm_right(b, a.exp - b.exp); + } + + /* OK, now things should be normalized! */ + if (int128_gt(b.mant, a.mant)) { + return accum_add(b, a); + }; + ret.sign = a.sign; + ret.exp = a.exp; + assert(!int128_gt(b.mant, a.mant)); + ret.mant = int128_add(a.mant, b.mant); + ret.guard = b.guard; + ret.round = b.round; + ret.sticky = b.sticky; + return ret; +} + +/* Return an infinity with requested sign */ +static inline float64 infinite_float64(uint8_t sign) +{ + if (sign) { + return make_float64(DF_MINUS_INF); + } else { + return make_float64(DF_INF); + } +} + +/* Return a maximum finite value with requested sign */ +static inline float64 maxfinite_float64(uint8_t sign) +{ + if (sign) { + return make_float64(DF_MINUS_MAXF); + } else { + return make_float64(DF_MAXF); + } +} + +/* Return a zero value with requested sign */ +static inline float64 zero_float64(uint8_t sign) +{ + if (sign) { + return make_float64(0x8000000000000000); + } else { + return float64_zero; + } +} + +/* Return an infinity with the requested sign */ +float32 infinite_float32(uint8_t sign) +{ + if (sign) { + return make_float32(SF_MINUS_INF); + } else { + return make_float32(SF_INF); + } +} + +/* Return a maximum finite value with the requested sign */ +static inline float32 maxfinite_float32(uint8_t sign) +{ + if (sign) { + return make_float32(SF_MINUS_MAXF); + } else { + return make_float32(SF_MAXF); + } +} + +/* Return a zero value with requested sign */ +static inline float32 zero_float32(uint8_t sign) +{ + if (sign) { + return make_float32(0x80000000); + } else { + return float32_zero; + } +} + +#define GEN_XF_ROUND(SUFFIX, MANTBITS, INF_EXP, INTERNAL_TYPE) \ +static inline SUFFIX accum_round_##SUFFIX(Accum a, float_status * fp_status) \ +{ \ + if ((int128_gethi(a.mant) == 0) && (int128_getlo(a.mant) == 0) \ + && ((a.guard | a.round | a.sticky) == 0)) { \ + /* result zero */ \ + switch (fp_status->float_rounding_mode) { \ + case float_round_down: \ + return zero_##SUFFIX(1); \ + default: \ + return zero_##SUFFIX(0); \ + } \ + } \ + /* Normalize right */ \ + /* We want MANTBITS bits of mantissa plus the leading one. */ \ + /* That means that we want MANTBITS+1 bits, or 0x000000000000FF_FFFF */ \ + /* So we need to normalize right while the high word is non-zero and \ + * while the low word is nonzero when masked with 0xffe0_0000_0000_0000 */ \ + while ((int128_gethi(a.mant) != 0) || \ + ((int128_getlo(a.mant) >> (MANTBITS + 1)) != 0)) { \ + a = accum_norm_right(a, 1); \ + } \ + /* \ + * OK, now normalize left \ + * We want to normalize left until we have a leading one in bit 24 \ + * Theoretically, we only need to shift a maximum of one to the left if we \ + * shifted out lots of bits from B, or if we had no shift / 1 shift sticky \ + * shoudl be 0 \ + */ \ + while ((int128_getlo(a.mant) & (1ULL << MANTBITS)) == 0) { \ + a = accum_norm_left(a); \ + } \ + /* \ + * OK, now we might need to denormalize because of potential underflow. \ + * We need to do this before rounding, and rounding might make us normal \ + * again \ + */ \ + while (a.exp <= 0) { \ + a = accum_norm_right(a, 1 - a.exp); \ + /* \ + * Do we have underflow? \ + * That's when we get an inexact answer because we ran out of bits \ + * in a denormal. \ + */ \ + if (a.guard || a.round || a.sticky) { \ + float_raise(float_flag_underflow, fp_status); \ + } \ + } \ + /* OK, we're relatively canonical... now we need to round */ \ + if (a.guard || a.round || a.sticky) { \ + float_raise(float_flag_inexact, fp_status); \ + switch (fp_status->float_rounding_mode) { \ + case float_round_to_zero: \ + /* Chop and we're done */ \ + break; \ + case float_round_up: \ + if (a.sign == 0) { \ + a.mant = int128_add(a.mant, int128_one()); \ + } \ + break; \ + case float_round_down: \ + if (a.sign != 0) { \ + a.mant = int128_add(a.mant, int128_one()); \ + } \ + break; \ + default: \ + if (a.round || a.sticky) { \ + /* round up if guard is 1, down if guard is zero */ \ + a.mant = int128_add(a.mant, int128_make64(a.guard)); \ + } else if (a.guard) { \ + /* exactly .5, round up if odd */ \ + a.mant = int128_add(a.mant, int128_and(a.mant, int128_one())); \ + } \ + break; \ + } \ + } \ + /* \ + * OK, now we might have carried all the way up. \ + * So we might need to shr once \ + * at least we know that the lsb should be zero if we rounded and \ + * got a carry out... \ + */ \ + if ((int128_getlo(a.mant) >> (MANTBITS + 1)) != 0) { \ + a = accum_norm_right(a, 1); \ + } \ + /* Overflow? */ \ + if (a.exp >= INF_EXP) { \ + /* Yep, inf result */ \ + float_raise(float_flag_overflow, fp_status); \ + float_raise(float_flag_inexact, fp_status); \ + switch (fp_status->float_rounding_mode) { \ + case float_round_to_zero: \ + return maxfinite_##SUFFIX(a.sign); \ + case float_round_up: \ + if (a.sign == 0) { \ + return infinite_##SUFFIX(a.sign); \ + } else { \ + return maxfinite_##SUFFIX(a.sign); \ + } \ + case float_round_down: \ + if (a.sign != 0) { \ + return infinite_##SUFFIX(a.sign); \ + } else { \ + return maxfinite_##SUFFIX(a.sign); \ + } \ + default: \ + return infinite_##SUFFIX(a.sign); \ + } \ + } \ + /* Underflow? */ \ + if (int128_getlo(a.mant) & (1ULL << MANTBITS)) { \ + /* Leading one means: No, we're normal. So, we should be done... */ \ + INTERNAL_TYPE ret; \ + ret.i = 0; \ + ret.sign = a.sign; \ + ret.exp = a.exp; \ + ret.mant = int128_getlo(a.mant); \ + return ret.i; \ + } \ + assert(a.exp == 1); \ + INTERNAL_TYPE ret; \ + ret.i = 0; \ + ret.sign = a.sign; \ + ret.exp = 0; \ + ret.mant = int128_getlo(a.mant); \ + return ret.i; \ +} + +GEN_XF_ROUND(float64, DF_MANTBITS, DF_INF_EXP, Double) +GEN_XF_ROUND(float32, SF_MANTBITS, SF_INF_EXP, Float) + +static bool isfinite(float64 x) +{ + return !float64_is_any_nan(x) && !float64_is_infinity(x); +} + +static bool is_inf_prod(float64 a, float64 b) +{ + return ((float64_is_infinity(a) && float64_is_infinity(b)) || + (float64_is_infinity(a) && isfinite(b) && (!float64_is_zero(b))) || + (float64_is_infinity(b) && isfinite(a) && (float64_is_zero(a)))); +} + +static inline float64 special_fma(float64 a, float64 b, float64 c, + float_status *fp_status) +{ + float64 ret = make_float64(0); + + /* + * If A multiplied by B is an exact infinity and C is also an infinity + * but with the opposite sign, FMA returns NaN and raises invalid. + */ + uint8_t a_sign = float64_is_neg(a); + uint8_t b_sign = float64_is_neg(b); + uint8_t c_sign = float64_is_neg(c); + if (is_inf_prod(a, b) && float64_is_infinity(c)) { + if ((a_sign ^ b_sign) != c_sign) { + ret = make_float64(DF_NAN); + float_raise(float_flag_invalid, fp_status); + return ret; + } + } + if ((float64_is_infinity(a) && float64_is_zero(b)) || + (float64_is_zero(a) && float64_is_infinity(b))) { + ret = make_float64(DF_NAN); + float_raise(float_flag_invalid, fp_status); + return ret; + } + /* + * If none of the above checks are true and C is a NaN, + * a NaN shall be returned + * If A or B are NaN, a NAN shall be returned. + */ + if (float64_is_any_nan(a) || + float64_is_any_nan(b) || + float64_is_any_nan(c)) { + if (float64_is_any_nan(a) && (fGETBIT(51, a) == 0)) { + float_raise(float_flag_invalid, fp_status); + } + if (float64_is_any_nan(b) && (fGETBIT(51, b) == 0)) { + float_raise(float_flag_invalid, fp_status); + } + if (float64_is_any_nan(c) && (fGETBIT(51, c) == 0)) { + float_raise(float_flag_invalid, fp_status); + } + ret = make_float64(DF_NAN); + return ret; + } + /* + * We have checked for adding opposite-signed infinities. + * Other infinities return infinity with the correct sign + */ + if (float64_is_infinity(c)) { + ret = infinite_float64(c_sign); + return ret; + } + if (float64_is_infinity(a) || float64_is_infinity(b)) { + ret = infinite_float64(a_sign ^ b_sign); + return ret; + } + g_assert_not_reached(); +} + +static inline float32 special_fmaf(float32 a, float32 b, float32 c, + float_status *fp_status) +{ + float64 aa, bb, cc; + aa = float32_to_float64(a, fp_status); + bb = float32_to_float64(b, fp_status); + cc = float32_to_float64(c, fp_status); + return float64_to_float32(special_fma(aa, bb, cc, fp_status), fp_status); +} + +float32 internal_fmafx(float32 a, float32 b, float32 c, int scale, + float_status *fp_status) +{ + Accum prod; + Accum acc; + Accum result; + accum_init(&prod); + accum_init(&acc); + accum_init(&result); + + uint8_t a_sign = float32_is_neg(a); + uint8_t b_sign = float32_is_neg(b); + uint8_t c_sign = float32_is_neg(c); + if (float32_is_infinity(a) || + float32_is_infinity(b) || + float32_is_infinity(c)) { + return special_fmaf(a, b, c, fp_status); + } + if (float32_is_any_nan(a) || + float32_is_any_nan(b) || + float32_is_any_nan(c)) { + return special_fmaf(a, b, c, fp_status); + } + if ((scale == 0) && (float32_is_zero(a) || float32_is_zero(b))) { + float32 tmp = float32_mul(a, b, fp_status); + tmp = float32_add(tmp, c, fp_status); + return tmp; + } + + /* (a * 2**b) * (c * 2**d) == a*c * 2**(b+d) */ + prod.mant = int128_mul_6464(float32_getmant(a), float32_getmant(b)); + + /* + * Note: extracting the mantissa into an int is multiplying by + * 2**23, so adjust here + */ + prod.exp = float32_getexp(a) + float32_getexp(b) - SF_BIAS - 23; + prod.sign = a_sign ^ b_sign; + if (float32_is_zero(a) || float32_is_zero(b)) { + prod.exp = -2 * WAY_BIG_EXP; + } + if ((scale > 0) && float32_is_denormal(c)) { + acc.mant = int128_mul_6464(0, 0); + acc.exp = -WAY_BIG_EXP; + acc.sign = c_sign; + acc.sticky = 1; + result = accum_add(prod, acc); + } else if (!float32_is_zero(c)) { + acc.mant = int128_mul_6464(float32_getmant(c), 1); + acc.exp = float32_getexp(c); + acc.sign = c_sign; + result = accum_add(prod, acc); + } else { + result = prod; + } + result.exp += scale; + return accum_round_float32(result, fp_status); +} + +float32 internal_mpyf(float32 a, float32 b, float_status *fp_status) +{ + if (float32_is_zero(a) || float32_is_zero(b)) { + return float32_mul(a, b, fp_status); + } + return internal_fmafx(a, b, float32_zero, 0, fp_status); +} + +float64 internal_mpyhh(float64 a, float64 b, + unsigned long long int accumulated, + float_status *fp_status) +{ + Accum x; + unsigned long long int prod; + unsigned int sticky; + + sticky = accumulated & 1; + accumulated >>= 1; + accum_init(&x); + if (float64_is_zero(a) || + float64_is_any_nan(a) || + float64_is_infinity(a)) { + return float64_mul(a, b, fp_status); + } + if (float64_is_zero(b) || + float64_is_any_nan(b) || + float64_is_infinity(b)) { + return float64_mul(a, b, fp_status); + } + x.mant = int128_mul_6464(accumulated, 1); + x.sticky = sticky; + prod = fGETUWORD(1, float64_getmant(a)) * fGETUWORD(1, float64_getmant(b)); + x.mant = int128_add(x.mant, int128_mul_6464(prod, 0x100000000ULL)); + x.exp = float64_getexp(a) + float64_getexp(b) - DF_BIAS - 20; + if (!float64_is_normal(a) || !float64_is_normal(b)) { + /* crush to inexact zero */ + x.sticky = 1; + x.exp = -4096; + } + uint8_t a_sign = float64_is_neg(a); + uint8_t b_sign = float64_is_neg(b); + x.sign = a_sign ^ b_sign; + return accum_round_float64(x, fp_status); +} From patchwork Fri Oct 30 00:08:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 681CFC55178 for ; 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29 Oct 2020 17:08:45 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 6081B411D; Thu, 29 Oct 2020 19:08:45 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 19/33] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Date: Thu, 29 Oct 2020 19:08:25 -0500 Message-Id: <1604016519-28065-20-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Run the C preprocessor across the instruction definition files and macro definition file to expand macros and prepare the semantics_generated.pyinc file. The resulting file contains one entry with the semantics for each instruction and one line with the instruction attributes associated with each macro. Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé . + */ + +/* + * This program generates the semantics file that is processed by + * the do_qemu.py script. We use the C preporcessor to manipulate the + * files imported from the Hexagon architecture library. + */ + +#include +#define STRINGIZE(X) #X + +int main(int argc, char *argv[]) +{ + FILE *outfile; + + if (argc != 2) { + fprintf(stderr, "Usage: gen_semantics ouptputfile\n"); + return 1; + } + outfile = fopen(argv[1], "w"); + if (outfile == NULL) { + fprintf(stderr, "Cannot open %s for writing\n", argv[1]); + return 1; + } + +/* + * Process the instruction definitions + * Scalar core instructions have the following form + * Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(), + * "Add 32-bit registers", + * { RdV=RsV+RtV;}) + */ +#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ + do { \ + fprintf(outfile, "SEMANTICS( \\\n" \ + " \"%s\", \\\n" \ + " %s, \\\n" \ + " \"\"\"%s\"\"\" \\\n" \ + ")\n", \ + #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \ + fprintf(outfile, "ATTRIBUTES( \\\n" \ + " \"%s\", \\\n" \ + " \"%s\" \\\n" \ + ")\n", \ + #TAG, STRINGIZE(ATTRIBS)); \ + } while (0); +#include "imported/allidefs.def" +#undef Q6INSN + +/* + * Process the macro definitions + * Macros definitions have the following form + * DEF_MACRO( + * fLSBNEW0, + * predlog_read(thread,0), + * () + * ) + * The important part here is the attributes. Whenever an instruction + * invokes a macro, we add the macro's attributes to the instruction. + */ +#define DEF_MACRO(MNAME, BEH, ATTRS) \ + fprintf(outfile, "MACROATTRIB( \\\n" \ + " \"%s\", \\\n" \ + " \"\"\"%s\"\"\", \\\n" \ + " \"%s\" \\\n" \ + ")\n", \ + #MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS)); +#include "imported/macros.def" +#undef DEF_MACRO + + fclose(outfile); + return 0; +} From patchwork Fri Oct 30 00:08:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A529C4742C for ; Fri, 30 Oct 2020 00:34:22 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D3BF520723 for ; Fri, 30 Oct 2020 00:34:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="skFcCk8h" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D3BF520723 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:59246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kYIN2-00024i-Po for qemu-devel@archiver.kernel.org; Thu, 29 Oct 2020 20:34:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39202) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kYHyy-0004IL-La for qemu-devel@nongnu.org; Thu, 29 Oct 2020 20:09:28 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:54820) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kYHys-0005RE-6r for qemu-devel@nongnu.org; Thu, 29 Oct 2020 20:09:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1604016562; x=1635552562; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JY9APKqwwFW6QQIVwUlm2KqDq6O0G/1RptPUjIoD7HY=; b=skFcCk8hjhnhgRw1b6PpsGEoePgBMHh3QklaOa0esCN6054BLxcaji6+ EZZiVGkgokgAv9Yf50qyYfpNK3q/9eWk9OyGzKW4FsvEe0YE6EDBQ+jyr DDfBC65l8VqBW5nfDUoWIwz1eD+J/Dw5bvPKTXG86RN51GHYVGVmxy6KV c=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 29 Oct 2020 17:08:46 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg04-sd.qualcomm.com with ESMTP; 29 Oct 2020 17:08:45 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id BB8594119; Thu, 29 Oct 2020 19:08:45 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 21/33] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Date: Thu, 29 Oct 2020 19:08:27 -0500 Message-Id: <1604016519-28065-22-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Run the C preprocessor across the instruction definition and encoding files to expand macros and prepare the iset.py file. The resulting fill contains python data structures used to build the decode tree. Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé . + */ + +/* + * This program generates the encodings file that is processed by + * the dectree.py script to produce the decoding tree. We use the C + * preprocessor to manipulate the files imported from the Hexagon + * architecture library. + */ +#include "qemu/osdep.h" +#include "opcodes.h" + +#define STRINGIZE(X) #X + +const char * const opcode_names[] = { +#define OPCODE(IID) STRINGIZE(IID) +#include "opcodes_def_generated.h" + NULL +#undef OPCODE +}; + +/* + * Process the instruction definitions + * Scalar core instructions have the following form + * Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(), + * "Add 32-bit registers", + * { RdV=RsV+RtV;}) + */ +const char * const opcode_syntax[XX_LAST_OPCODE] = { +#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ + [TAG] = BEH, +#define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ + [TAG] = BEH, +#include "imported/allidefs.def" +#undef Q6INSN +#undef EXTINSN +}; + +const char * const opcode_rregs[] = { +#define REGINFO(TAG, REGINFO, RREGS, WREGS) RREGS, +#define IMMINFO(TAG, SIGN, SIZE, SHAMT, SIGN2, SIZE2, SHAMT2) /* nothing */ +#include "op_regs_generated.h" + NULL +#undef REGINFO +#undef IMMINFO +}; + +const char * const opcode_wregs[] = { +#define REGINFO(TAG, REGINFO, RREGS, WREGS) WREGS, +#define IMMINFO(TAG, SIGN, SIZE, SHAMT, SIGN2, SIZE2, SHAMT2) /* nothing */ +#include "op_regs_generated.h" + NULL +#undef REGINFO +#undef IMMINFO +}; + +const OpcodeEncoding opcode_encodings[] = { +#define DEF_ENC32(TAG, ENCSTR) \ + [TAG] = { .encoding = ENCSTR }, +#define DEF_ENC_SUBINSN(TAG, CLASS, ENCSTR) \ + [TAG] = { .encoding = ENCSTR, .enc_class = CLASS }, +#define DEF_EXT_ENC(TAG, CLASS, ENCSTR) \ + [TAG] = { .encoding = ENCSTR, .enc_class = CLASS }, +#include "imported/encode.def" +#undef DEF_ENC32 +#undef DEF_ENC_SUBINSN +#undef DEF_EXT_ENC +}; + +static const char * const opcode_enc_class_names[XX_LAST_ENC_CLASS] = { + "NORMAL", + "16BIT", + "SUBINSN_A", + "SUBINSN_L1", + "SUBINSN_L2", + "SUBINSN_S1", + "SUBINSN_S2", + "EXT_noext", + "EXT_mmvec", +}; + +static const char *get_opcode_enc(int opcode) +{ + const char *tmp = opcode_encodings[opcode].encoding; + if (tmp == NULL) { + tmp = "MISSING ENCODING"; + } + return tmp; +} + +static const char *get_opcode_enc_class(int opcode) +{ + return opcode_enc_class_names[opcode_encodings[opcode].enc_class]; +} + +static void gen_iset_table(FILE *out) +{ + int i; + + fprintf(out, "iset = {\n"); + for (i = 0; i < XX_LAST_OPCODE; i++) { + fprintf(out, "\t\'%s\' : {\n", opcode_names[i]); + fprintf(out, "\t\t\'tag\' : \'%s\',\n", opcode_names[i]); + fprintf(out, "\t\t\'syntax\' : \'%s\',\n", opcode_syntax[i]); + fprintf(out, "\t\t\'rregs\' : \'%s\',\n", opcode_rregs[i]); + fprintf(out, "\t\t\'wregs\' : \'%s\',\n", opcode_wregs[i]); + fprintf(out, "\t\t\'enc\' : \'%s\',\n", get_opcode_enc(i)); + fprintf(out, "\t\t\'enc_class\' : \'%s\',\n", get_opcode_enc_class(i)); + fprintf(out, "\t},\n"); + } + fprintf(out, "};\n\n"); +} + +static void gen_tags_list(FILE *out) +{ + int i; + + fprintf(out, "tags = [\n"); + for (i = 0; i < XX_LAST_OPCODE; i++) { + fprintf(out, "\t\'%s\',\n", opcode_names[i]); + } + fprintf(out, "];\n\n"); +} + +static void gen_enc_ext_spaces_table(FILE *out) +{ + fprintf(out, "enc_ext_spaces = {\n"); +#define DEF_EXT_SPACE(SPACEID, ENCSTR) \ + fprintf(out, "\t\'%s\' : \'%s\',\n", #SPACEID, ENCSTR); +#include "imported/encode.def" +#undef DEF_EXT_SPACE + fprintf(out, "};\n\n"); +} + +static void gen_subinsn_groupings_table(FILE *out) +{ + fprintf(out, "subinsn_groupings = {\n"); +#define DEF_PACKED32(TAG, TYPEA, TYPEB, ENCSTR) \ + do { \ + fprintf(out, "\t\'%s\' : {\n", #TAG); \ + fprintf(out, "\t\t\'name\' : \'%s\',\n", #TAG); \ + fprintf(out, "\t\t\'class_a\' : \'%s\',\n", #TYPEA); \ + fprintf(out, "\t\t\'class_b\' : \'%s\',\n", #TYPEB); \ + fprintf(out, "\t\t\'enc\' : \'%s\',\n", ENCSTR); \ + fprintf(out, "\t},\n"); \ + } while (0); +#include "imported/encode.def" +#undef DEF_PACKED32 + fprintf(out, "};\n\n"); +} + +int main(int argc, char *argv[]) +{ + FILE *outfile; + + if (argc != 2) { + fprintf(stderr, "Usage: gen_dectree_import ouptputfile\n"); + return 1; + } + outfile = fopen(argv[1], "w"); + if (outfile == NULL) { + fprintf(stderr, "Cannot open %s for writing\n", argv[1]); + return 1; + } + + gen_iset_table(outfile); + gen_tags_list(outfile); + gen_enc_ext_spaces_table(outfile); + gen_subinsn_groupings_table(outfile); + + fclose(outfile); + return 0; +} From patchwork Fri Oct 30 00:08:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316568 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48E9CC2D0A3 for ; Fri, 30 Oct 2020 00:37:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 977E820723 for ; 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Thu, 29 Oct 2020 20:09:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1604016576; x=1635552576; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BpHAH5vhBB84mnTXmksS9DJraDtehmFXG3U/+0GbW9w=; b=oHmVO/UHno+GWTO1f8edsgeYYl0dSaTcRjOp8iZx/py5HxgMKwpaWjO2 RmJS0EAXK5AQu8khORl2bhlbN6pYA0xnh6veY8K3mXqL4vumCf0u9kmbf uGIRna/e1vXUTHthS6wrjMOEMVEhc7d1HGJRhO6GzOlzTRpSH3Z6pJ04S 8=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 29 Oct 2020 17:08:46 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg-SD-alpha.qualcomm.com with ESMTP; 29 Oct 2020 17:08:46 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id D3068411B; Thu, 29 Oct 2020 19:08:45 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 22/33] Hexagon (target/hexagon) generater phase 4 - decode tree Date: Thu, 29 Oct 2020 19:08:28 -0500 Message-Id: <1604016519-28065-23-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Python script that emits the decode tree in dectree_generated.h. Signed-off-by: Taylor Simpson --- target/hexagon/dectree.py | 352 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 352 insertions(+) create mode 100755 target/hexagon/dectree.py diff --git a/target/hexagon/dectree.py b/target/hexagon/dectree.py new file mode 100755 index 0000000..8e9d32f --- /dev/null +++ b/target/hexagon/dectree.py @@ -0,0 +1,352 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import io +import re + +import sys +import iset + +encs = {tag : ''.join(reversed(iset.iset[tag]['enc'].replace(' ', ''))) + for tag in iset.tags if iset.iset[tag]['enc'] != 'MISSING ENCODING'} + +enc_classes = set([iset.iset[tag]['enc_class'] for tag in encs.keys()]) +subinsn_enc_classes = \ + set([enc_class for enc_class in enc_classes \ + if enc_class.startswith('SUBINSN_')]) +ext_enc_classes = \ + set([enc_class for enc_class in enc_classes \ + if enc_class not in ('NORMAL', '16BIT') and \ + not enc_class.startswith('SUBINSN_')]) + +try: + subinsn_groupings = iset.subinsn_groupings +except AttributeError: + subinsn_groupings = {} + +for (tag, subinsn_grouping) in subinsn_groupings.items(): + encs[tag] = ''.join(reversed(subinsn_grouping['enc'].replace(' ', ''))) + +dectree_normal = {'leaves' : set()} +dectree_16bit = {'leaves' : set()} +dectree_subinsn_groupings = {'leaves' : set()} +dectree_subinsns = {name : {'leaves' : set()} for name in subinsn_enc_classes} +dectree_extensions = {name : {'leaves' : set()} for name in ext_enc_classes} + +for tag in encs.keys(): + if tag in subinsn_groupings: + dectree_subinsn_groupings['leaves'].add(tag) + continue + enc_class = iset.iset[tag]['enc_class'] + if enc_class.startswith('SUBINSN_'): + if len(encs[tag]) != 32: + encs[tag] = encs[tag] + '0' * (32 - len(encs[tag])) + dectree_subinsns[enc_class]['leaves'].add(tag) + elif enc_class == '16BIT': + if len(encs[tag]) != 16: + raise Exception('Tag "{}" has enc_class "{}" and not an encoding ' + + 'width of 16 bits!'.format(tag, enc_class)) + dectree_16bit['leaves'].add(tag) + else: + if len(encs[tag]) != 32: + raise Exception('Tag "{}" has enc_class "{}" and not an encoding ' + + 'width of 32 bits!'.format(tag, enc_class)) + if enc_class == 'NORMAL': + dectree_normal['leaves'].add(tag) + else: + dectree_extensions[enc_class]['leaves'].add(tag) + +faketags = set() +for (tag, enc) in iset.enc_ext_spaces.items(): + faketags.add(tag) + encs[tag] = ''.join(reversed(enc.replace(' ', ''))) + dectree_normal['leaves'].add(tag) + +faketags |= set(subinsn_groupings.keys()) + +def every_bit_counts(bitset): + for i in range(1, len(next(iter(bitset)))): + if len(set([bits[:i] + bits[i+1:] for bits in bitset])) == len(bitset): + return False + return True + +def auto_separate(node): + tags = node['leaves'] + if len(tags) <= 1: + return + enc_width = len(encs[next(iter(tags))]) + opcode_bit_for_all = \ + [all([encs[tag][i] in '01' \ + for tag in tags]) for i in range(enc_width)] + opcode_bit_is_0_for_all = \ + [opcode_bit_for_all[i] and all([encs[tag][i] == '0' \ + for tag in tags]) for i in range(enc_width)] + opcode_bit_is_1_for_all = \ + [opcode_bit_for_all[i] and all([encs[tag][i] == '1' \ + for tag in tags]) for i in range(enc_width)] + differentiator_opcode_bit = \ + [opcode_bit_for_all[i] and \ + not (opcode_bit_is_0_for_all[i] or \ + opcode_bit_is_1_for_all[i]) \ + for i in range(enc_width)] + best_width = 0 + for width in range(4, 0, -1): + for lsb in range(enc_width - width, -1, -1): + bitset = set([encs[tag][lsb:lsb+width] for tag in tags]) + if all(differentiator_opcode_bit[lsb:lsb+width]) and \ + (len(bitset) == len(tags) or every_bit_counts(bitset)): + best_width = width + best_lsb = lsb + caught_all_tags = len(bitset) == len(tags) + break + if best_width != 0: + break + if best_width == 0: + raise Exception('Could not find a way to differentiate the encodings ' + + 'of the following tags:\n{}'.format('\n'.join(tags))) + if caught_all_tags: + for width in range(1, best_width): + for lsb in range(enc_width - width, -1, -1): + bitset = set([encs[tag][lsb:lsb+width] for tag in tags]) + if all(differentiator_opcode_bit[lsb:lsb+width]) and \ + len(bitset) == len(tags): + best_width = width + best_lsb = lsb + break + else: + continue + break + node['separator_lsb'] = best_lsb + node['separator_width'] = best_width + node['children'] = [] + for value in range(2 ** best_width): + child = {} + bits = ''.join(reversed('{:0{}b}'.format(value, best_width))) + child['leaves'] = \ + set([tag for tag in tags \ + if encs[tag][best_lsb:best_lsb+best_width] == bits]) + node['children'].append(child) + for child in node['children']: + auto_separate(child) + +auto_separate(dectree_normal) +auto_separate(dectree_16bit) +if subinsn_groupings: + auto_separate(dectree_subinsn_groupings) +for dectree_subinsn in dectree_subinsns.values(): + auto_separate(dectree_subinsn) +for dectree_ext in dectree_extensions.values(): + auto_separate(dectree_ext) + +for tag in faketags: + del encs[tag] + +def table_name(parents, node): + path = parents + [node] + root = path[0] + tag = next(iter(node['leaves'])) + if tag in subinsn_groupings: + enc_width = len(subinsn_groupings[tag]['enc'].replace(' ', '')) + else: + tag = next(iter(node['leaves'] - faketags)) + enc_width = len(encs[tag]) + determining_bits = ['_'] * enc_width + for (parent, child) in zip(path[:-1], path[1:]): + lsb = parent['separator_lsb'] + width = parent['separator_width'] + value = parent['children'].index(child) + determining_bits[lsb:lsb+width] = \ + list(reversed('{:0{}b}'.format(value, width))) + if tag in subinsn_groupings: + name = 'DECODE_ROOT_EE' + else: + enc_class = iset.iset[tag]['enc_class'] + if enc_class in ext_enc_classes: + name = 'DECODE_EXT_{}'.format(enc_class) + elif enc_class in subinsn_enc_classes: + name = 'DECODE_SUBINSN_{}'.format(enc_class) + else: + name = 'DECODE_ROOT_{}'.format(enc_width) + if node != root: + name += '_' + ''.join(reversed(determining_bits)) + return name + +def print_node(f, node, parents): + if len(node['leaves']) <= 1: + return + name = table_name(parents, node) + lsb = node['separator_lsb'] + width = node['separator_width'] + print('DECODE_NEW_TABLE({},{},DECODE_SEPARATOR_BITS({},{}))'.\ + format(name, 2 ** width, lsb, width), file=f) + for child in node['children']: + if len(child['leaves']) == 0: + print('INVALID()', file=f) + elif len(child['leaves']) == 1: + (tag,) = child['leaves'] + if tag in subinsn_groupings: + class_a = subinsn_groupings[tag]['class_a'] + class_b = subinsn_groupings[tag]['class_b'] + enc = subinsn_groupings[tag]['enc'].replace(' ', '') + if 'RESERVED' in tag: + print('INVALID()', file=f) + else: + print('SUBINSNS({},{},{},"{}")'.\ + format(tag, class_a, class_b, enc), file=f) + elif tag in iset.enc_ext_spaces: + enc = iset.enc_ext_spaces[tag].replace(' ', '') + print('EXTSPACE({},"{}")'.format(tag, enc), file=f) + else: + enc = ''.join(reversed(encs[tag])) + print('TERMINAL({},"{}")'.format(tag, enc), file=f) + else: + print('TABLE_LINK({})'.format(table_name(parents + [node], child)), + file=f) + print('DECODE_END_TABLE({},{},DECODE_SEPARATOR_BITS({},{}))'.\ + format(name, 2 ** width, lsb, width), file=f) + print(file=f) + parents.append(node) + for child in node['children']: + print_node(f, child, parents) + parents.pop() + +def print_tree(f, tree): + print_node(f, tree, []) + +def print_match_info(f): + for tag in sorted(encs.keys(), key=iset.tags.index): + enc = ''.join(reversed(encs[tag])) + mask = int(re.sub(r'[^1]', r'0', enc.replace('0', '1')), 2) + match = int(re.sub(r'[^01]', r'0', enc), 2) + suffix = '' + print('DECODE{}_MATCH_INFO({},0x{:x}U,0x{:x}U)'.\ + format(suffix, tag, mask, match), file=f) + +regre = re.compile( + r'((? 1: + raise Exception('Tag "{}" has split register field!'.\ + format(tag)) + reg_enc_field = reg_enc_fields[0] + if 2 ** len(reg_enc_field) != reg_num_choices: + raise Exception('Tag "{}" has incorrect register field width!'.\ + format(tag)) + print(' DECODE_REG({},{},{})'.\ + format(regno, len(reg_enc_field), enc.index(reg_enc_field)), + file=f) + if reg_type in num_registers and \ + reg_num_choices != num_registers[reg_type]: + print(' DECODE_MAPPED_REG({},{})'.\ + format(regno, reg_mapping), file=f) + regno += 1 + def implicit_register_key(reg): + return implicit_registers[reg] + for reg in sorted( + set([r for r in (iset.iset[tag]['rregs'].split(',') + \ + iset.iset[tag]['wregs'].split(',')) \ + if r in implicit_registers]), key=implicit_register_key): + print(' DECODE_IMPL_REG({},{})'.\ + format(regno, implicit_registers[reg]), file=f) + regno += 1 + if imms and imms[0][0].isupper(): + imms = reversed(imms) + for imm in imms: + if imm[0].isupper(): + immno = 1 + else: + immno = 0 + imm_type = imm[0] + imm_width = int(imm[1]) + imm_shift = imm[2] + if imm_shift: + imm_shift = int(imm_shift) + else: + imm_shift = 0 + if imm_type.islower(): + imm_letter = 'i' + else: + imm_letter = 'I' + remainder = imm_width + for m in reversed(list(re.finditer(imm_letter + '+', enc))): + remainder -= m.end() - m.start() + print(' DECODE_IMM({},{},{},{})'.\ + format(immno, m.end() - m.start(), m.start(), remainder), + file=f) + if remainder != 0: + if imm[2]: + imm[2] = ':' + imm[2] + raise Exception('Tag "{}" has an incorrect number of ' + \ + 'encoding bits for immediate "{}"'.\ + format(tag, ''.join(imm))) + if imm_type.lower() in 'sr': + print(' DECODE_IMM_SXT({},{})'.\ + format(immno, imm_width), file=f) + if imm_type.lower() == 'n': + print(' DECODE_IMM_NEG({},{})'.\ + format(immno, imm_width), file=f) + if imm_shift: + print(' DECODE_IMM_SHIFT({},{})'.\ + format(immno, imm_shift), file=f) + print(')', file=f) + +if __name__ == '__main__': + f = io.StringIO() + print_tree(f, dectree_normal) + print_tree(f, dectree_16bit) + if subinsn_groupings: + print_tree(f, dectree_subinsn_groupings) + for (name, dectree_subinsn) in sorted(dectree_subinsns.items()): + print_tree(f, dectree_subinsn) + for (name, dectree_ext) in sorted(dectree_extensions.items()): + print_tree(f, dectree_ext) + print_match_info(f) + print_op_info(f) + open(sys.argv[1], 'w').write(f.getvalue()) From patchwork Fri Oct 30 00:08:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 24/33] Hexagon (target/hexagon) macros Date: Thu, 29 Oct 2020 19:08:30 -0500 Message-Id: <1604016519-28065-25-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" macros to interface with the generator macros referenced in instruction semantics Signed-off-by: Taylor Simpson --- target/hexagon/macros.h | 591 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 591 insertions(+) create mode 100644 target/hexagon/macros.h diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h new file mode 100644 index 0000000..ff2ddd0 --- /dev/null +++ b/target/hexagon/macros.h @@ -0,0 +1,591 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_MACROS_H +#define HEXAGON_MACROS_H + +#include "cpu.h" +#include "hex_regs.h" +#include "reg_fields.h" + +#ifdef QEMU_GENERATE +#define READ_REG(dest, NUM) gen_read_reg(dest, NUM) +#define READ_PREG(dest, NUM) gen_read_preg(dest, (NUM)) +#else +#define READ_REG(NUM) (env->gpr[(NUM)]) +#define READ_PREG(NUM) (env->pred[NUM]) + +#define WRITE_RREG(NUM, VAL) log_reg_write(env, NUM, VAL, slot) +#define WRITE_PREG(NUM, VAL) log_pred_write(env, NUM, VAL) +#endif + +#define PCALIGN 4 +#define PCALIGN_MASK (PCALIGN - 1) + +#define GET_FIELD(FIELD, REGIN) \ + fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \ + reg_field_info[FIELD].offset) + +#ifdef QEMU_GENERATE +#define GET_USR_FIELD(FIELD, DST) \ + tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \ + reg_field_info[FIELD].offset, \ + reg_field_info[FIELD].width) + +#define TYPE_INT(X) __builtin_types_compatible_p(typeof(X), int) +#define TYPE_TCGV(X) __builtin_types_compatible_p(typeof(X), TCGv) +#define TYPE_TCGV_I64(X) __builtin_types_compatible_p(typeof(X), TCGv_i64) + +#define SET_USR_FIELD_FUNC(X) \ + __builtin_choose_expr(TYPE_INT(X), \ + gen_set_usr_fieldi, \ + __builtin_choose_expr(TYPE_TCGV(X), \ + gen_set_usr_field, (void)0)) +#define SET_USR_FIELD(FIELD, VAL) \ + SET_USR_FIELD_FUNC(VAL)(FIELD, VAL) +#else +#define GET_USR_FIELD(FIELD) \ + fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \ + reg_field_info[FIELD].offset) + +#define SET_USR_FIELD(FIELD, VAL) \ + fINSERT_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \ + reg_field_info[FIELD].offset, (VAL)) +#endif + +#ifdef QEMU_GENERATE +/* + * Section 5.5 of the Hexagon V67 Programmer's Reference Manual + * + * Slot 1 store with slot 0 load + * A slot 1 store operation with a slot 0 load operation can appear in a packet. + * The packet attribute :mem_noshuf inhibits the instruction reordering that + * would otherwise be done by the assembler. For example: + * { + * memw(R5) = R2 // slot 1 store + * R3 = memh(R6) // slot 0 load + * }:mem_noshuf + * Unlike most packetized operations, these memory operations are not executed + * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1 + * effectively executes first, followed by the load instruction in Slot 0. If + * the addresses of the two operations are overlapping, the load will receive + * the newly stored data. This feature is supported in processor versions + * V65 or greater. + * + * + * For qemu, we look for a load in slot 0 when there is a store in slot 1 + * in the same packet. When we see this, we call a helper that merges the + * bytes from the store buffer with the value loaded from memory. + */ +#define CHECK_NOSHUF \ + do { \ + if (insn->slot == 0 && pkt->pkt_has_store_s1) { \ + process_store(ctx, 1); \ + } \ + } while (0) + +#define MEM_LOAD1s(DST, VA) \ + do { \ + CHECK_NOSHUF; \ + tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \ + } while (0) +#define MEM_LOAD1u(DST, VA) \ + do { \ + CHECK_NOSHUF; \ + tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \ + } while (0) +#define MEM_LOAD2s(DST, VA) \ + do { \ + CHECK_NOSHUF; \ + tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \ + } while (0) +#define MEM_LOAD2u(DST, VA) \ + do { \ + CHECK_NOSHUF; \ + tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \ + } while (0) +#define MEM_LOAD4s(DST, VA) \ + do { \ + CHECK_NOSHUF; \ + tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \ + } while (0) +#define MEM_LOAD4u(DST, VA) \ + do { \ + CHECK_NOSHUF; \ + tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \ + } while (0) +#define MEM_LOAD8u(DST, VA) \ + do { \ + CHECK_NOSHUF; \ + tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \ + } while (0) +#else +#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA)) +#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA)) +#define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, slot, VA)) +#define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, slot, VA)) +#define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, slot, VA)) +#define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, slot, VA)) +#define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, slot, VA)) +#define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, slot, VA)) + +#define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT) +#define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT) +#define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT) +#define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT) +#endif + +#define CANCEL cancel_slot(env, slot) + +#define LOAD_CANCEL(EA) do { CANCEL; } while (0) + +#ifdef QEMU_GENERATE +static inline void gen_pred_cancel(TCGv pred, int slot_num) + { + TCGv slot_mask = tcg_const_tl(1 << slot_num); + TCGv tmp = tcg_temp_new(); + TCGv zero = tcg_const_tl(0); + TCGv one = tcg_const_tl(1); + tcg_gen_or_tl(slot_mask, hex_slot_cancelled, slot_mask); + tcg_gen_andi_tl(tmp, pred, 1); + tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero, + slot_mask, hex_slot_cancelled); + tcg_temp_free(slot_mask); + tcg_temp_free(tmp); + tcg_temp_free(zero); + tcg_temp_free(one); +} +#define PRED_LOAD_CANCEL(PRED, EA) \ + gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot) +#endif + +#define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); } + +#define fMAX(A, B) (((A) > (B)) ? (A) : (B)) + +#define fMIN(A, B) (((A) < (B)) ? (A) : (B)) + +#define fABS(A) (((A) < 0) ? (-(A)) : (A)) +#define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \ + REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG) +#define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \ + ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL) +#define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \ + (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8))) +#define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \ + (((HIBIT) - (LOWBIT) + 1) ? \ + extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \ + 0LL) + +#define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) + +#ifdef QEMU_GENERATE +#define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1) +#else +#define fLSBOLD(VAL) ((VAL) & 1) +#endif + +#ifdef QEMU_GENERATE +#define fLSBNEW(PVAL) tcg_gen_mov_tl(LSB, (PVAL)) +#define fLSBNEW0 fLSBNEW(0) +#define fLSBNEW1 fLSBNEW(1) +#else +#define fLSBNEW(PVAL) (PVAL) +#define fLSBNEW0 new_pred_value(env, 0) +#define fLSBNEW1 new_pred_value(env, 1) +#endif + +#ifdef QEMU_GENERATE +static inline void gen_logical_not(TCGv dest, TCGv src) +{ + TCGv one = tcg_const_tl(1); + TCGv zero = tcg_const_tl(0); + + tcg_gen_movcond_tl(TCG_COND_NE, dest, src, zero, zero, one); + + tcg_temp_free(one); + tcg_temp_free(zero); +} +#define fLSBOLDNOT(VAL) \ + do { \ + tcg_gen_andi_tl(LSB, (VAL), 1); \ + tcg_gen_xori_tl(LSB, LSB, 1); \ + } while (0) +#define fLSBNEWNOT(PNUM) \ + gen_logical_not(LSB, (PNUM)) +#else +#define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM)) +#define fLSBOLDNOT(VAL) (!fLSBOLD(VAL)) +#define fLSBNEW0NOT (!fLSBNEW0) +#define fLSBNEW1NOT (!fLSBNEW1) +#endif + +#define fNEWREG(RNUM) ((int32_t)(env->new_value[(RNUM)])) + +#define fNEWREG_ST(RNUM) (env->new_value[(RNUM)]) + +#define fSATUVALN(N, VAL) \ + ({ \ + fSET_OVERFLOW(); \ + ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \ + }) +#define fSATVALN(N, VAL) \ + ({ \ + fSET_OVERFLOW(); \ + ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \ + }) +#define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL) +#define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL) +#define fSATN(N, VAL) \ + ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL)) +#define fADDSAT64(DST, A, B) \ + do { \ + uint64_t __a = fCAST8u(A); \ + uint64_t __b = fCAST8u(B); \ + uint64_t __sum = __a + __b; \ + uint64_t __xor = __a ^ __b; \ + const uint64_t __mask = 0x8000000000000000ULL; \ + if (__xor & __mask) { \ + DST = __sum; \ + } \ + else if ((__a ^ __sum) & __mask) { \ + if (__sum & __mask) { \ + DST = 0x7FFFFFFFFFFFFFFFLL; \ + fSET_OVERFLOW(); \ + } else { \ + DST = 0x8000000000000000LL; \ + fSET_OVERFLOW(); \ + } \ + } else { \ + DST = __sum; \ + } \ + } while (0) +#define fSATUN(N, VAL) \ + ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL)) +#define fSATH(VAL) (fSATN(16, VAL)) +#define fSATUH(VAL) (fSATUN(16, VAL)) +#define fSATUB(VAL) (fSATUN(8, VAL)) +#define fSATB(VAL) (fSATN(8, VAL)) +#define fIMMEXT(IMM) (IMM = IMM) +#define fMUST_IMMEXT(IMM) fIMMEXT(IMM) + +#define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK) + +#define fREAD_LR() (READ_REG(HEX_REG_LR)) + +#define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A) +#define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A) +#define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A) + +#define fREAD_SP() (READ_REG(HEX_REG_SP)) +#define fREAD_LC0 (READ_REG(HEX_REG_LC0)) +#define fREAD_LC1 (READ_REG(HEX_REG_LC1)) +#define fREAD_SA0 (READ_REG(HEX_REG_SA0)) +#define fREAD_SA1 (READ_REG(HEX_REG_SA1)) +#define fREAD_FP() (READ_REG(HEX_REG_FP)) +#ifdef FIXME +/* Figure out how to get insn->extension_valid to helper */ +#define fREAD_GP() \ + (insn->extension_valid ? 0 : READ_REG(HEX_REG_GP)) +#else +#define fREAD_GP() READ_REG(HEX_REG_GP) +#endif +#define fREAD_PC() (READ_REG(HEX_REG_PC)) + +#define fREAD_NPC() (env->next_PC & (0xfffffffe)) + +#define fREAD_P0() (READ_PREG(0)) +#define fREAD_P3() (READ_PREG(3)) + +#define fCHECK_PCALIGN(A) + +#define fWRITE_NPC(A) write_new_pc(env, A) + +#define fBRANCH(LOC, TYPE) fWRITE_NPC(LOC) +#define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR) +#define fHINTJR(TARGET) { /* Not modelled in qemu */} +#define fCALL(A) \ + do { \ + fWRITE_LR(fREAD_NPC()); \ + fBRANCH(A, COF_TYPE_CALL); \ + } while (0) +#define fCALLR(A) \ + do { \ + fWRITE_LR(fREAD_NPC()); \ + fBRANCH(A, COF_TYPE_CALLR); \ + } while (0) +#define fWRITE_LOOP_REGS0(START, COUNT) \ + do { \ + WRITE_RREG(HEX_REG_LC0, COUNT); \ + WRITE_RREG(HEX_REG_SA0, START); \ + } while (0) +#define fWRITE_LOOP_REGS1(START, COUNT) \ + do { \ + WRITE_RREG(HEX_REG_LC1, COUNT); \ + WRITE_RREG(HEX_REG_SA1, START);\ + } while (0) +#define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL) +#define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL) + +#define fCARRY_FROM_ADD(A, B, C) carry_from_add64(A, B, C) + +#define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1) +#define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL)) +#define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG)) +#define fWRITE_P0(VAL) WRITE_PREG(0, VAL) +#define fWRITE_P1(VAL) WRITE_PREG(1, VAL) +#define fWRITE_P2(VAL) WRITE_PREG(2, VAL) +#define fWRITE_P3(VAL) WRITE_PREG(3, VAL) +#define fPART1(WORK) if (part1) { WORK; return; } +#define fCAST4u(A) ((uint32_t)(A)) +#define fCAST4s(A) ((int32_t)(A)) +#define fCAST8u(A) ((uint64_t)(A)) +#define fCAST8s(A) ((int64_t)(A)) +#define fCAST4_4s(A) ((int32_t)(A)) +#define fCAST4_4u(A) ((uint32_t)(A)) +#define fCAST4_8s(A) ((int64_t)((int32_t)(A))) +#define fCAST4_8u(A) ((uint64_t)((uint32_t)(A))) +#define fCAST8_8s(A) ((int64_t)(A)) +#define fCAST8_8u(A) ((uint64_t)(A)) +#define fCAST2_8s(A) ((int64_t)((int16_t)(A))) +#define fCAST2_8u(A) ((uint64_t)((uint16_t)(A))) +#define fZE8_16(A) ((int16_t)((uint8_t)(A))) +#define fSE8_16(A) ((int16_t)((int8_t)(A))) +#define fSE16_32(A) ((int32_t)((int16_t)(A))) +#define fZE16_32(A) ((uint32_t)((uint16_t)(A))) +#define fSE32_64(A) ((int64_t)((int32_t)(A))) +#define fZE32_64(A) ((uint64_t)((uint32_t)(A))) +#define fSE8_32(A) ((int32_t)((int8_t)(A))) +#define fZE8_32(A) ((int32_t)((uint8_t)(A))) +#define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B)) +#define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B)) +#define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B)) +#define fMPY8SS(A, B) (int)((short)(A) * (short)(B)) +#define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B)) +#define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B)) +#define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B)) +#define fMPY16US(A, B) fMPY16SU(B, A) +#define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B)) +#define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B)) +#define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B)) +#define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B)) +#define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B)) +#define fROUND(A) (A + 0x8000) +#define fCLIP(DST, SRC, U) \ + do { \ + int32_t maxv = (1 << U) - 1; \ + int32_t minv = -(1 << U); \ + DST = fMIN(maxv, fMAX(SRC, minv)); \ + } while (0) +#define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A))) +#define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1)))))) +#define fCRNDN(A, N) (conv_round(A, N)) +#define fADD128(A, B) (int128_add(A, B)) +#define fSUB128(A, B) (int128_sub(A, B)) +#define fSHIFTR128(A, B) (int128_rshift(A, B)) +#define fSHIFTL128(A, B) (int128_lshift(A, B)) +#define fAND128(A, B) (int128_and(A, B)) +#define fCAST8S_16S(A) (int128_exts64(A)) +#define fCAST16S_8S(A) (int128_getlo(A)) + +#define fEA_RI(REG, IMM) \ + do { \ + EA = REG + IMM; \ + } while (0) +#define fEA_RRs(REG, REG2, SCALE) \ + do { \ + EA = REG + (REG2 << SCALE); \ + } while (0) +#define fEA_IRs(IMM, REG, SCALE) \ + do { \ + EA = IMM + (REG << SCALE); \ + } while (0) + +#ifdef QEMU_GENERATE +#define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM) +#define fEA_REG(REG) tcg_gen_mov_tl(EA, REG) +#define fPM_I(REG, IMM) tcg_gen_addi_tl(REG, REG, IMM) +#define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL) +#else +#define fEA_IMM(IMM) do { EA = (IMM); } while (0) +#define fEA_REG(REG) do { EA = (REG); } while (0) +#define fEA_GPI(IMM) do { EA = (fREAD_GP() + (IMM)); } while (0) +#define fPM_I(REG, IMM) do { REG = REG + (IMM); } while (0) +#define fPM_M(REG, MVAL) do { REG = REG + (MVAL); } while (0) +#endif +#define fSCALE(N, A) (((int64_t)(A)) << N) +#define fSATW(A) fSATN(32, ((long long)A)) +#define fSAT(A) fSATN(32, (A)) +#define fSAT_ORIG_SHL(A, ORIG_REG) \ + ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \ + ? fSATVALN(32, ((int32_t)(ORIG_REG))) \ + : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \ + : fSAT(A))) +#define fPASS(A) A +#define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ + : (fCAST##REGSTYPE(SRC) << (SHAMT))) +#define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \ + fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s) +#define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \ + fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u) +#define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ + : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC))) +#define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \ + : (fCAST##REGSTYPE(SRC) >> (SHAMT))) +#define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \ + fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s) +#define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \ + fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u) +#define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \ + << ((-(SHAMT)) - 1)) << 1, (SRC)) \ + : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))) +#define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT)) +#define fLSHIFTR(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) >= 64) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT))) +#define fROTL(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \ + ((fCAST##REGSTYPE##u(SRC) >> \ + ((sizeof(SRC) * 8) - (SHAMT)))))) +#define fROTR(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \ + ((fCAST##REGSTYPE##u(SRC) << \ + ((sizeof(SRC) * 8) - (SHAMT)))))) +#define fASHIFTL(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) >= 64) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT))) + +#ifdef QEMU_GENERATE +#define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) +#else +#define fLOAD(NUM, SIZE, SIGN, EA, DST) \ + DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA) +#endif + +#define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE) + +#define fGET_FRAMEKEY() READ_REG(HEX_REG_FRAMEKEY) +#define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32)) +#define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL) + +#ifdef CONFIG_USER_ONLY +#define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */ +#else +/* System mode not implemented yet */ +#define fFRAMECHECK(ADDR, EA) g_assert_not_reached(); +#endif + +#ifdef QEMU_GENERATE +#define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \ + gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx); +#endif + +#define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot) + +#ifdef QEMU_GENERATE +#define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \ + gen_store_conditional##SIZE(env, ctx, PdN, PRED, EA, SRC); +#endif + +#define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff)) +#define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff)) + +#define fSETBYTE(N, DST, VAL) \ + do { \ + DST = (DST & ~(0x0ffLL << ((N) * 8))) | \ + (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \ + } while (0) +#define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff)) +#define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff)) +#define fSETHALF(N, DST, VAL) \ + do { \ + DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \ + (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \ + } while (0) +#define fSETHALFw fSETHALF +#define fSETHALFd fSETHALF + +#define fGETWORD(N, SRC) \ + ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) +#define fGETUWORD(N, SRC) \ + ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) + +#define fSETWORD(N, DST, VAL) \ + do { \ + DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \ + (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \ + } while (0) + +#define fSETBIT(N, DST, VAL) \ + do { \ + DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \ + } while (0) + +#define fGETBIT(N, SRC) (((SRC) >> N) & 1) +#define fSETBITS(HI, LO, DST, VAL) \ + do { \ + int j; \ + for (j = LO; j <= HI; j++) { \ + fSETBIT(j, DST, VAL); \ + } \ + } while (0) +#define fCOUNTONES_4(VAL) ctpop32(VAL) +#define fCOUNTONES_8(VAL) ctpop64(VAL) +#define fBREV_8(VAL) revbit64(VAL) +#define fBREV_4(VAL) revbit32(VAL) +#define fCL1_8(VAL) clo64(VAL) +#define fCL1_4(VAL) clo32(VAL) +#define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN) +#define fDEINTERLEAVE(MIXED) deinterleave(MIXED) +#define fHIDE(A) A +#define fCONSTLL(A) A##LL +#define fECHO(A) (A) + +#define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0) + +#define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \ + ((VAL) << reg_field_info[FIELD].offset) +#define fGET_REG_FIELD_MASK(FIELD) \ + (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset) +#define fREAD_REG_FIELD(REG, FIELD) \ + fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \ + reg_field_info[FIELD].width, \ + reg_field_info[FIELD].offset) +#define fGET_FIELD(VAL, FIELD) +#define fSET_FIELD(VAL, FIELD, NEWVAL) +#define fBARRIER() +#define fSYNCH() +#define fISYNC() +#define fDCFETCH(REG) \ + do { (void)REG; } while (0) /* Nothing to do in qemu */ +#define fICINVA(REG) \ + do { (void)REG; } while (0) /* Nothing to do in qemu */ +#define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS) +#define fDCCLEANA(REG) \ + do { (void)REG; } while (0) /* Nothing to do in qemu */ +#define fDCCLEANINVA(REG) \ + do { (void)REG; } while (0) /* Nothing to do in qemu */ + +#define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0) + +#define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \ + STRBITNUM) /* Nothing */ + + +#endif From patchwork Fri Oct 30 00:08:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEC1DC2D0A3 for ; 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29 Oct 2020 17:08:46 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 31015411F; Thu, 29 Oct 2020 19:08:46 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 25/33] Hexagon (target/hexagon) instruction classes Date: Thu, 29 Oct 2020 19:08:31 -0500 Message-Id: <1604016519-28065-26-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Determine legal VLIW slots for each instruction Signed-off-by: Taylor Simpson --- target/hexagon/iclass.h | 50 ++++++++++++++++++++++++++ target/hexagon/iclass.c | 73 ++++++++++++++++++++++++++++++++++++++ target/hexagon/imported/iclass.def | 51 ++++++++++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 target/hexagon/iclass.h create mode 100644 target/hexagon/iclass.c create mode 100644 target/hexagon/imported/iclass.def diff --git a/target/hexagon/iclass.h b/target/hexagon/iclass.h new file mode 100644 index 0000000..b57f11d --- /dev/null +++ b/target/hexagon/iclass.h @@ -0,0 +1,50 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_ICLASS_H +#define HEXAGON_ICLASS_H + +#include "opcodes.h" + +#define ICLASS_FROM_TYPE(TYPE) ICLASS_##TYPE + +enum { + +#define DEF_PP_ICLASS32(TYPE, SLOTS, UNITS) ICLASS_FROM_TYPE(TYPE), +#define DEF_EE_ICLASS32(TYPE, SLOTS, UNITS) ICLASS_FROM_TYPE(TYPE), +#include "imported/iclass.def" +#undef DEF_PP_ICLASS32 +#undef DEF_EE_ICLASS32 + + ICLASS_FROM_TYPE(COPROC_VX), + ICLASS_FROM_TYPE(COPROC_VMEM), + NUM_ICLASSES +}; + +typedef enum { + SLOTS_0 = (1 << 0), + SLOTS_1 = (1 << 1), + SLOTS_2 = (1 << 2), + SLOTS_3 = (1 << 3), + SLOTS_01 = SLOTS_0 | SLOTS_1, + SLOTS_23 = SLOTS_2 | SLOTS_3, + SLOTS_0123 = SLOTS_0 | SLOTS_1 | SLOTS_2 | SLOTS_3, +} SlotMask; + +extern SlotMask find_iclass_slots(Opcode opcode, int itype); + +#endif diff --git a/target/hexagon/iclass.c b/target/hexagon/iclass.c new file mode 100644 index 0000000..05117a9 --- /dev/null +++ b/target/hexagon/iclass.c @@ -0,0 +1,73 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "iclass.h" + +static const SlotMask iclass_info[] = { + +#define DEF_PP_ICLASS32(TYPE, SLOTS, UNITS) \ + [ICLASS_FROM_TYPE(TYPE)] = SLOTS_##SLOTS, +#define DEF_EE_ICLASS32(TYPE, SLOTS, UNITS) \ + [ICLASS_FROM_TYPE(TYPE)] = SLOTS_##SLOTS, +#include "imported/iclass.def" +#undef DEF_PP_ICLASS32 +#undef DEF_EE_ICLASS32 +}; + +SlotMask find_iclass_slots(Opcode opcode, int itype) +{ + /* There are some exceptions to what the iclass dictates */ + if (GET_ATTRIB(opcode, A_ICOP)) { + return SLOTS_2; + } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT0ONLY)) { + return SLOTS_0; + } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT1ONLY)) { + return SLOTS_1; + } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT2ONLY)) { + return SLOTS_2; + } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT3ONLY)) { + return SLOTS_3; + } else if (GET_ATTRIB(opcode, A_COF) && + GET_ATTRIB(opcode, A_INDIRECT) && + !GET_ATTRIB(opcode, A_MEMLIKE) && + !GET_ATTRIB(opcode, A_MEMLIKE_PACKET_RULES)) { + return SLOTS_2; + } else if (GET_ATTRIB(opcode, A_RESTRICT_NOSLOT1)) { + return SLOTS_0; + } else if ((opcode == J2_trap0) || + (opcode == Y2_isync) || + (opcode == J4_hintjumpr)) { + return SLOTS_2; + } else if ((itype == ICLASS_V2LDST) && (GET_ATTRIB(opcode, A_STORE))) { + return SLOTS_01; + } else if ((itype == ICLASS_V2LDST) && (!GET_ATTRIB(opcode, A_STORE))) { + return SLOTS_01; + } else if (GET_ATTRIB(opcode, A_CRSLOT23)) { + return SLOTS_23; + } else if (GET_ATTRIB(opcode, A_RESTRICT_PREFERSLOT0)) { + return SLOTS_0; + } else if (GET_ATTRIB(opcode, A_SUBINSN)) { + return SLOTS_01; + } else if (GET_ATTRIB(opcode, A_CALL)) { + return SLOTS_23; + } else if ((opcode == J4_jumpseti) || (opcode == J4_jumpsetr)) { + return SLOTS_23; + } else { + return iclass_info[itype]; + } +} diff --git a/target/hexagon/imported/iclass.def b/target/hexagon/imported/iclass.def new file mode 100644 index 0000000..92b0406 --- /dev/null +++ b/target/hexagon/imported/iclass.def @@ -0,0 +1,51 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* DEF_*(TYPE,SLOTS,UNITS) */ +DEF_PP_ICLASS32(EXTENDER,0123,LDST|SUNIT|MUNIT) /* 0 */ +DEF_PP_ICLASS32(CJ,0123,CTRLFLOW) /* 1 */ +DEF_PP_ICLASS32(NCJ,01,LDST|CTRLFLOW) /* 2 */ +DEF_PP_ICLASS32(V4LDST,01,LDST) /* 3 */ +DEF_PP_ICLASS32(V2LDST,01,LDST) /* 4 */ +DEF_PP_ICLASS32(J,0123,CTRLFLOW) /* 5 */ +DEF_PP_ICLASS32(CR,3,SUNIT) /* 6 */ +DEF_PP_ICLASS32(ALU32_2op,0123,LDST|SUNIT|MUNIT) /* 7 */ +DEF_PP_ICLASS32(S_2op,23,SUNIT|MUNIT) /* 8 */ +DEF_PP_ICLASS32(LD,01,LDST) /* 9 */ +DEF_PP_ICLASS32(ST,01,LDST) /* 10 */ +DEF_PP_ICLASS32(ALU32_ADDI,0123,LDST|SUNIT|MUNIT) /* 11 */ +DEF_PP_ICLASS32(S_3op,23,SUNIT|MUNIT) /* 12 */ +DEF_PP_ICLASS32(ALU64,23,SUNIT|MUNIT) /* 13 */ +DEF_PP_ICLASS32(M,23,SUNIT|MUNIT) /* 14 */ +DEF_PP_ICLASS32(ALU32_3op,0123,LDST|SUNIT|MUNIT) /* 15 */ + +DEF_EE_ICLASS32(EE0,01,INVALID) /* 0 */ +DEF_EE_ICLASS32(EE1,01,INVALID) /* 1 */ +DEF_EE_ICLASS32(EE2,01,INVALID) /* 2 */ +DEF_EE_ICLASS32(EE3,01,INVALID) /* 3 */ +DEF_EE_ICLASS32(EE4,01,INVALID) /* 4 */ +DEF_EE_ICLASS32(EE5,01,INVALID) /* 5 */ +DEF_EE_ICLASS32(EE6,01,INVALID) /* 6 */ +DEF_EE_ICLASS32(EE7,01,INVALID) /* 7 */ +DEF_EE_ICLASS32(EE8,01,INVALID) /* 8 */ +DEF_EE_ICLASS32(EE9,01,INVALID) /* 9 */ +DEF_EE_ICLASS32(EEA,01,INVALID) /* 10 */ +DEF_EE_ICLASS32(EEB,01,INVALID) /* 11 */ +DEF_EE_ICLASS32(EEC,01,INVALID) /* 12 */ +DEF_EE_ICLASS32(EED,01,INVALID) /* 13 */ +DEF_EE_ICLASS32(EEE,01,INVALID) /* 14 */ +DEF_EE_ICLASS32(EEF,01,INVALID) /* 15 */ From patchwork Fri Oct 30 00:08:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98499C2D0A3 for ; Fri, 30 Oct 2020 00:59:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E5D662071A for ; Fri, 30 Oct 2020 00:59:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="xRjXtwNp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E5D662071A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kYIlb-00023z-RW for qemu-devel@archiver.kernel.org; Thu, 29 Oct 2020 20:59:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kYHys-0004Bo-9w for qemu-devel@nongnu.org; Thu, 29 Oct 2020 20:09:22 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:39660) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kYHyp-0005Qi-5q for qemu-devel@nongnu.org; Thu, 29 Oct 2020 20:09:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1604016559; x=1635552559; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MP0p+d0tCPd8RO+KWYmjChAvFvfuCSZjYWt38Th6n6c=; b=xRjXtwNpRGn7znmd8sLjS8MdP1QS1puOEQbR+k5RTftLnHVhpvh0gdi8 Dla9izDo8DI2u2kdAYAvkluZwFq6NpTggLpOIobCQj4h3qo3KEPVk6nyo qRZltq+lV7qRa6C5dIX+PZeiU2NxSPopKOyZY1+2q+scjHrb2bKaUxvEK s=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 29 Oct 2020 17:08:47 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 29 Oct 2020 17:08:46 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 7979A4118; Thu, 29 Oct 2020 19:08:46 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 28/33] Hexagon (target/hexagon) TCG for floating point instructions Date: Thu, 29 Oct 2020 19:08:34 -0500 Message-Id: <1604016519-28065-29-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The imported code uses host floating point. We override them to use qemu softfloat Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 121 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 35568d1..d605b1e 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -195,4 +195,125 @@ #define fGEN_TCG_S4_stored_locked(SHORTCODE) \ do { SHORTCODE; READ_PREG(PdV, PdN); } while (0) +/* Floating point */ +#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ + gen_helper_conv_sf2df(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \ + gen_helper_conv_df2sf(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \ + gen_helper_conv_uw2sf(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \ + gen_helper_conv_uw2df(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \ + gen_helper_conv_w2sf(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_w2df(SHORTCODE) \ + gen_helper_conv_w2df(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \ + gen_helper_conv_ud2sf(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \ + gen_helper_conv_ud2df(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \ + gen_helper_conv_d2sf(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_d2df(SHORTCODE) \ + gen_helper_conv_d2df(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \ + gen_helper_conv_sf2uw(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \ + gen_helper_conv_sf2w(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \ + gen_helper_conv_sf2ud(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \ + gen_helper_conv_sf2d(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \ + gen_helper_conv_df2uw(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2w(SHORTCODE) \ + gen_helper_conv_df2w(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \ + gen_helper_conv_df2ud(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2d(SHORTCODE) \ + gen_helper_conv_df2d(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \ + gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \ + gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \ + gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \ + gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \ + gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \ + gen_helper_conv_df2w_chop(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \ + gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \ + gen_helper_conv_df2d_chop(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_sfadd(SHORTCODE) \ + gen_helper_sfadd(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfsub(SHORTCODE) \ + gen_helper_sfsub(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \ + gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \ + gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpge(SHORTCODE) \ + gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \ + gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfmax(SHORTCODE) \ + gen_helper_sfmax(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfmin(SHORTCODE) \ + gen_helper_sfmin(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfclass(SHORTCODE) \ + do { \ + TCGv imm = tcg_const_tl(uiV); \ + gen_helper_sfclass(PdV, cpu_env, RsV, imm); \ + tcg_temp_free(imm); \ + } while (0) +#define fGEN_TCG_F2_sffixupn(SHORTCODE) \ + gen_helper_sffixupn(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sffixupd(SHORTCODE) \ + gen_helper_sffixupd(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sffixupr(SHORTCODE) \ + gen_helper_sffixupr(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_dfadd(SHORTCODE) \ + gen_helper_dfadd(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfsub(SHORTCODE) \ + gen_helper_dfsub(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfmax(SHORTCODE) \ + gen_helper_dfmax(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfmin(SHORTCODE) \ + gen_helper_dfmin(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \ + gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \ + gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpge(SHORTCODE) \ + gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \ + gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfclass(SHORTCODE) \ + do { \ + TCGv imm = tcg_const_tl(uiV); \ + gen_helper_dfclass(PdV, cpu_env, RssV, imm); \ + tcg_temp_free(imm); \ + } while (0) +#define fGEN_TCG_F2_sfmpy(SHORTCODE) \ + gen_helper_sfmpy(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sffma(SHORTCODE) \ + gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV) +#define fGEN_TCG_F2_sffma_sc(SHORTCODE) \ + gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV) +#define fGEN_TCG_F2_sffms(SHORTCODE) \ + gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV) +#define fGEN_TCG_F2_sffma_lib(SHORTCODE) \ + gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV) +#define fGEN_TCG_F2_sffms_lib(SHORTCODE) \ + gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV) + +#define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \ + gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \ + gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV) + #endif From patchwork Thu Oct 29 23:58:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6072CC55179 for ; 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29 Oct 2020 16:58:55 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id CF28B410F; Thu, 29 Oct 2020 18:58:55 -0500 (CDT) From: Taylor Simpson To: tsimpson@quicinc.com Subject: [RFC PATCH v5 29/33] Hexagon (target/hexagon) translation Date: Thu, 29 Oct 2020 18:58:46 -0500 Message-Id: <1604015931-23005-30-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604015931-23005-1-git-send-email-tsimpson@quicinc.com> References: <1604015931-23005-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:All patches CC here" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Read the instruction memory Create a packet data structure Generate TCG code for the start of the packet Invoke the generate function for each instruction Generate TCG code for the end of the packet Signed-off-by: Taylor Simpson --- target/hexagon/translate.h | 85 ++++++ target/hexagon/translate.c | 687 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 772 insertions(+) create mode 100644 target/hexagon/translate.h create mode 100644 target/hexagon/translate.c diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h new file mode 100644 index 0000000..c91d89d --- /dev/null +++ b/target/hexagon/translate.h @@ -0,0 +1,85 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_TRANSLATE_H +#define HEXAGON_TRANSLATE_H + +#include "qemu/bitmap.h" +#include "cpu.h" +#include "exec/translator.h" +#include "tcg/tcg-op.h" +#include "internal.h" + +typedef struct DisasContext { + DisasContextBase base; + uint32_t mem_idx; + int reg_log[REG_WRITES_MAX]; + int reg_log_idx; + DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); + int preg_log[PRED_WRITES_MAX]; + int preg_log_idx; + uint8_t store_width[STORES_MAX]; + uint8_t s1_store_processed; +} DisasContext; + +static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) +{ +#if HEX_DEBUG + if (test_bit(rnum, ctx->regs_written)) { + HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum); + } +#endif + ctx->reg_log[ctx->reg_log_idx] = rnum; + ctx->reg_log_idx++; + set_bit(rnum, ctx->regs_written); +} + +static inline void ctx_log_pred_write(DisasContext *ctx, int pnum) +{ + ctx->preg_log[ctx->preg_log_idx] = pnum; + ctx->preg_log_idx++; +} + +static inline bool is_preloaded(DisasContext *ctx, int num) +{ + return test_bit(num, ctx->regs_written); +} + +extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; +extern TCGv hex_pred[NUM_PREGS]; +extern TCGv hex_next_PC; +extern TCGv hex_this_PC; +extern TCGv hex_slot_cancelled; +extern TCGv hex_branch_taken; +extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; +extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; +extern TCGv hex_new_pred_value[NUM_PREGS]; +extern TCGv hex_pred_written; +extern TCGv hex_store_addr[STORES_MAX]; +extern TCGv hex_store_width[STORES_MAX]; +extern TCGv hex_store_val32[STORES_MAX]; +extern TCGv_i64 hex_store_val64[STORES_MAX]; +extern TCGv hex_dczero_addr; +extern TCGv hex_llsc_addr; +extern TCGv hex_llsc_val; +extern TCGv_i64 hex_llsc_val_i64; + +extern void gen_exception(int excp); +extern void gen_exception_debug(void); + +extern void process_store(DisasContext *ctx, int slot_num); +#endif diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c new file mode 100644 index 0000000..efc51ce --- /dev/null +++ b/target/hexagon/translate.c @@ -0,0 +1,687 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#define QEMU_GENERATE +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg/tcg-op.h" +#include "exec/cpu_ldst.h" +#include "exec/log.h" +#include "internal.h" +#include "attribs.h" +#include "insn.h" +#include "decode.h" +#include "translate.h" +#include "printinsn.h" + +TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; +TCGv hex_pred[NUM_PREGS]; +TCGv hex_next_PC; +TCGv hex_this_PC; +TCGv hex_slot_cancelled; +TCGv hex_branch_taken; +TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; +#if HEX_DEBUG +TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; +#endif +TCGv hex_new_pred_value[NUM_PREGS]; +TCGv hex_pred_written; +TCGv hex_store_addr[STORES_MAX]; +TCGv hex_store_width[STORES_MAX]; +TCGv hex_store_val32[STORES_MAX]; +TCGv_i64 hex_store_val64[STORES_MAX]; +TCGv hex_pkt_has_store_s1; +TCGv hex_dczero_addr; +TCGv hex_llsc_addr; +TCGv hex_llsc_val; +TCGv_i64 hex_llsc_val_i64; + +static const char * const hexagon_prednames[] = { + "p0", "p1", "p2", "p3" +}; + +void gen_exception(int excp) +{ + TCGv_i32 helper_tmp = tcg_const_i32(excp); + gen_helper_raise_exception(cpu_env, helper_tmp); + tcg_temp_free_i32(helper_tmp); +} + +void gen_exception_debug(void) +{ + gen_exception(EXCP_DEBUG); +} + +#if HEX_DEBUG +#define PACKET_BUFFER_LEN 1028 +static void print_pkt(Packet *pkt) +{ + char buf[PACKET_BUFFER_LEN]; + snprint_a_pkt_debug(buf, PACKET_BUFFER_LEN, pkt); + HEX_DEBUG_LOG("%s", buf); +} +#define HEX_DEBUG_PRINT_PKT(pkt) print_pkt(pkt) +#else +#define HEX_DEBUG_PRINT_PKT(pkt) /* nothing */ +#endif + +static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, + uint32_t words[]) +{ + bool found_end = false; + int nwords; + + memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); + for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { + words[nwords] = cpu_ldl_code(env, + ctx->base.pc_next + nwords * sizeof(uint32_t)); + found_end = is_packet_end(words[nwords]); + } + if (!found_end) { + /* Read too many words without finding the end */ + return 0; + } + + /* Check for page boundary crossing */ + int max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t); + if (nwords > max_words) { + /* We can only cross a page boundary at the beginning of a TB */ + g_assert(ctx->base.num_insns == 1); + } + + HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next); + HEX_DEBUG_LOG(" words = { "); + for (int i = 0; i < nwords; i++) { + HEX_DEBUG_LOG("0x%x, ", words[i]); + } + HEX_DEBUG_LOG("}\n"); + + return nwords; +} + +static void gen_start_packet(DisasContext *ctx, Packet *pkt) +{ + target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes; + int i; + + /* Clear out the disassembly context */ + ctx->reg_log_idx = 0; + bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); + ctx->preg_log_idx = 0; + for (i = 0; i < STORES_MAX; i++) { + ctx->store_width[i] = 0; + } + tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); + ctx->s1_store_processed = 0; + +#if HEX_DEBUG + /* Handy place to set a breakpoint before the packet executes */ + gen_helper_debug_start_packet(cpu_env); + tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next); +#endif + + /* Initialize the runtime state for packet semantics */ + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); + tcg_gen_movi_tl(hex_slot_cancelled, 0); + if (pkt->pkt_has_cof) { + tcg_gen_movi_tl(hex_branch_taken, 0); + tcg_gen_movi_tl(hex_next_PC, next_PC); + } + tcg_gen_movi_tl(hex_pred_written, 0); +} + +/* + * The LOG_*_WRITE macros mark most of the writes in a packet + * However, there are some implicit writes marked as attributes + * of the applicable instructions. + */ +static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn, + int attrib, int rnum) +{ + if (GET_ATTRIB(insn->opcode, attrib)) { + int is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); + if (is_predicated && !is_preloaded(ctx, rnum)) { + tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]); + } + + ctx_log_reg_write(ctx, rnum); + } +} + +static void mark_implicit_pred_write(DisasContext *ctx, Insn *insn, + int attrib, int pnum) +{ + if (GET_ATTRIB(insn->opcode, attrib)) { + ctx_log_pred_write(ctx, pnum); + } +} + +static void mark_implicit_writes(DisasContext *ctx, Insn *insn) +{ + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP, HEX_REG_FP); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP, HEX_REG_SP); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LR, HEX_REG_LR); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); + mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); + + mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0); + mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1); + mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2); + mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P3, 3); +} + +static void gen_insn(CPUHexagonState *env, DisasContext *ctx, + Insn *insn, Packet *pkt) +{ + if (insn->generate) { + mark_implicit_writes(ctx, insn); + insn->generate(env, ctx, insn, pkt); + } else { + gen_exception(HEX_EXCP_INVALID_OPCODE); + ctx->base.is_jmp = DISAS_NORETURN; + } +} + +/* + * Helpers for generating the packet commit + */ +static void gen_reg_writes(DisasContext *ctx) +{ + int i; + + for (i = 0; i < ctx->reg_log_idx; i++) { + int reg_num = ctx->reg_log[i]; + + tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]); + } +} + +static void gen_pred_writes(DisasContext *ctx, Packet *pkt) +{ + /* Early exit if the log is empty */ + if (!ctx->preg_log_idx) { + return; + } + + TCGv zero = tcg_const_tl(0); + TCGv control_reg = tcg_temp_new(); + TCGv pval = tcg_temp_new(); + int i; + + /* + * Only endloop instructions will conditionally + * write a predicate. If there are no endloop + * instructions, we can use the non-conditional + * write of the predicates. + */ + if (pkt->pkt_has_endloop) { + TCGv pred_written = tcg_temp_new(); + for (i = 0; i < ctx->preg_log_idx; i++) { + int pred_num = ctx->preg_log[i]; + + tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num); + tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num], + pred_written, zero, + hex_new_pred_value[pred_num], + hex_pred[pred_num]); + } + tcg_temp_free(pred_written); + } else { + for (i = 0; i < ctx->preg_log_idx; i++) { + int pred_num = ctx->preg_log[i]; + tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]); +#if HEX_DEBUG + /* Do this so HELPER(debug_commit_end) will know */ + tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pred_num); +#endif + } + } + + tcg_temp_free(zero); + tcg_temp_free(control_reg); + tcg_temp_free(pval); +} + +#if HEX_DEBUG +static inline void gen_check_store_width(DisasContext *ctx, int slot_num) +{ + TCGv slot = tcg_const_tl(slot_num); + TCGv check = tcg_const_tl(ctx->store_width[slot_num]); + gen_helper_debug_check_store_width(cpu_env, slot, check); + tcg_temp_free(slot); + tcg_temp_free(check); +} +#define HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num) \ + gen_check_store_width(ctx, slot_num) +#else +#define HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num) /* nothing */ +#endif + +void process_store(DisasContext *ctx, int slot_num) +{ + /* + * We may have already processed this store + * See CHECK_NOSHUF in macros.h + */ + if (slot_num == 1 && ctx->s1_store_processed) { + return; + } + ctx->s1_store_processed = 1; + + TCGv cancelled = tcg_temp_new(); + TCGLabel *label_end = gen_new_label(); + + /* Don't do anything if the slot was cancelled */ + tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); + tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); + tcg_temp_free(cancelled); + { + TCGv address = tcg_temp_local_new(); + tcg_gen_mov_tl(address, hex_store_addr[slot_num]); + + /* + * If we know the width from the DisasContext, we can + * generate much cleaner code. + * Unfortunately, not all instructions execute the fSTORE + * macro during code generation. Anything that uses the + * generic helper will have this problem. Instructions + * that use fWRAP to generate proper TCG code will be OK. + */ + switch (ctx->store_width[slot_num]) { + case 1: + HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num); + tcg_gen_qemu_st8(hex_store_val32[slot_num], + hex_store_addr[slot_num], + ctx->mem_idx); + break; + case 2: + HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num); + tcg_gen_qemu_st16(hex_store_val32[slot_num], + hex_store_addr[slot_num], + ctx->mem_idx); + break; + case 4: + HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num); + tcg_gen_qemu_st32(hex_store_val32[slot_num], + hex_store_addr[slot_num], + ctx->mem_idx); + break; + case 8: + HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num); + tcg_gen_qemu_st64(hex_store_val64[slot_num], + hex_store_addr[slot_num], + ctx->mem_idx); + break; + default: + { + /* + * If we get to here, we don't know the width at + * TCG generation time, we'll use a helper to + * avoid branching based on the width at runtime. + */ + TCGv slot = tcg_const_tl(slot_num); + gen_helper_commit_store(cpu_env, slot); + tcg_temp_free(slot); + } + } + tcg_temp_free(address); + } + gen_set_label(label_end); +} + +static void process_store_log(DisasContext *ctx, Packet *pkt) +{ + /* + * When a packet has two stores, the hardware processes + * slot 1 and then slot 2. This will be important when + * the memory accesses overlap. + */ + if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) { + process_store(ctx, 1); + } + if (pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa) { + process_store(ctx, 0); + } +} + +/* Zero out a 32-bit cache line */ +static void process_dczeroa(DisasContext *ctx, Packet *pkt) +{ + if (pkt->pkt_has_dczeroa) { + /* Store 32 bytes of zero starting at (addr & ~0x1f) */ + TCGv addr = tcg_temp_new(); + TCGv_i64 zero = tcg_const_i64(0); + + tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f); + tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + + tcg_temp_free(addr); + tcg_temp_free_i64(zero); + } +} + +static void gen_exec_counters(Packet *pkt) +{ + int num_insns = pkt->num_insns; + int num_real_insns = 0; + int i; + + for (i = 0; i < num_insns; i++) { + if (!pkt->insn[i].is_endloop && + !pkt->insn[i].part1 && + !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { + num_real_insns++; + } + } + + tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], + hex_gpr[HEX_REG_QEMU_PKT_CNT], 1); + tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], + hex_gpr[HEX_REG_QEMU_INSN_CNT], num_real_insns); +} + +static void gen_commit_packet(DisasContext *ctx, Packet *pkt) +{ + gen_reg_writes(ctx); + gen_pred_writes(ctx, pkt); + process_store_log(ctx, pkt); + process_dczeroa(ctx, pkt); + gen_exec_counters(pkt); +#if HEX_DEBUG + { + TCGv has_st0 = + tcg_const_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); + TCGv has_st1 = + tcg_const_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); + + /* Handy place to set a breakpoint at the end of execution */ + gen_helper_debug_commit_end(cpu_env, has_st0, has_st1); + + tcg_temp_free(has_st0); + tcg_temp_free(has_st1); + } +#endif + + if (pkt->pkt_has_cof) { + ctx->base.is_jmp = DISAS_NORETURN; + } +} + +static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) +{ + uint32_t words[PACKET_WORDS_MAX]; + int nwords; + Packet pkt; + int i; + + nwords = read_packet_words(env, ctx, words); + if (!nwords) { + gen_exception(HEX_EXCP_INVALID_PACKET); + ctx->base.is_jmp = DISAS_NORETURN; + return; + } + + if (decode_packet(nwords, words, &pkt, false) > 0) { + HEX_DEBUG_PRINT_PKT(&pkt); + gen_start_packet(ctx, &pkt); + for (i = 0; i < pkt.num_insns; i++) { + gen_insn(env, ctx, &pkt.insn[i], &pkt); + } + gen_commit_packet(ctx, &pkt); + ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; + } else { + gen_exception(HEX_EXCP_INVALID_PACKET); + ctx->base.is_jmp = DISAS_NORETURN; + } +} + +static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + ctx->mem_idx = MMU_USER_IDX; +} + +static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + +static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(ctx->base.pc_next); +} + +static bool hexagon_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); + ctx->base.is_jmp = DISAS_NORETURN; + gen_exception_debug(); + /* + * The address covered by the breakpoint must be included in + * [tb->pc, tb->pc + tb->size) in order to for it to be + * properly cleared -- thus we increment the PC here so that + * the logic setting tb->size below does the right thing. + */ + ctx->base.pc_next += 4; + return true; +} + +static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) +{ + target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; + bool found_end = false; + int nwords; + + for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { + uint32_t word = cpu_ldl_code(env, + ctx->base.pc_next + nwords * sizeof(uint32_t)); + found_end = is_packet_end(word); + } + uint32_t next_ptr = ctx->base.pc_next + nwords * sizeof(uint32_t); + return found_end && next_ptr - page_start >= TARGET_PAGE_SIZE; +} + +static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPUHexagonState *env = cpu->env_ptr; + + decode_and_translate_packet(env, ctx); + + if (ctx->base.is_jmp == DISAS_NEXT) { + target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; + target_ulong bytes_max = PACKET_WORDS_MAX * sizeof(target_ulong); + + if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE || + (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - bytes_max && + pkt_crosses_page(env, ctx))) { + ctx->base.is_jmp = DISAS_TOO_MANY; + } + + /* + * The CPU log is used to compare against LLDB single stepping, + * so end the TLB after every packet. + */ + HexagonCPU *hex_cpu = container_of(env, HexagonCPU, env); + if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) { + ctx->base.is_jmp = DISAS_TOO_MANY; + } +#if HEX_DEBUG + /* When debugging, only put one packet per TB */ + ctx->base.is_jmp = DISAS_TOO_MANY; +#endif + } +} + +static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + switch (ctx->base.is_jmp) { + case DISAS_TOO_MANY: + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); + if (ctx->base.singlestep_enabled) { + gen_exception_debug(); + } else { + tcg_gen_exit_tb(NULL, 0); + } + break; + case DISAS_NORETURN: + tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); + if (ctx->base.singlestep_enabled) { + gen_exception_debug(); + } else { + tcg_gen_exit_tb(NULL, 0); + } + break; + default: + g_assert_not_reached(); + } +} + +static void hexagon_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + + +static const TranslatorOps hexagon_tr_ops = { + .init_disas_context = hexagon_tr_init_disas_context, + .tb_start = hexagon_tr_tb_start, + .insn_start = hexagon_tr_insn_start, + .breakpoint_check = hexagon_tr_breakpoint_check, + .translate_insn = hexagon_tr_translate_packet, + .tb_stop = hexagon_tr_tb_stop, + .disas_log = hexagon_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) +{ + DisasContext ctx; + + translator_loop(&hexagon_tr_ops, &ctx.base, cs, tb, max_insns); +} + +#define NAME_LEN 64 +static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; +#if HEX_DEBUG +static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; +#endif +static char new_pred_value_names[NUM_PREGS][NAME_LEN]; +static char store_addr_names[STORES_MAX][NAME_LEN]; +static char store_width_names[STORES_MAX][NAME_LEN]; +static char store_val32_names[STORES_MAX][NAME_LEN]; +static char store_val64_names[STORES_MAX][NAME_LEN]; + +void hexagon_translate_init(void) +{ + int i; + + opcode_init(); + +#if HEX_DEBUG + if (!qemu_logfile) { + qemu_set_log(qemu_loglevel); + } +#endif + + for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + hex_gpr[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, gpr[i]), + hexagon_regnames[i]); + + snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]); + hex_new_value[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, new_value[i]), + new_value_names[i]); + +#if HEX_DEBUG + snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", + hexagon_regnames[i]); + hex_reg_written[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, reg_written[i]), + reg_written_names[i]); +#endif + } + for (i = 0; i < NUM_PREGS; i++) { + hex_pred[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, pred[i]), + hexagon_prednames[i]); + + snprintf(new_pred_value_names[i], NAME_LEN, "new_pred_%s", + hexagon_prednames[i]); + hex_new_pred_value[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, new_pred_value[i]), + new_pred_value_names[i]); + } + hex_pred_written = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, pred_written), "pred_written"); + hex_next_PC = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, next_PC), "next_PC"); + hex_this_PC = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, this_PC), "this_PC"); + hex_slot_cancelled = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); + hex_branch_taken = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, branch_taken), "branch_taken"); + hex_pkt_has_store_s1 = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1"); + hex_dczero_addr = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, dczero_addr), "dczero_addr"); + hex_llsc_addr = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, llsc_addr), "llsc_addr"); + hex_llsc_val = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, llsc_val), "llsc_val"); + hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); + for (i = 0; i < STORES_MAX; i++) { + snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); + hex_store_addr[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, mem_log_stores[i].va), + store_addr_names[i]); + + snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); + hex_store_width[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, mem_log_stores[i].width), + store_width_names[i]); + + snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); + hex_store_val32[i] = tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, mem_log_stores[i].data32), + store_val32_names[i]); + + snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); + hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHexagonState, mem_log_stores[i].data64), + store_val64_names[i]); + } +} From patchwork Fri Oct 30 00:08:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1669CC2D0A3 for ; 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29 Oct 2020 17:08:47 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 5335F4117; Thu, 29 Oct 2020 19:08:47 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v5 31/33] Hexagon (tests/tcg/hexagon) TCG tests Date: Thu, 29 Oct 2020 19:08:37 -0500 Message-Id: <1604016519-28065-32-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> References: <1604016519-28065-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, at.org@qualcomm.com, laurent@vivier.eu, tsimpson@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Modify tests/tcg/configure.sh Add reference files to tests/tcg/hexagon Add Hexagon-specific tests Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/atomics.c | 122 ++++++ tests/tcg/hexagon/clrtnew.c | 56 +++ tests/tcg/hexagon/dual_stores.c | 60 +++ tests/tcg/hexagon/mem_noshuf.c | 291 ++++++++++++++ tests/tcg/hexagon/misc.c | 293 ++++++++++++++ tests/tcg/hexagon/preg_alias.c | 106 +++++ tests/tcg/hexagon/pthread_cancel.c | 43 +++ tests/tcg/hexagon/sfminmax.c | 62 +++ tests/tcg/configure.sh | 4 +- tests/tcg/hexagon/Makefile.target | 48 +++ tests/tcg/hexagon/first.S | 56 +++ tests/tcg/hexagon/float_convs.ref | 748 ++++++++++++++++++++++++++++++++++++ tests/tcg/hexagon/float_madds.ref | 768 +++++++++++++++++++++++++++++++++++++ 13 files changed, 2656 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/hexagon/atomics.c create mode 100644 tests/tcg/hexagon/clrtnew.c create mode 100644 tests/tcg/hexagon/dual_stores.c create mode 100644 tests/tcg/hexagon/mem_noshuf.c create mode 100644 tests/tcg/hexagon/misc.c create mode 100644 tests/tcg/hexagon/preg_alias.c create mode 100644 tests/tcg/hexagon/pthread_cancel.c create mode 100644 tests/tcg/hexagon/sfminmax.c create mode 100644 tests/tcg/hexagon/Makefile.target create mode 100644 tests/tcg/hexagon/first.S create mode 100644 tests/tcg/hexagon/float_convs.ref create mode 100644 tests/tcg/hexagon/float_madds.ref diff --git a/tests/tcg/hexagon/atomics.c b/tests/tcg/hexagon/atomics.c new file mode 100644 index 0000000..88d7450 --- /dev/null +++ b/tests/tcg/hexagon/atomics.c @@ -0,0 +1,122 @@ +#include +#include +#include +#include +#include +#include + +/* Using volatile because we are testing atomics */ +static inline int atomic_inc32(volatile int *x) +{ + int old, dummy; + __asm__ __volatile__( + "1: %0 = memw_locked(%2)\n\t" + " %1 = add(%0, #1)\n\t" + " memw_locked(%2, p0) = %1\n\t" + " if (!p0) jump 1b\n\t" + : "=&r"(old), "=&r"(dummy) + : "r"(x) + : "p0", "memory"); + return old; +} + +/* Using volatile because we are testing atomics */ +static inline long long atomic_inc64(volatile long long *x) +{ + long long old, dummy; + __asm__ __volatile__( + "1: %0 = memd_locked(%2)\n\t" + " %1 = #1\n\t" + " %1 = add(%0, %1)\n\t" + " memd_locked(%2, p0) = %1\n\t" + " if (!p0) jump 1b\n\t" + : "=&r"(old), "=&r"(dummy) + : "r"(x) + : "p0", "memory"); + return old; +} + +/* Using volatile because we are testing atomics */ +static inline int atomic_dec32(volatile int *x) +{ + int old, dummy; + __asm__ __volatile__( + "1: %0 = memw_locked(%2)\n\t" + " %1 = add(%0, #-1)\n\t" + " memw_locked(%2, p0) = %1\n\t" + " if (!p0) jump 1b\n\t" + : "=&r"(old), "=&r"(dummy) + : "r"(x) + : "p0", "memory"); + return old; +} + +/* Using volatile because we are testing atomics */ +static inline long long atomic_dec64(volatile long long *x) +{ + long long old, dummy; + __asm__ __volatile__( + "1: %0 = memd_locked(%2)\n\t" + " %1 = #-1\n\t" + " %1 = add(%0, %1)\n\t" + " memd_locked(%2, p0) = %1\n\t" + " if (!p0) jump 1b\n\t" + : "=&r"(old), "=&r"(dummy) + : "r"(x) + : "p0", "memory"); + return old; +} + +#define LOOP_CNT 1000 +/* Using volatile because we are testing atomics */ +volatile int tick32 = 1; +/* Using volatile because we are testing atomics */ +volatile long long tick64 = 1; +int err; + +void *thread1_func(void *arg) +{ + int i; + + for (i = 0; i < LOOP_CNT; i++) { + atomic_inc32(&tick32); + atomic_dec64(&tick64); + } + return NULL; +} + +void *thread2_func(void *arg) +{ + int i; + for (i = 0; i < LOOP_CNT; i++) { + atomic_dec32(&tick32); + atomic_inc64(&tick64); + } + return NULL; +} + +void test_pthread(void) +{ + pthread_t tid1, tid2; + + pthread_create(&tid1, NULL, thread1_func, "hello1"); + pthread_create(&tid2, NULL, thread2_func, "hello2"); + pthread_join(tid1, NULL); + pthread_join(tid2, NULL); + + if (tick32 != 1) { + printf("ERROR: tick32 %d != 1\n", tick32); + err++; + } + if (tick64 != 1) { + printf("ERROR: tick64 %lld != 1\n", tick64); + err++; + } +} + +int main(int argc, char **argv) +{ + test_pthread(); + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/clrtnew.c b/tests/tcg/hexagon/clrtnew.c new file mode 100644 index 0000000..665c2b3 --- /dev/null +++ b/tests/tcg/hexagon/clrtnew.c @@ -0,0 +1,56 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +static inline int test_clrtnew(int arg1, int old_val) +{ + int ret; + asm volatile("r5 = %2\n\t" + "{\n\t" + "p0 = cmp.eq(%1, #1)\n\t" + "if (p0.new) r5=#0\n\t" + "}\n\t" + "%0 = r5\n\t" + : "=r"(ret) + : "r"(arg1), "r"(old_val) + : "p0", "r5"); + return ret; +} + +int err; + +static void check(int val, int expect) +{ + if (val != expect) { + printf("ERROR: 0x%d != 0x%d\n", val, expect); + err++; + } +} + +int main() +{ + int res; + + res = test_clrtnew(1, 7); + check(res, 0); + res = test_clrtnew(2, 7); + check(res, 7); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/dual_stores.c b/tests/tcg/hexagon/dual_stores.c new file mode 100644 index 0000000..ba81bc2 --- /dev/null +++ b/tests/tcg/hexagon/dual_stores.c @@ -0,0 +1,60 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +/* + * Make sure that two stores in the same packet honor proper + * semantics: slot 1 executes first, then slot 0. + * This is important when the addresses overlap. + */ +static inline void dual_stores(int *p, char *q, int x, char y) +{ + asm volatile("{\n\t" + " memw(%0) = %2\n\t" + " memb(%1) = %3\n\t" + "}\n" + :: "r"(p), "r"(q), "r"(x), "r"(y) + : "memory"); +} + +typedef union { + int word; + char byte; +} Dual; + +int err; + +static void check(Dual d, int expect) +{ + if (d.word != expect) { + printf("ERROR: 0x%08x != 0x%08x\n", d.word, expect); + err++; + } +} + +int main() +{ + Dual d; + + d.word = ~0; + dual_stores(&d.word, &d.byte, 0x12345678, 0xff); + check(d, 0x123456ff); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/mem_noshuf.c b/tests/tcg/hexagon/mem_noshuf.c new file mode 100644 index 0000000..f7bf2e3 --- /dev/null +++ b/tests/tcg/hexagon/mem_noshuf.c @@ -0,0 +1,291 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +/* + * Make sure that the :mem_noshuf packet attribute is honored. + * This is important when the addresses overlap. + * The store instruction in slot 1 effectively executes first, + * followed by the load instruction in slot 0. + */ + +#define MEM_NOSHUF32(NAME, ST_TYPE, LD_TYPE, ST_OP, LD_OP) \ +static inline unsigned int NAME(ST_TYPE * p, LD_TYPE * q, ST_TYPE x) \ +{ \ + unsigned int ret; \ + asm volatile("{\n\t" \ + " " #ST_OP "(%1) = %3\n\t" \ + " %0 = " #LD_OP "(%2)\n\t" \ + "}:mem_noshuf\n" \ + : "=r"(ret) \ + : "r"(p), "r"(q), "r"(x) \ + : "memory"); \ + return ret; \ +} + +#define MEM_NOSHUF64(NAME, ST_TYPE, LD_TYPE, ST_OP, LD_OP) \ +static inline unsigned long long NAME(ST_TYPE * p, LD_TYPE * q, ST_TYPE x) \ +{ \ + unsigned long long ret; \ + asm volatile("{\n\t" \ + " " #ST_OP "(%1) = %3\n\t" \ + " %0 = " #LD_OP "(%2)\n\t" \ + "}:mem_noshuf\n" \ + : "=r"(ret) \ + : "r"(p), "r"(q), "r"(x) \ + : "memory"); \ + return ret; \ +} + +/* Store byte combinations */ +MEM_NOSHUF32(mem_noshuf_sb_lb, signed char, signed char, memb, memb) +MEM_NOSHUF32(mem_noshuf_sb_lub, signed char, unsigned char, memb, memub) +MEM_NOSHUF32(mem_noshuf_sb_lh, signed char, signed short, memb, memh) +MEM_NOSHUF32(mem_noshuf_sb_luh, signed char, unsigned short, memb, memuh) +MEM_NOSHUF32(mem_noshuf_sb_lw, signed char, signed int, memb, memw) +MEM_NOSHUF64(mem_noshuf_sb_ld, signed char, signed long long, memb, memd) + +/* Store half combinations */ +MEM_NOSHUF32(mem_noshuf_sh_lb, signed short, signed char, memh, memb) +MEM_NOSHUF32(mem_noshuf_sh_lub, signed short, unsigned char, memh, memub) +MEM_NOSHUF32(mem_noshuf_sh_lh, signed short, signed short, memh, memh) +MEM_NOSHUF32(mem_noshuf_sh_luh, signed short, unsigned short, memh, memuh) +MEM_NOSHUF32(mem_noshuf_sh_lw, signed short, signed int, memh, memw) +MEM_NOSHUF64(mem_noshuf_sh_ld, signed short, signed long long, memh, memd) + +/* Store word combinations */ +MEM_NOSHUF32(mem_noshuf_sw_lb, signed int, signed char, memw, memb) +MEM_NOSHUF32(mem_noshuf_sw_lub, signed int, unsigned char, memw, memub) +MEM_NOSHUF32(mem_noshuf_sw_lh, signed int, signed short, memw, memh) +MEM_NOSHUF32(mem_noshuf_sw_luh, signed int, unsigned short, memw, memuh) +MEM_NOSHUF32(mem_noshuf_sw_lw, signed int, signed int, memw, memw) +MEM_NOSHUF64(mem_noshuf_sw_ld, signed int, signed long long, memw, memd) + +/* Store double combinations */ +MEM_NOSHUF32(mem_noshuf_sd_lb, long long, signed char, memd, memb) +MEM_NOSHUF32(mem_noshuf_sd_lub, long long, unsigned char, memd, memub) +MEM_NOSHUF32(mem_noshuf_sd_lh, long long, signed short, memd, memh) +MEM_NOSHUF32(mem_noshuf_sd_luh, long long, unsigned short, memd, memuh) +MEM_NOSHUF32(mem_noshuf_sd_lw, long long, signed int, memd, memw) +MEM_NOSHUF64(mem_noshuf_sd_ld, long long, signed long long, memd, memd) + +static inline unsigned int cancel_sw_lb(int pred, int *p, signed char *q, int x) +{ + unsigned int ret; + asm volatile("p0 = cmp.eq(%4, #0)\n\t" + "{\n\t" + " if (!p0) memw(%1) = %3\n\t" + " %0 = memb(%2)\n\t" + "}:mem_noshuf\n" + : "=r"(ret) + : "r"(p), "r"(q), "r"(x), "r"(pred) + : "p0", "memory"); + return ret; +} + +static inline +unsigned long long cancel_sw_ld(int pred, int *p, long long *q, int x) +{ + long long ret; + asm volatile("p0 = cmp.eq(%4, #0)\n\t" + "{\n\t" + " if (!p0) memw(%1) = %3\n\t" + " %0 = memd(%2)\n\t" + "}:mem_noshuf\n" + : "=r"(ret) + : "r"(p), "r"(q), "r"(x), "r"(pred) + : "p0", "memory"); + return ret; +} + +typedef union { + signed long long d; + unsigned long long ud; + signed int w[2]; + unsigned int uw[2]; + signed short h[4]; + unsigned short uh[4]; + signed char b[8]; + unsigned char ub[8]; +} Memory; + +int err; + +static void check32(int n, int expect) +{ + if (n != expect) { + printf("ERROR: 0x%08x != 0x%08x\n", n, expect); + err++; + } +} + +static void check64(long long n, long long expect) +{ + if (n != expect) { + printf("ERROR: 0x%08llx != 0x%08llx\n", n, expect); + err++; + } +} + +int main() +{ + Memory n; + unsigned int res32; + unsigned long long res64; + + /* + * Store byte combinations + */ + n.w[0] = ~0; + res32 = mem_noshuf_sb_lb(&n.b[0], &n.b[0], 0x87); + check32(res32, 0xffffff87); + + n.w[0] = ~0; + res32 = mem_noshuf_sb_lub(&n.b[0], &n.ub[0], 0x87); + check32(res32, 0x00000087); + + n.w[0] = ~0; + res32 = mem_noshuf_sb_lh(&n.b[0], &n.h[0], 0x87); + check32(res32, 0xffffff87); + + n.w[0] = ~0; + res32 = mem_noshuf_sb_luh(&n.b[0], &n.uh[0], 0x87); + check32(res32, 0x0000ff87); + + n.w[0] = ~0; + res32 = mem_noshuf_sb_lw(&n.b[0], &n.w[0], 0x87); + check32(res32, 0xffffff87); + + n.d = ~0; + res64 = mem_noshuf_sb_ld(&n.b[0], &n.d, 0x87); + check64(res64, 0xffffffffffffff87); + + /* + * Store half combinations + */ + n.w[0] = ~0; + res32 = mem_noshuf_sh_lb(&n.h[0], &n.b[0], 0x8787); + check32(res32, 0xffffff87); + + n.w[0] = ~0; + res32 = mem_noshuf_sh_lub(&n.h[0], &n.ub[1], 0x8f87); + check32(res32, 0x0000008f); + + n.w[0] = ~0; + res32 = mem_noshuf_sh_lh(&n.h[0], &n.h[0], 0x8a87); + check32(res32, 0xffff8a87); + + n.w[0] = ~0; + res32 = mem_noshuf_sh_luh(&n.h[0], &n.uh[0], 0x8a87); + check32(res32, 0x8a87); + + n.w[0] = ~0; + res32 = mem_noshuf_sh_lw(&n.h[1], &n.w[0], 0x8a87); + check32(res32, 0x8a87ffff); + + n.w[0] = ~0; + res64 = mem_noshuf_sh_ld(&n.h[1], &n.d, 0x8a87); + check64(res64, 0xffffffff8a87ffff); + + /* + * Store word combinations + */ + n.w[0] = ~0; + res32 = mem_noshuf_sw_lb(&n.w[0], &n.b[0], 0x12345687); + check32(res32, 0xffffff87); + + n.w[0] = ~0; + res32 = mem_noshuf_sw_lub(&n.w[0], &n.ub[0], 0x12345687); + check32(res32, 0x00000087); + + n.w[0] = ~0; + res32 = mem_noshuf_sw_lh(&n.w[0], &n.h[0], 0x1234f678); + check32(res32, 0xfffff678); + + n.w[0] = ~0; + res32 = mem_noshuf_sw_luh(&n.w[0], &n.uh[0], 0x12345678); + check32(res32, 0x00005678); + + n.w[0] = ~0; + res32 = mem_noshuf_sw_lw(&n.w[0], &n.w[0], 0x12345678); + check32(res32, 0x12345678); + + n.d = ~0; + res64 = mem_noshuf_sw_ld(&n.w[0], &n.d, 0x12345678); + check64(res64, 0xffffffff12345678); + + /* + * Store double combinations + */ + n.d = ~0; + res32 = mem_noshuf_sd_lb(&n.d, &n.b[1], 0x123456789abcdef0); + check32(res32, 0xffffffde); + + n.d = ~0; + res32 = mem_noshuf_sd_lub(&n.d, &n.ub[1], 0x123456789abcdef0); + check32(res32, 0x000000de); + + n.d = ~0; + res32 = mem_noshuf_sd_lh(&n.d, &n.h[1], 0x123456789abcdef0); + check32(res32, 0xffff9abc); + + n.d = ~0; + res32 = mem_noshuf_sd_luh(&n.d, &n.uh[1], 0x123456789abcdef0); + check32(res32, 0x00009abc); + + n.d = ~0; + res32 = mem_noshuf_sd_lw(&n.d, &n.w[1], 0x123456789abcdef0); + check32(res32, 0x12345678); + + n.d = ~0; + res64 = mem_noshuf_sd_ld(&n.d, &n.d, 0x123456789abcdef0); + check64(res64, 0x123456789abcdef0); + + /* + * Predicated word stores + */ + n.w[0] = ~0; + res32 = cancel_sw_lb(0, &n.w[0], &n.b[0], 0x12345678); + check32(res32, 0xffffffff); + + n.w[0] = ~0; + res32 = cancel_sw_lb(1, &n.w[0], &n.b[0], 0x12345687); + check32(res32, 0xffffff87); + + /* + * Predicated double stores + */ + n.d = ~0; + res64 = cancel_sw_ld(0, &n.w[0], &n.d, 0x12345678); + check64(res64, 0xffffffffffffffff); + + n.d = ~0; + res64 = cancel_sw_ld(1, &n.w[0], &n.d, 0x12345678); + check64(res64, 0xffffffff12345678); + + n.d = ~0; + res64 = cancel_sw_ld(0, &n.w[1], &n.d, 0x12345678); + check64(res64, 0xffffffffffffffff); + + n.d = ~0; + res64 = cancel_sw_ld(1, &n.w[1], &n.d, 0x12345678); + check64(res64, 0x12345678ffffffff); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c new file mode 100644 index 0000000..796ac74 --- /dev/null +++ b/tests/tcg/hexagon/misc.c @@ -0,0 +1,293 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; + + +static inline void S4_storerhnew_rr(void *p, int index, uint16_t v) +{ + asm volatile("{\n\t" + " r0 = %0\n\n" + " memh(%1+%2<<#2) = r0.new\n\t" + "}\n" + :: "r"(v), "r"(p), "r"(index) + : "r0", "memory"); +} + +static uint32_t data; +static inline void *S4_storerbnew_ap(uint8_t v) +{ + void *ret; + asm volatile("{\n\t" + " r0 = %1\n\n" + " memb(%0 = ##data) = r0.new\n\t" + "}\n" + : "=r"(ret) + : "r"(v) + : "r0", "memory"); + return ret; +} + +static inline void *S4_storerhnew_ap(uint16_t v) +{ + void *ret; + asm volatile("{\n\t" + " r0 = %1\n\n" + " memh(%0 = ##data) = r0.new\n\t" + "}\n" + : "=r"(ret) + : "r"(v) + : "r0", "memory"); + return ret; +} + +static inline void *S4_storerinew_ap(uint32_t v) +{ + void *ret; + asm volatile("{\n\t" + " r0 = %1\n\n" + " memw(%0 = ##data) = r0.new\n\t" + "}\n" + : "=r"(ret) + : "r"(v) + : "r0", "memory"); + return ret; +} + +static inline void S4_storeirbt_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (p0) memb(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirbf_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (!p0) memb(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirbtnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (p0.new) memb(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirbfnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (!p0.new) memb(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirht_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (p0) memh(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirhf_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (!p0) memh(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirhtnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (p0.new) memh(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirhfnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (!p0.new) memh(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirit_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (p0) memw(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirif_io(void *p, int pred) +{ + asm volatile("p0 = cmp.eq(%0, #1)\n\t" + "if (!p0) memw(%1+#4)=#27\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeiritnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (p0.new) memw(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +static inline void S4_storeirifnew_io(void *p, int pred) +{ + asm volatile("{\n\t" + " p0 = cmp.eq(%0, #1)\n\t" + " if (!p0.new) memw(%1+#4)=#27\n\t" + "}\n\t" + :: "r"(pred), "r"(p) + : "p0", "memory"); +} + +int err; + +static void check(int val, int expect) +{ + if (val != expect) { + printf("ERROR: 0x%04x != 0x%04x\n", val, expect); + err++; + } +} + +uint32_t init[10] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }; +uint32_t array[10]; + +int main() +{ + + memcpy(array, init, sizeof(array)); + S4_storerhnew_rr(array, 4, 0xffff); + check(array[4], 0xffff); + + data = ~0; + check((uint32_t)S4_storerbnew_ap(0x12), (uint32_t)&data); + check(data, 0xffffff12); + + data = ~0; + check((uint32_t)S4_storerhnew_ap(0x1234), (uint32_t)&data); + check(data, 0xffff1234); + + data = ~0; + check((uint32_t)S4_storerinew_ap(0x12345678), (uint32_t)&data); + check(data, 0x12345678); + + /* Byte */ + memcpy(array, init, sizeof(array)); + S4_storeirbt_io(&array[1], 1); + check(array[2], 27); + S4_storeirbt_io(&array[2], 0); + check(array[3], 3); + + memcpy(array, init, sizeof(array)); + S4_storeirbf_io(&array[3], 0); + check(array[4], 27); + S4_storeirbf_io(&array[4], 1); + check(array[5], 5); + + memcpy(array, init, sizeof(array)); + S4_storeirbtnew_io(&array[5], 1); + check(array[6], 27); + S4_storeirbtnew_io(&array[6], 0); + check(array[7], 7); + + memcpy(array, init, sizeof(array)); + S4_storeirbfnew_io(&array[7], 0); + check(array[8], 27); + S4_storeirbfnew_io(&array[8], 1); + check(array[9], 9); + + /* Half word */ + memcpy(array, init, sizeof(array)); + S4_storeirht_io(&array[1], 1); + check(array[2], 27); + S4_storeirht_io(&array[2], 0); + check(array[3], 3); + + memcpy(array, init, sizeof(array)); + S4_storeirhf_io(&array[3], 0); + check(array[4], 27); + S4_storeirhf_io(&array[4], 1); + check(array[5], 5); + + memcpy(array, init, sizeof(array)); + S4_storeirhtnew_io(&array[5], 1); + check(array[6], 27); + S4_storeirhtnew_io(&array[6], 0); + check(array[7], 7); + + memcpy(array, init, sizeof(array)); + S4_storeirhfnew_io(&array[7], 0); + check(array[8], 27); + S4_storeirhfnew_io(&array[8], 1); + check(array[9], 9); + + /* Word */ + memcpy(array, init, sizeof(array)); + S4_storeirit_io(&array[1], 1); + check(array[2], 27); + S4_storeirit_io(&array[2], 0); + check(array[3], 3); + + memcpy(array, init, sizeof(array)); + S4_storeirif_io(&array[3], 0); + check(array[4], 27); + S4_storeirif_io(&array[4], 1); + check(array[5], 5); + + memcpy(array, init, sizeof(array)); + S4_storeiritnew_io(&array[5], 1); + check(array[6], 27); + S4_storeiritnew_io(&array[6], 0); + check(array[7], 7); + + memcpy(array, init, sizeof(array)); + S4_storeirifnew_io(&array[7], 0); + check(array[8], 27); + S4_storeirifnew_io(&array[8], 1); + check(array[9], 9); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/preg_alias.c b/tests/tcg/hexagon/preg_alias.c new file mode 100644 index 0000000..4d51674 --- /dev/null +++ b/tests/tcg/hexagon/preg_alias.c @@ -0,0 +1,106 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +static inline int preg_alias(int v0, int v1, int v2, int v3) +{ + int ret; + asm volatile("p0 = %1\n\t" + "p1 = %2\n\t" + "p2 = %3\n\t" + "p3 = %4\n\t" + "%0 = C4\n" + : "=r"(ret) + : "r"(v0), "r"(v1), "r"(v2), "r"(v3) + : "p0", "p1", "p2", "p3"); + return ret; +} + +typedef union { + int creg; + struct { + unsigned char p0; + unsigned char p1; + unsigned char p2; + unsigned char p3; + } pregs; +} PRegs; + +static inline void creg_alias(int cval, PRegs *pregs) +{ + unsigned char val; + asm volatile("c4 = %0" : : "r"(cval)); + + asm volatile("%0 = p0" : "=r"(val)); + pregs->pregs.p0 = val; + asm volatile("%0 = p1" : "=r"(val)); + pregs->pregs.p1 = val; + asm volatile("%0 = p2" : "=r"(val)); + pregs->pregs.p2 = val; + asm volatile("%0 = p3" : "=r"(val)); + pregs->pregs.p3 = val; +} + +int err; + +static void check(int val, int expect) +{ + if (val != expect) { + printf("ERROR: 0x%08x != 0x%08x\n", val, expect); + err++; + } +} + +int main() +{ + int c4; + PRegs pregs; + + c4 = preg_alias(0xff, 0x00, 0xff, 0x00); + check(c4, 0x00ff00ff); + c4 = preg_alias(0xff, 0x00, 0x00, 0x00); + check(c4, 0x000000ff); + c4 = preg_alias(0x00, 0xff, 0x00, 0x00); + check(c4, 0x0000ff00); + c4 = preg_alias(0x00, 0x00, 0xff, 0x00); + check(c4, 0x00ff0000); + c4 = preg_alias(0x00, 0x00, 0x00, 0xff); + check(c4, 0xff000000); + c4 = preg_alias(0xff, 0xff, 0xff, 0xff); + check(c4, 0xffffffff); + + creg_alias(0x00ff00ff, &pregs); + check(pregs.creg, 0x00ff00ff); + creg_alias(0x00ffff00, &pregs); + check(pregs.creg, 0x00ffff00); + creg_alias(0x00000000, &pregs); + check(pregs.creg, 0x00000000); + creg_alias(0xff000000, &pregs); + check(pregs.creg, 0xff000000); + creg_alias(0x00ff0000, &pregs); + check(pregs.creg, 0x00ff0000); + creg_alias(0x0000ff00, &pregs); + check(pregs.creg, 0x0000ff00); + creg_alias(0x000000ff, &pregs); + check(pregs.creg, 0x000000ff); + creg_alias(0xffffffff, &pregs); + check(pregs.creg, 0xffffffff); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/pthread_cancel.c b/tests/tcg/hexagon/pthread_cancel.c new file mode 100644 index 0000000..db30cbc --- /dev/null +++ b/tests/tcg/hexagon/pthread_cancel.c @@ -0,0 +1,43 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include +#include + +static void *func(void *arg) +{ + sleep(3); + return 0; +} + +int main() +{ + int err = 0; + pthread_t thread; + void *res; + + pthread_create(&thread, 0, func, NULL); + pthread_cancel(thread); + pthread_join(thread, &res); + if (res != PTHREAD_CANCELED) { + err++; + } + + puts(err == 0 ? "PASS" : "FAIL"); + return err == 0 ? 0 : -1; +} diff --git a/tests/tcg/hexagon/sfminmax.c b/tests/tcg/hexagon/sfminmax.c new file mode 100644 index 0000000..cfe443f --- /dev/null +++ b/tests/tcg/hexagon/sfminmax.c @@ -0,0 +1,62 @@ +/* + * Copyright(c) 2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +/* + * This test checks that the FP invalid bit in USR is not set + * when one of the operands is NaN. + */ +const int FPINVF_BIT = 1; + +int err; + +int main() +{ + int usr; + + asm volatile("r2 = usr\n\t" + "r2 = clrbit(r2, #%1)\n\t" + "usr = r2\n\t" + "r2 = ##0x7fc00000\n\t" /* NaN */ + "r3 = ##0x7f7fffff\n\t" + "r2 = sfmin(r2, r3)\n\t" + "%0 = usr\n\t" + : "=r"(usr) : "i"(FPINVF_BIT) : "r2", "r3", "usr"); + + if (usr & (1 << FPINVF_BIT)) { + puts("sfmin test failed"); + err++; + } + + asm volatile("r2 = usr\n\t" + "r2 = clrbit(r2, #%1)\n\t" + "usr = r2\n\t" + "r2 = ##0x7fc00000\n\t" /* NaN */ + "r3 = ##0x7f7fffff\n\t" + "r2 = sfmax(r2, r3)\n\t" + "%0 = usr\n\t" + : "=r"(usr) : "i"(FPINVF_BIT) : "r2", "r3", "usr"); + + if (usr & (1 << FPINVF_BIT)) { + puts("sfmax test failed"); + err++; + } + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index e1b70e2..eaa1835 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -69,6 +69,8 @@ fi : ${cross_cc_cflags_sparc64="-m64 -mcpu=ultrasparc"} : ${cross_cc_x86_64="x86_64-pc-linux-gnu-gcc"} : ${cross_cc_cflags_x86_64="-m64"} +: ${cross_cc_hexagon="hexagon-unknown-linux-musl-clang"} +: ${cross_cc_cflags_hexagon="-mv67 -O2 --static -Wno-incompatible-pointer-types"} for target in $target_list; do arch=${target%%-*} @@ -94,7 +96,7 @@ for target in $target_list; do xtensa|xtensaeb) arches=xtensa ;; - alpha|cris|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64) + alpha|cris|hexagon|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64) arches=$target ;; *) diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target new file mode 100644 index 0000000..706345e --- /dev/null +++ b/tests/tcg/hexagon/Makefile.target @@ -0,0 +1,48 @@ +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +# Hexagon doesn't support gdb, so skip the EXTRA_RUNS +EXTRA_RUNS = + +# Hexagon has 64K pages, so increase the timeout to keep +# test-mmap from timing out +ifeq ($(CONFIG_DEBUG_TCG),y) +TIMEOUT=600 +else +TIMEOUT=400 +endif + + +CFLAGS = -mv67 -O2 + +HEX_SRC=$(SRC_PATH)/tests/tcg/hexagon +VPATH += $(HEX_SRC) + +first: $(HEX_SRC)/first.S + $(CC) -static -mv67 -nostdlib $^ -o $@ + +HEX_TESTS = first +HEX_TESTS += misc +HEX_TESTS += preg_alias +HEX_TESTS += dual_stores +HEX_TESTS += clrtnew +HEX_TESTS += mem_noshuf +HEX_TESTS += pthread_cancel +HEX_TESTS += atomics +HEX_TESTS += sfminmax + +TESTS += $(HEX_TESTS) diff --git a/tests/tcg/hexagon/first.S b/tests/tcg/hexagon/first.S new file mode 100644 index 0000000..a02e7a2 --- /dev/null +++ b/tests/tcg/hexagon/first.S @@ -0,0 +1,56 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#define SYS_write 64 +#define SYS_exit_group 94 +#define SYS_exit 93 + +#define FD_STDOUT 1 + + .type str,@object + .section .rodata +str: + .string "Hello!\n" + .size str, 8 + +.text +.global _start +_start: + r6 = #SYS_write + r0 = #FD_STDOUT + r1 = ##str + r2 = #7 + trap0(#1) + + r0 = #0 + r6 = #SYS_exit_group + trap0(#1) + +.section ".note.ABI-tag", "a" +.align 4 +.long 1f - 0f /* name length */ +.long 3f - 2f /* data length */ +.long 1 /* note type */ + +/* + * vendor name seems like this should be MUSL but lldb doesn't agree. + */ +0: .asciz "GNU" +1: .align 4 +2: .long 0 /* linux */ + .long 3,0,0 +3: .align 4 diff --git a/tests/tcg/hexagon/float_convs.ref b/tests/tcg/hexagon/float_convs.ref new file mode 100644 index 0000000..9ec9ffc --- /dev/null +++ b/tests/tcg/hexagon/float_convs.ref @@ -0,0 +1,748 @@ +### Rounding to nearest +from single: f32(-nan:0xffa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0xffc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-inf:0xff800000) + to double: f64(-inf:0x00fff0000000000000) (OK) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + to double: f64(-0x1.fffffe00000000000000p+127:0x00c7efffffe0000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + to double: f64(-0x1.1874b200000000000000p+103:0x00c661874b20000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + to double: f64(-0x1.c0bab600000000000000p+99:0x00c62c0bab60000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.31f75000000000000000p-40:0xab98fba8) + to double: f64(-0x1.31f75000000000000000p-40:0x00bd731f7500000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.50544400000000000000p-66:0x9ea82a22) + to double: f64(-0x1.50544400000000000000p-66:0x00bbd5054440000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.00000000000000000000p-126:0x80800000) + to double: f64(-0x1.00000000000000000000p-126:0x00b810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(0x0.00000000000000000000p+0:0000000000) + to double: f64(0x0.00000000000000000000p+0:00000000000000000000) (OK) + to int32: 0 (OK) + to int64: 0 (OK) + to uint32: 0 (OK) + to uint64: 0 (OK) +from single: f32(0x1.00000000000000000000p-126:0x00800000) + to double: f64(0x1.00000000000000000000p-126:0x003810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p-25:0x33000000) + to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) + to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ff801a00000000000000p-15:0x387fc00d) + to double: f64(0x1.ff801a00000000000000p-15:0x003f0ff801a0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000c00000000000000p-14:0x38800006) + to double: f64(0x1.00000c00000000000000p-14:0x003f100000c0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p+0:0x3f800000) + to double: f64(0x1.00000000000000000000p+0:0x003ff0000000000000) (OK) + to int32: 1 (OK) + to int64: 1 (OK) + to uint32: 1 (OK) + to uint64: 1 (OK) +from single: f32(0x1.00400000000000000000p+0:0x3f802000) + to double: f64(0x1.00400000000000000000p+0:0x003ff0040000000000) (INEXACT ) + to int32: 1 (INEXACT ) + to int64: 1 (INEXACT ) + to uint32: 1 (INEXACT ) + to uint64: 1 (INEXACT ) +from single: f32(0x1.00000000000000000000p+1:0x40000000) + to double: f64(0x1.00000000000000000000p+1:0x004000000000000000) (OK) + to int32: 2 (OK) + to int64: 2 (OK) + to uint32: 2 (OK) + to uint64: 2 (OK) +from single: f32(0x1.5bf0a800000000000000p+1:0x402df854) + to double: f64(0x1.5bf0a800000000000000p+1:0x004005bf0a80000000) (INEXACT ) + to int32: 2 (INEXACT ) + to int64: 2 (INEXACT ) + to uint32: 2 (INEXACT ) + to uint64: 2 (INEXACT ) +from single: f32(0x1.921fb600000000000000p+1:0x40490fdb) + to double: f64(0x1.921fb600000000000000p+1:0x00400921fb60000000) (INEXACT ) + to int32: 3 (INEXACT ) + to int64: 3 (INEXACT ) + to uint32: 3 (INEXACT ) + to uint64: 3 (INEXACT ) +from single: f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + to double: f64(0x1.ffbe0000000000000000p+15:0x0040effbe000000000) (INEXACT ) + to int32: 65503 (OK) + to int64: 65503 (OK) + to uint32: 65503 (OK) + to uint64: 65503 (OK) +from single: f32(0x1.ffc00000000000000000p+15:0x477fe000) + to double: f64(0x1.ffc00000000000000000p+15:0x0040effc0000000000) (INEXACT ) + to int32: 65504 (OK) + to int64: 65504 (OK) + to uint32: 65504 (OK) + to uint64: 65504 (OK) +from single: f32(0x1.ffc20000000000000000p+15:0x477fe100) + to double: f64(0x1.ffc20000000000000000p+15:0x0040effc2000000000) (INEXACT ) + to int32: 65505 (OK) + to int64: 65505 (OK) + to uint32: 65505 (OK) + to uint64: 65505 (OK) +from single: f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + to double: f64(0x1.ffbf0000000000000000p+16:0x0040fffbf000000000) (INEXACT ) + to int32: 131007 (OK) + to int64: 131007 (OK) + to uint32: 131007 (OK) + to uint64: 131007 (OK) +from single: f32(0x1.ffc00000000000000000p+16:0x47ffe000) + to double: f64(0x1.ffc00000000000000000p+16:0x0040fffc0000000000) (INEXACT ) + to int32: 131008 (OK) + to int64: 131008 (OK) + to uint32: 131008 (OK) + to uint64: 131008 (OK) +from single: f32(0x1.ffc10000000000000000p+16:0x47ffe080) + to double: f64(0x1.ffc10000000000000000p+16:0x0040fffc1000000000) (INEXACT ) + to int32: 131009 (OK) + to int64: 131009 (OK) + to uint32: 131009 (OK) + to uint64: 131009 (OK) +from single: f32(0x1.c0bab600000000000000p+99:0x71605d5b) + to double: f64(0x1.c0bab600000000000000p+99:0x00462c0bab60000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + to double: f64(0x1.fffffe00000000000000p+127:0x0047efffffe0000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(inf:0x7f800000) + to double: f64(inf:0x007ff0000000000000) (OK) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +### Rounding upwards +from single: f32(-nan:0xffa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0xffc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-inf:0xff800000) + to double: f64(-inf:0x00fff0000000000000) (OK) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + to double: f64(-0x1.fffffe00000000000000p+127:0x00c7efffffe0000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + to double: f64(-0x1.1874b200000000000000p+103:0x00c661874b20000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + to double: f64(-0x1.c0bab600000000000000p+99:0x00c62c0bab60000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.31f75000000000000000p-40:0xab98fba8) + to double: f64(-0x1.31f75000000000000000p-40:0x00bd731f7500000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.50544400000000000000p-66:0x9ea82a22) + to double: f64(-0x1.50544400000000000000p-66:0x00bbd5054440000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.00000000000000000000p-126:0x80800000) + to double: f64(-0x1.00000000000000000000p-126:0x00b810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(0x0.00000000000000000000p+0:0000000000) + to double: f64(0x0.00000000000000000000p+0:00000000000000000000) (OK) + to int32: 0 (OK) + to int64: 0 (OK) + to uint32: 0 (OK) + to uint64: 0 (OK) +from single: f32(0x1.00000000000000000000p-126:0x00800000) + to double: f64(0x1.00000000000000000000p-126:0x003810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p-25:0x33000000) + to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) + to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ff801a00000000000000p-15:0x387fc00d) + to double: f64(0x1.ff801a00000000000000p-15:0x003f0ff801a0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000c00000000000000p-14:0x38800006) + to double: f64(0x1.00000c00000000000000p-14:0x003f100000c0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p+0:0x3f800000) + to double: f64(0x1.00000000000000000000p+0:0x003ff0000000000000) (OK) + to int32: 1 (OK) + to int64: 1 (OK) + to uint32: 1 (OK) + to uint64: 1 (OK) +from single: f32(0x1.00400000000000000000p+0:0x3f802000) + to double: f64(0x1.00400000000000000000p+0:0x003ff0040000000000) (INEXACT ) + to int32: 1 (INEXACT ) + to int64: 1 (INEXACT ) + to uint32: 1 (INEXACT ) + to uint64: 1 (INEXACT ) +from single: f32(0x1.00000000000000000000p+1:0x40000000) + to double: f64(0x1.00000000000000000000p+1:0x004000000000000000) (OK) + to int32: 2 (OK) + to int64: 2 (OK) + to uint32: 2 (OK) + to uint64: 2 (OK) +from single: f32(0x1.5bf0a800000000000000p+1:0x402df854) + to double: f64(0x1.5bf0a800000000000000p+1:0x004005bf0a80000000) (INEXACT ) + to int32: 2 (INEXACT ) + to int64: 2 (INEXACT ) + to uint32: 2 (INEXACT ) + to uint64: 2 (INEXACT ) +from single: f32(0x1.921fb600000000000000p+1:0x40490fdb) + to double: f64(0x1.921fb600000000000000p+1:0x00400921fb60000000) (INEXACT ) + to int32: 3 (INEXACT ) + to int64: 3 (INEXACT ) + to uint32: 3 (INEXACT ) + to uint64: 3 (INEXACT ) +from single: f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + to double: f64(0x1.ffbe0000000000000000p+15:0x0040effbe000000000) (INEXACT ) + to int32: 65503 (OK) + to int64: 65503 (OK) + to uint32: 65503 (OK) + to uint64: 65503 (OK) +from single: f32(0x1.ffc00000000000000000p+15:0x477fe000) + to double: f64(0x1.ffc00000000000000000p+15:0x0040effc0000000000) (INEXACT ) + to int32: 65504 (OK) + to int64: 65504 (OK) + to uint32: 65504 (OK) + to uint64: 65504 (OK) +from single: f32(0x1.ffc20000000000000000p+15:0x477fe100) + to double: f64(0x1.ffc20000000000000000p+15:0x0040effc2000000000) (INEXACT ) + to int32: 65505 (OK) + to int64: 65505 (OK) + to uint32: 65505 (OK) + to uint64: 65505 (OK) +from single: f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + to double: f64(0x1.ffbf0000000000000000p+16:0x0040fffbf000000000) (INEXACT ) + to int32: 131007 (OK) + to int64: 131007 (OK) + to uint32: 131007 (OK) + to uint64: 131007 (OK) +from single: f32(0x1.ffc00000000000000000p+16:0x47ffe000) + to double: f64(0x1.ffc00000000000000000p+16:0x0040fffc0000000000) (INEXACT ) + to int32: 131008 (OK) + to int64: 131008 (OK) + to uint32: 131008 (OK) + to uint64: 131008 (OK) +from single: f32(0x1.ffc10000000000000000p+16:0x47ffe080) + to double: f64(0x1.ffc10000000000000000p+16:0x0040fffc1000000000) (INEXACT ) + to int32: 131009 (OK) + to int64: 131009 (OK) + to uint32: 131009 (OK) + to uint64: 131009 (OK) +from single: f32(0x1.c0bab600000000000000p+99:0x71605d5b) + to double: f64(0x1.c0bab600000000000000p+99:0x00462c0bab60000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + to double: f64(0x1.fffffe00000000000000p+127:0x0047efffffe0000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(inf:0x7f800000) + to double: f64(inf:0x007ff0000000000000) (OK) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +### Rounding downwards +from single: f32(-nan:0xffa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0xffc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-inf:0xff800000) + to double: f64(-inf:0x00fff0000000000000) (OK) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + to double: f64(-0x1.fffffe00000000000000p+127:0x00c7efffffe0000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + to double: f64(-0x1.1874b200000000000000p+103:0x00c661874b20000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + to double: f64(-0x1.c0bab600000000000000p+99:0x00c62c0bab60000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.31f75000000000000000p-40:0xab98fba8) + to double: f64(-0x1.31f75000000000000000p-40:0x00bd731f7500000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.50544400000000000000p-66:0x9ea82a22) + to double: f64(-0x1.50544400000000000000p-66:0x00bbd5054440000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.00000000000000000000p-126:0x80800000) + to double: f64(-0x1.00000000000000000000p-126:0x00b810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(0x0.00000000000000000000p+0:0000000000) + to double: f64(0x0.00000000000000000000p+0:00000000000000000000) (OK) + to int32: 0 (OK) + to int64: 0 (OK) + to uint32: 0 (OK) + to uint64: 0 (OK) +from single: f32(0x1.00000000000000000000p-126:0x00800000) + to double: f64(0x1.00000000000000000000p-126:0x003810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p-25:0x33000000) + to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) + to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ff801a00000000000000p-15:0x387fc00d) + to double: f64(0x1.ff801a00000000000000p-15:0x003f0ff801a0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000c00000000000000p-14:0x38800006) + to double: f64(0x1.00000c00000000000000p-14:0x003f100000c0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p+0:0x3f800000) + to double: f64(0x1.00000000000000000000p+0:0x003ff0000000000000) (OK) + to int32: 1 (OK) + to int64: 1 (OK) + to uint32: 1 (OK) + to uint64: 1 (OK) +from single: f32(0x1.00400000000000000000p+0:0x3f802000) + to double: f64(0x1.00400000000000000000p+0:0x003ff0040000000000) (INEXACT ) + to int32: 1 (INEXACT ) + to int64: 1 (INEXACT ) + to uint32: 1 (INEXACT ) + to uint64: 1 (INEXACT ) +from single: f32(0x1.00000000000000000000p+1:0x40000000) + to double: f64(0x1.00000000000000000000p+1:0x004000000000000000) (OK) + to int32: 2 (OK) + to int64: 2 (OK) + to uint32: 2 (OK) + to uint64: 2 (OK) +from single: f32(0x1.5bf0a800000000000000p+1:0x402df854) + to double: f64(0x1.5bf0a800000000000000p+1:0x004005bf0a80000000) (INEXACT ) + to int32: 2 (INEXACT ) + to int64: 2 (INEXACT ) + to uint32: 2 (INEXACT ) + to uint64: 2 (INEXACT ) +from single: f32(0x1.921fb600000000000000p+1:0x40490fdb) + to double: f64(0x1.921fb600000000000000p+1:0x00400921fb60000000) (INEXACT ) + to int32: 3 (INEXACT ) + to int64: 3 (INEXACT ) + to uint32: 3 (INEXACT ) + to uint64: 3 (INEXACT ) +from single: f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + to double: f64(0x1.ffbe0000000000000000p+15:0x0040effbe000000000) (INEXACT ) + to int32: 65503 (OK) + to int64: 65503 (OK) + to uint32: 65503 (OK) + to uint64: 65503 (OK) +from single: f32(0x1.ffc00000000000000000p+15:0x477fe000) + to double: f64(0x1.ffc00000000000000000p+15:0x0040effc0000000000) (INEXACT ) + to int32: 65504 (OK) + to int64: 65504 (OK) + to uint32: 65504 (OK) + to uint64: 65504 (OK) +from single: f32(0x1.ffc20000000000000000p+15:0x477fe100) + to double: f64(0x1.ffc20000000000000000p+15:0x0040effc2000000000) (INEXACT ) + to int32: 65505 (OK) + to int64: 65505 (OK) + to uint32: 65505 (OK) + to uint64: 65505 (OK) +from single: f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + to double: f64(0x1.ffbf0000000000000000p+16:0x0040fffbf000000000) (INEXACT ) + to int32: 131007 (OK) + to int64: 131007 (OK) + to uint32: 131007 (OK) + to uint64: 131007 (OK) +from single: f32(0x1.ffc00000000000000000p+16:0x47ffe000) + to double: f64(0x1.ffc00000000000000000p+16:0x0040fffc0000000000) (INEXACT ) + to int32: 131008 (OK) + to int64: 131008 (OK) + to uint32: 131008 (OK) + to uint64: 131008 (OK) +from single: f32(0x1.ffc10000000000000000p+16:0x47ffe080) + to double: f64(0x1.ffc10000000000000000p+16:0x0040fffc1000000000) (INEXACT ) + to int32: 131009 (OK) + to int64: 131009 (OK) + to uint32: 131009 (OK) + to uint64: 131009 (OK) +from single: f32(0x1.c0bab600000000000000p+99:0x71605d5b) + to double: f64(0x1.c0bab600000000000000p+99:0x00462c0bab60000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + to double: f64(0x1.fffffe00000000000000p+127:0x0047efffffe0000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(inf:0x7f800000) + to double: f64(inf:0x007ff0000000000000) (OK) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +### Rounding to zero +from single: f32(-nan:0xffa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0xffc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-inf:0xff800000) + to double: f64(-inf:0x00fff0000000000000) (OK) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + to double: f64(-0x1.fffffe00000000000000p+127:0x00c7efffffe0000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + to double: f64(-0x1.1874b200000000000000p+103:0x00c661874b20000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + to double: f64(-0x1.c0bab600000000000000p+99:0x00c62c0bab60000000) (INEXACT ) + to int32: -2147483648 (INVALID) + to int64: -9223372036854775808 (INVALID) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.31f75000000000000000p-40:0xab98fba8) + to double: f64(-0x1.31f75000000000000000p-40:0x00bd731f7500000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.50544400000000000000p-66:0x9ea82a22) + to double: f64(-0x1.50544400000000000000p-66:0x00bbd5054440000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(-0x1.00000000000000000000p-126:0x80800000) + to double: f64(-0x1.00000000000000000000p-126:0x00b810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INVALID) + to uint64: 0 (INVALID) +from single: f32(0x0.00000000000000000000p+0:0000000000) + to double: f64(0x0.00000000000000000000p+0:00000000000000000000) (OK) + to int32: 0 (OK) + to int64: 0 (OK) + to uint32: 0 (OK) + to uint64: 0 (OK) +from single: f32(0x1.00000000000000000000p-126:0x00800000) + to double: f64(0x1.00000000000000000000p-126:0x003810000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p-25:0x33000000) + to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) + to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.ff801a00000000000000p-15:0x387fc00d) + to double: f64(0x1.ff801a00000000000000p-15:0x003f0ff801a0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000c00000000000000p-14:0x38800006) + to double: f64(0x1.00000c00000000000000p-14:0x003f100000c0000000) (INEXACT ) + to int32: 0 (INEXACT ) + to int64: 0 (INEXACT ) + to uint32: 0 (INEXACT ) + to uint64: 0 (INEXACT ) +from single: f32(0x1.00000000000000000000p+0:0x3f800000) + to double: f64(0x1.00000000000000000000p+0:0x003ff0000000000000) (OK) + to int32: 1 (OK) + to int64: 1 (OK) + to uint32: 1 (OK) + to uint64: 1 (OK) +from single: f32(0x1.00400000000000000000p+0:0x3f802000) + to double: f64(0x1.00400000000000000000p+0:0x003ff0040000000000) (INEXACT ) + to int32: 1 (INEXACT ) + to int64: 1 (INEXACT ) + to uint32: 1 (INEXACT ) + to uint64: 1 (INEXACT ) +from single: f32(0x1.00000000000000000000p+1:0x40000000) + to double: f64(0x1.00000000000000000000p+1:0x004000000000000000) (OK) + to int32: 2 (OK) + to int64: 2 (OK) + to uint32: 2 (OK) + to uint64: 2 (OK) +from single: f32(0x1.5bf0a800000000000000p+1:0x402df854) + to double: f64(0x1.5bf0a800000000000000p+1:0x004005bf0a80000000) (INEXACT ) + to int32: 2 (INEXACT ) + to int64: 2 (INEXACT ) + to uint32: 2 (INEXACT ) + to uint64: 2 (INEXACT ) +from single: f32(0x1.921fb600000000000000p+1:0x40490fdb) + to double: f64(0x1.921fb600000000000000p+1:0x00400921fb60000000) (INEXACT ) + to int32: 3 (INEXACT ) + to int64: 3 (INEXACT ) + to uint32: 3 (INEXACT ) + to uint64: 3 (INEXACT ) +from single: f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + to double: f64(0x1.ffbe0000000000000000p+15:0x0040effbe000000000) (INEXACT ) + to int32: 65503 (OK) + to int64: 65503 (OK) + to uint32: 65503 (OK) + to uint64: 65503 (OK) +from single: f32(0x1.ffc00000000000000000p+15:0x477fe000) + to double: f64(0x1.ffc00000000000000000p+15:0x0040effc0000000000) (INEXACT ) + to int32: 65504 (OK) + to int64: 65504 (OK) + to uint32: 65504 (OK) + to uint64: 65504 (OK) +from single: f32(0x1.ffc20000000000000000p+15:0x477fe100) + to double: f64(0x1.ffc20000000000000000p+15:0x0040effc2000000000) (INEXACT ) + to int32: 65505 (OK) + to int64: 65505 (OK) + to uint32: 65505 (OK) + to uint64: 65505 (OK) +from single: f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + to double: f64(0x1.ffbf0000000000000000p+16:0x0040fffbf000000000) (INEXACT ) + to int32: 131007 (OK) + to int64: 131007 (OK) + to uint32: 131007 (OK) + to uint64: 131007 (OK) +from single: f32(0x1.ffc00000000000000000p+16:0x47ffe000) + to double: f64(0x1.ffc00000000000000000p+16:0x0040fffc0000000000) (INEXACT ) + to int32: 131008 (OK) + to int64: 131008 (OK) + to uint32: 131008 (OK) + to uint64: 131008 (OK) +from single: f32(0x1.ffc10000000000000000p+16:0x47ffe080) + to double: f64(0x1.ffc10000000000000000p+16:0x0040fffc1000000000) (INEXACT ) + to int32: 131009 (OK) + to int64: 131009 (OK) + to uint32: 131009 (OK) + to uint64: 131009 (OK) +from single: f32(0x1.c0bab600000000000000p+99:0x71605d5b) + to double: f64(0x1.c0bab600000000000000p+99:0x00462c0bab60000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + to double: f64(0x1.fffffe00000000000000p+127:0x0047efffffe0000000) (INEXACT ) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(inf:0x7f800000) + to double: f64(inf:0x007ff0000000000000) (OK) + to int32: 2147483647 (INVALID) + to int64: 9223372036854775807 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fc00000) + to double: f64(-nan:0x00ffffffffffffffff) (OK) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) +from single: f32(-nan:0x7fa00000) + to double: f64(-nan:0x00ffffffffffffffff) (INVALID) + to int32: -1 (INVALID) + to int64: -1 (INVALID) + to uint32: -1 (INVALID) + to uint64: -1 (INVALID) diff --git a/tests/tcg/hexagon/float_madds.ref b/tests/tcg/hexagon/float_madds.ref new file mode 100644 index 0000000..ceed3bb --- /dev/null +++ b/tests/tcg/hexagon/float_madds.ref @@ -0,0 +1,768 @@ +### Rounding to nearest +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=INVALID (0/0) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/1) +op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/2) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(-nan:0xffffffff) flags=OK (1/0) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=OK (1/1) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=OK (1/2) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OK (2/0) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-inf:0xff800000) +res: f32(-inf:0xff800000) flags=OK (2/1) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OK (2/2) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/0) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/1) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/2) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (4/0) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) flags=INEXACT (4/1) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) flags=INEXACT (4/2) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(0x1.0c27fa00000000000000p+60:0x5d8613fd) flags=INEXACT (5/0) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) flags=INEXACT (5/1) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.26c46200000000000000p+34:0x50936231) flags=INEXACT (5/2) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(0x1.91f94000000000000000p-106:0x0ac8fca0) flags=INEXACT (6/0) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(-0x1.31f75000000000000000p-40:0xab98fba8) flags=INEXACT (6/1) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (6/2) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (7/0) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (7/1) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (7/2) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (8/0) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (8/1) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(-0x0.00000000000000000000p+0:0x80000000) flags=UNDERFLOW INEXACT (8/2) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (9/1) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (9/2) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.ffffe600000000000000p-25:0x337ffff3) flags=INEXACT (10/0) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.ffffe600000000000000p-50:0x26fffff3) flags=INEXACT (10/1) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=INEXACT (10/2) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801a00000000000000p-15:0x387fc00d) flags=INEXACT (11/0) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.0007fe00000000000000p-25:0x330003ff) flags=INEXACT (11/1) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0001f200000000000000p-24:0x338000f9) flags=INEXACT (11/2) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00000c00000000000000p-14:0x38800006) flags=INEXACT (12/0) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0ffbf400000000000000p-24:0x3387fdfa) flags=INEXACT (12/1) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801c00000000000000p-15:0x387fc00e) flags=INEXACT (12/2) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00000000000000000000p+0:0x3f800000) flags=INEXACT (13/0) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/1) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/2) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/0) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/1) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00040200000000000000p+0:0x3f800201) flags=INEXACT (14/2) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/0) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.80400000000000000000p+1:0x40402000) flags=INEXACT (15/1) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/2) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.2e185400000000000000p+2:0x40970c2a) flags=INEXACT (16/0) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.9c00a800000000000000p+2:0x40ce0054) flags=INEXACT (16/1) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.2e23d200000000000000p+2:0x409711e9) flags=INEXACT (16/2) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.12804200000000000000p+3:0x41094021) flags=INEXACT (17/0) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.51458000000000000000p+3:0x4128a2c0) flags=INEXACT (17/1) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.200c0400000000000000p+3:0x41100602) flags=INEXACT (17/2) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ffcf1400000000000000p+15:0x477fe78a) flags=INEXACT (18/0) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.91ed3c00000000000000p+17:0x4848f69e) flags=INEXACT (18/1) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.5bc56000000000000000p+17:0x482de2b0) flags=INEXACT (18/2) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.08edf000000000000000p+18:0x488476f8) flags=INEXACT (19/0) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.ff7e0800000000000000p+31:0x4f7fbf04) flags=INEXACT (19/1) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.08ee7a00000000000000p+18:0x4884773d) flags=INEXACT (19/2) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+31:0x4f7fc004) flags=INEXACT (20/0) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ff840800000000000000p+31:0x4f7fc204) flags=INEXACT (20/1) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820800000000000000p+31:0x4f7fc104) flags=INEXACT (20/2) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff860800000000000000p+31:0x4f7fc304) flags=INEXACT (21/0) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820800000000000000p+32:0x4fffc104) flags=INEXACT (21/1) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+32:0x4fffc004) flags=INEXACT (21/2) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff830800000000000000p+32:0x4fffc184) flags=INEXACT (22/0) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff7f8800000000000000p+33:0x507fbfc4) flags=INEXACT (22/1) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff840800000000000000p+32:0x4fffc204) flags=INEXACT (22/2) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.ff800800000000000000p+33:0x507fc004) flags=INEXACT (23/0) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff820800000000000000p+33:0x507fc104) flags=INEXACT (23/1) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff810800000000000000p+33:0x507fc084) flags=INEXACT (23/2) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.c0bab600000000000000p+99:0x71605d5b) flags=INEXACT (24/0) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.c0838000000000000000p+116:0x79e041c0) flags=INEXACT (24/1) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.c0829e00000000000000p+116:0x79e0414f) flags=INEXACT (24/2) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/0) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/1) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/2) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(inf:0x7f800000) flags=OK (26/0) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OK (26/1) +op : f32(inf:0x7f800000) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OK (26/2) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=OK (27/0) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(-nan:0xffffffff) flags=OK (27/1) +op : f32(-nan:0x7fc00000) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=OK (27/2) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/0) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=INVALID (28/1) +op : f32(-nan:0x7fa00000) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/2) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/0) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/1) +op : f32(-nan:0xffa00000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/2) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/0) +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/1) +op : f32(-nan:0xffc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/2) +# LP184149 +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-1:0x3f000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=OK (31/0) +op : f32(0x1.00000000000000000000p-149:0x00000001) * f32(0x1.00000000000000000000p-149:0x00000001) + f32(0x1.00000000000000000000p-149:0x00000001) +res: f32(0x1.00000000000000000000p-149:0x00000001) flags=UNDERFLOW INEXACT (32/0) +### Rounding upwards +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=INVALID (0/0) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/1) +op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/2) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(-nan:0xffffffff) flags=OK (1/0) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=OK (1/1) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=OK (1/2) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OK (2/0) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-inf:0xff800000) +res: f32(-inf:0xff800000) flags=OK (2/1) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OK (2/2) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/0) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/1) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (3/2) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (4/0) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(-0x1.1874b000000000000000p+103:0xf30c3a58) flags=INEXACT (4/1) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab400000000000000p+99:0xf1605d5a) flags=INEXACT (4/2) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(0x1.0c27fa00000000000000p+60:0x5d8613fd) flags=INEXACT (5/0) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab400000000000000p+99:0xf1605d5a) flags=INEXACT (5/1) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.26c46200000000000000p+34:0x50936231) flags=INEXACT (5/2) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(0x1.91f94000000000000000p-106:0x0ac8fca0) flags=INEXACT (6/0) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(-0x1.31f74e00000000000000p-40:0xab98fba7) flags=INEXACT (6/1) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544200000000000000p-66:0x9ea82a21) flags=INEXACT (6/2) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x1.00000000000000000000p-149:0x00000001) flags=UNDERFLOW INEXACT (7/0) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (7/1) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (7/2) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (8/0) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (8/1) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(-0x0.00000000000000000000p+0:0x80000000) flags=UNDERFLOW INEXACT (8/2) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x1.00000000000000000000p-149:0x00000001) flags=UNDERFLOW INEXACT (9/1) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (9/2) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.ffffe800000000000000p-25:0x337ffff4) flags=INEXACT (10/0) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.ffffe800000000000000p-50:0x26fffff4) flags=INEXACT (10/1) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000200000000000000p-25:0x33000001) flags=INEXACT (10/2) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801c00000000000000p-15:0x387fc00e) flags=INEXACT (11/0) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00080000000000000000p-25:0x33000400) flags=INEXACT (11/1) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0001f400000000000000p-24:0x338000fa) flags=INEXACT (11/2) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00000e00000000000000p-14:0x38800007) flags=INEXACT (12/0) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0ffbf600000000000000p-24:0x3387fdfb) flags=INEXACT (12/1) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801c00000000000000p-15:0x387fc00e) flags=INEXACT (12/2) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00000200000000000000p+0:0x3f800001) flags=INEXACT (13/0) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ffc01a00000000000000p-14:0x38ffe00d) flags=INEXACT (13/1) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.ffc01a00000000000000p-14:0x38ffe00d) flags=INEXACT (13/2) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.00440200000000000000p+0:0x3f802201) flags=INEXACT (14/0) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00440200000000000000p+0:0x3f802201) flags=INEXACT (14/1) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00040200000000000000p+0:0x3f800201) flags=INEXACT (14/2) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/0) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.80400000000000000000p+1:0x40402000) flags=INEXACT (15/1) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/2) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.2e185400000000000000p+2:0x40970c2a) flags=INEXACT (16/0) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.9c00a800000000000000p+2:0x40ce0054) flags=INEXACT (16/1) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.2e23d400000000000000p+2:0x409711ea) flags=INEXACT (16/2) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.12804200000000000000p+3:0x41094021) flags=INEXACT (17/0) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.51458200000000000000p+3:0x4128a2c1) flags=INEXACT (17/1) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.200c0600000000000000p+3:0x41100603) flags=INEXACT (17/2) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ffcf1600000000000000p+15:0x477fe78b) flags=INEXACT (18/0) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.91ed3c00000000000000p+17:0x4848f69e) flags=INEXACT (18/1) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.5bc56200000000000000p+17:0x482de2b1) flags=INEXACT (18/2) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.08edf000000000000000p+18:0x488476f8) flags=INEXACT (19/0) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.ff7e0a00000000000000p+31:0x4f7fbf05) flags=INEXACT (19/1) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.08ee7a00000000000000p+18:0x4884773d) flags=INEXACT (19/2) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800a00000000000000p+31:0x4f7fc005) flags=INEXACT (20/0) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ff840800000000000000p+31:0x4f7fc204) flags=INEXACT (20/1) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820800000000000000p+31:0x4f7fc104) flags=INEXACT (20/2) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff860800000000000000p+31:0x4f7fc304) flags=INEXACT (21/0) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820800000000000000p+32:0x4fffc104) flags=INEXACT (21/1) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800a00000000000000p+32:0x4fffc005) flags=INEXACT (21/2) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff830800000000000000p+32:0x4fffc184) flags=INEXACT (22/0) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff7f8a00000000000000p+33:0x507fbfc5) flags=INEXACT (22/1) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff840800000000000000p+32:0x4fffc204) flags=INEXACT (22/2) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.ff800a00000000000000p+33:0x507fc005) flags=INEXACT (23/0) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff820800000000000000p+33:0x507fc104) flags=INEXACT (23/1) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff810800000000000000p+33:0x507fc084) flags=INEXACT (23/2) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.c0bab800000000000000p+99:0x71605d5c) flags=INEXACT (24/0) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.c0838000000000000000p+116:0x79e041c0) flags=INEXACT (24/1) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.c082a000000000000000p+116:0x79e04150) flags=INEXACT (24/2) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/0) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/1) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OVERFLOW INEXACT (25/2) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(inf:0x7f800000) flags=OK (26/0) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OK (26/1) +op : f32(inf:0x7f800000) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OK (26/2) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=OK (27/0) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(-nan:0xffffffff) flags=OK (27/1) +op : f32(-nan:0x7fc00000) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=OK (27/2) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/0) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=INVALID (28/1) +op : f32(-nan:0x7fa00000) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/2) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/0) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/1) +op : f32(-nan:0xffa00000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/2) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/0) +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/1) +op : f32(-nan:0xffc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/2) +# LP184149 +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-1:0x3f000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=OK (31/0) +op : f32(0x1.00000000000000000000p-149:0x00000001) * f32(0x1.00000000000000000000p-149:0x00000001) + f32(0x1.00000000000000000000p-149:0x00000001) +res: f32(0x1.00000000000000000000p-148:0x00000002) flags=UNDERFLOW INEXACT (32/0) +### Rounding downwards +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=INVALID (0/0) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/1) +op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/2) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(-nan:0xffffffff) flags=OK (1/0) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=OK (1/1) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=OK (1/2) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OK (2/0) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-inf:0xff800000) +res: f32(-inf:0xff800000) flags=OK (2/1) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OK (2/2) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/0) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/1) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/2) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (4/0) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(-0x1.1874b200000000000000p+103:0xf30c3a59) flags=INEXACT (4/1) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) flags=INEXACT (4/2) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(0x1.0c27f800000000000000p+60:0x5d8613fc) flags=INEXACT (5/0) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) flags=INEXACT (5/1) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.26c46000000000000000p+34:0x50936230) flags=INEXACT (5/2) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(0x1.91f93e00000000000000p-106:0x0ac8fc9f) flags=INEXACT (6/0) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(-0x1.31f75000000000000000p-40:0xab98fba8) flags=INEXACT (6/1) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (6/2) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (7/0) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (7/1) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (7/2) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (8/0) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (8/1) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(-0x1.00000000000000000000p-149:0x80000001) flags=UNDERFLOW INEXACT (8/2) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (9/1) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (9/2) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.ffffe600000000000000p-25:0x337ffff3) flags=INEXACT (10/0) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.ffffe600000000000000p-50:0x26fffff3) flags=INEXACT (10/1) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=INEXACT (10/2) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801a00000000000000p-15:0x387fc00d) flags=INEXACT (11/0) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.0007fe00000000000000p-25:0x330003ff) flags=INEXACT (11/1) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0001f200000000000000p-24:0x338000f9) flags=INEXACT (11/2) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00000c00000000000000p-14:0x38800006) flags=INEXACT (12/0) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0ffbf400000000000000p-24:0x3387fdfa) flags=INEXACT (12/1) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801a00000000000000p-15:0x387fc00d) flags=INEXACT (12/2) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00000000000000000000p+0:0x3f800000) flags=INEXACT (13/0) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/1) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/2) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/0) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/1) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00040000000000000000p+0:0x3f800200) flags=INEXACT (14/2) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/0) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.80400000000000000000p+1:0x40402000) flags=INEXACT (15/1) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/2) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.2e185400000000000000p+2:0x40970c2a) flags=INEXACT (16/0) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.9c00a800000000000000p+2:0x40ce0054) flags=INEXACT (16/1) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.2e23d200000000000000p+2:0x409711e9) flags=INEXACT (16/2) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.12804000000000000000p+3:0x41094020) flags=INEXACT (17/0) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.51458000000000000000p+3:0x4128a2c0) flags=INEXACT (17/1) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.200c0400000000000000p+3:0x41100602) flags=INEXACT (17/2) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ffcf1400000000000000p+15:0x477fe78a) flags=INEXACT (18/0) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.91ed3a00000000000000p+17:0x4848f69d) flags=INEXACT (18/1) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.5bc56000000000000000p+17:0x482de2b0) flags=INEXACT (18/2) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.08edee00000000000000p+18:0x488476f7) flags=INEXACT (19/0) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.ff7e0800000000000000p+31:0x4f7fbf04) flags=INEXACT (19/1) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.08ee7800000000000000p+18:0x4884773c) flags=INEXACT (19/2) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+31:0x4f7fc004) flags=INEXACT (20/0) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ff840600000000000000p+31:0x4f7fc203) flags=INEXACT (20/1) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820600000000000000p+31:0x4f7fc103) flags=INEXACT (20/2) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff860600000000000000p+31:0x4f7fc303) flags=INEXACT (21/0) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820600000000000000p+32:0x4fffc103) flags=INEXACT (21/1) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+32:0x4fffc004) flags=INEXACT (21/2) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff830600000000000000p+32:0x4fffc183) flags=INEXACT (22/0) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff7f8800000000000000p+33:0x507fbfc4) flags=INEXACT (22/1) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff840600000000000000p+32:0x4fffc203) flags=INEXACT (22/2) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.ff800800000000000000p+33:0x507fc004) flags=INEXACT (23/0) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff820600000000000000p+33:0x507fc103) flags=INEXACT (23/1) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff810600000000000000p+33:0x507fc083) flags=INEXACT (23/2) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.c0bab600000000000000p+99:0x71605d5b) flags=INEXACT (24/0) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.c0837e00000000000000p+116:0x79e041bf) flags=INEXACT (24/1) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.c0829e00000000000000p+116:0x79e0414f) flags=INEXACT (24/2) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/0) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/1) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/2) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(inf:0x7f800000) flags=OK (26/0) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OK (26/1) +op : f32(inf:0x7f800000) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OK (26/2) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=OK (27/0) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(-nan:0xffffffff) flags=OK (27/1) +op : f32(-nan:0x7fc00000) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=OK (27/2) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/0) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=INVALID (28/1) +op : f32(-nan:0x7fa00000) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/2) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/0) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/1) +op : f32(-nan:0xffa00000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/2) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/0) +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/1) +op : f32(-nan:0xffc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/2) +# LP184149 +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-1:0x3f000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=OK (31/0) +op : f32(0x1.00000000000000000000p-149:0x00000001) * f32(0x1.00000000000000000000p-149:0x00000001) + f32(0x1.00000000000000000000p-149:0x00000001) +res: f32(0x1.00000000000000000000p-149:0x00000001) flags=UNDERFLOW INEXACT (32/0) +### Rounding to zero +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=INVALID (0/0) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/1) +op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (0/2) +op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(-nan:0xffffffff) flags=OK (1/0) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=OK (1/1) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) +res: f32(-nan:0xffffffff) flags=OK (1/2) +op : f32(-inf:0xff800000) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(inf:0x7f800000) flags=OK (2/0) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-inf:0xff800000) +res: f32(-inf:0xff800000) flags=OK (2/1) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-inf:0xff800000) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(inf:0x7f800000) flags=OK (2/2) +op : f32(-0x1.fffffe00000000000000p+127:0xff7fffff) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/0) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.fffffe00000000000000p+127:0xff7fffff) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/1) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.fffffe00000000000000p+127:0xff7fffff) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (3/2) +op : f32(-0x1.1874b200000000000000p+103:0xf30c3a59) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (4/0) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.1874b200000000000000p+103:0xf30c3a59) +res: f32(-0x1.1874b000000000000000p+103:0xf30c3a58) flags=INEXACT (4/1) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.1874b200000000000000p+103:0xf30c3a59) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab400000000000000p+99:0xf1605d5a) flags=INEXACT (4/2) +op : f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(0x1.0c27f800000000000000p+60:0x5d8613fc) flags=INEXACT (5/0) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) +res: f32(-0x1.c0bab400000000000000p+99:0xf1605d5a) flags=INEXACT (5/1) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.c0bab600000000000000p+99:0xf1605d5b) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(0x1.26c46000000000000000p+34:0x50936230) flags=INEXACT (5/2) +op : f32(-0x1.31f75000000000000000p-40:0xab98fba8) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(0x1.91f93e00000000000000p-106:0x0ac8fc9f) flags=INEXACT (6/0) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(-0x1.31f75000000000000000p-40:0xab98fba8) +res: f32(-0x1.31f74e00000000000000p-40:0xab98fba7) flags=INEXACT (6/1) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(-0x1.31f75000000000000000p-40:0xab98fba8) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544200000000000000p-66:0x9ea82a21) flags=INEXACT (6/2) +op : f32(-0x1.50544400000000000000p-66:0x9ea82a22) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (7/0) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(-0x1.50544400000000000000p-66:0x9ea82a22) +res: f32(-0x1.50544400000000000000p-66:0x9ea82a22) flags=INEXACT (7/1) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(-0x1.50544400000000000000p-66:0x9ea82a22) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (7/2) +op : f32(-0x1.00000000000000000000p-126:0x80800000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (8/0) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(-0x1.00000000000000000000p-126:0x80800000) +res: f32(-0x1.00000000000000000000p-126:0x80800000) flags=OK (8/1) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(-0x1.00000000000000000000p-126:0x80800000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(-0x0.00000000000000000000p+0:0x80000000) flags=UNDERFLOW INEXACT (8/2) +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=UNDERFLOW INEXACT (9/1) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.00000000000000000000p-126:0x00800000) flags=OK (9/2) +op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.ffffe600000000000000p-25:0x337ffff3) flags=INEXACT (10/0) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.00000000000000000000p-126:0x00800000) +res: f32(0x1.ffffe600000000000000p-50:0x26fffff3) flags=INEXACT (10/1) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.00000000000000000000p-25:0x33000000) flags=INEXACT (10/2) +op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801a00000000000000p-15:0x387fc00d) flags=INEXACT (11/0) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000000000000000000p-25:0x33000000) +res: f32(0x1.0007fe00000000000000p-25:0x330003ff) flags=INEXACT (11/1) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0001f200000000000000p-24:0x338000f9) flags=INEXACT (11/2) +op : f32(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00000c00000000000000p-14:0x38800006) flags=INEXACT (12/0) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.ffffe600000000000000p-25:0x337ffff3) +res: f32(0x1.0ffbf400000000000000p-24:0x3387fdfa) flags=INEXACT (12/1) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ff801a00000000000000p-15:0x387fc00d) flags=INEXACT (12/2) +op : f32(0x1.ff801a00000000000000p-15:0x387fc00d) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00000000000000000000p+0:0x3f800000) flags=INEXACT (13/0) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.ff801a00000000000000p-15:0x387fc00d) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/1) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.ff801a00000000000000p-15:0x387fc00d) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.ffc01800000000000000p-14:0x38ffe00c) flags=INEXACT (13/2) +op : f32(0x1.00000c00000000000000p-14:0x38800006) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/0) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000c00000000000000p-14:0x38800006) +res: f32(0x1.00440000000000000000p+0:0x3f802200) flags=INEXACT (14/1) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000c00000000000000p-14:0x38800006) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.00040000000000000000p+0:0x3f800200) flags=INEXACT (14/2) +op : f32(0x1.00000000000000000000p+0:0x3f800000) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/0) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.00000000000000000000p+0:0x3f800000) +res: f32(0x1.80400000000000000000p+1:0x40402000) flags=INEXACT (15/1) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.00000000000000000000p+0:0x3f800000) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.80200000000000000000p+1:0x40401000) flags=INEXACT (15/2) +op : f32(0x1.00400000000000000000p+0:0x3f802000) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.2e185400000000000000p+2:0x40970c2a) flags=INEXACT (16/0) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.00400000000000000000p+0:0x3f802000) +res: f32(0x1.9c00a800000000000000p+2:0x40ce0054) flags=INEXACT (16/1) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.00400000000000000000p+0:0x3f802000) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.2e23d200000000000000p+2:0x409711e9) flags=INEXACT (16/2) +op : f32(0x1.00000000000000000000p+1:0x40000000) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.12804000000000000000p+3:0x41094020) flags=INEXACT (17/0) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.00000000000000000000p+1:0x40000000) +res: f32(0x1.51458000000000000000p+3:0x4128a2c0) flags=INEXACT (17/1) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.00000000000000000000p+1:0x40000000) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.200c0400000000000000p+3:0x41100602) flags=INEXACT (17/2) +op : f32(0x1.5bf0a800000000000000p+1:0x402df854) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ffcf1400000000000000p+15:0x477fe78a) flags=INEXACT (18/0) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.5bf0a800000000000000p+1:0x402df854) +res: f32(0x1.91ed3a00000000000000p+17:0x4848f69d) flags=INEXACT (18/1) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.5bf0a800000000000000p+1:0x402df854) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.5bc56000000000000000p+17:0x482de2b0) flags=INEXACT (18/2) +op : f32(0x1.921fb600000000000000p+1:0x40490fdb) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.08edee00000000000000p+18:0x488476f7) flags=INEXACT (19/0) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.921fb600000000000000p+1:0x40490fdb) +res: f32(0x1.ff7e0800000000000000p+31:0x4f7fbf04) flags=INEXACT (19/1) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.921fb600000000000000p+1:0x40490fdb) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.08ee7800000000000000p+18:0x4884773c) flags=INEXACT (19/2) +op : f32(0x1.ffbe0000000000000000p+15:0x477fdf00) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+31:0x4f7fc004) flags=INEXACT (20/0) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbe0000000000000000p+15:0x477fdf00) +res: f32(0x1.ff840600000000000000p+31:0x4f7fc203) flags=INEXACT (20/1) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbe0000000000000000p+15:0x477fdf00) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820600000000000000p+31:0x4f7fc103) flags=INEXACT (20/2) +op : f32(0x1.ffc00000000000000000p+15:0x477fe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff860600000000000000p+31:0x4f7fc303) flags=INEXACT (21/0) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+15:0x477fe000) +res: f32(0x1.ff820600000000000000p+32:0x4fffc103) flags=INEXACT (21/1) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+15:0x477fe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff800800000000000000p+32:0x4fffc004) flags=INEXACT (21/2) +op : f32(0x1.ffc20000000000000000p+15:0x477fe100) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff830600000000000000p+32:0x4fffc183) flags=INEXACT (22/0) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc20000000000000000p+15:0x477fe100) +res: f32(0x1.ff7f8800000000000000p+33:0x507fbfc4) flags=INEXACT (22/1) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc20000000000000000p+15:0x477fe100) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff840600000000000000p+32:0x4fffc203) flags=INEXACT (22/2) +op : f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.ff800800000000000000p+33:0x507fc004) flags=INEXACT (23/0) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) +res: f32(0x1.ff820600000000000000p+33:0x507fc103) flags=INEXACT (23/1) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.ffbf0000000000000000p+16:0x47ffdf80) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.ff810600000000000000p+33:0x507fc083) flags=INEXACT (23/2) +op : f32(0x1.ffc00000000000000000p+16:0x47ffe000) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.c0bab600000000000000p+99:0x71605d5b) flags=INEXACT (24/0) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.ffc00000000000000000p+16:0x47ffe000) +res: f32(0x1.c0837e00000000000000p+116:0x79e041bf) flags=INEXACT (24/1) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.ffc00000000000000000p+16:0x47ffe000) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.c0829e00000000000000p+116:0x79e0414f) flags=INEXACT (24/2) +op : f32(0x1.ffc10000000000000000p+16:0x47ffe080) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/0) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(0x1.ffc10000000000000000p+16:0x47ffe080) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/1) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(0x1.ffc10000000000000000p+16:0x47ffe080) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(0x1.fffffe00000000000000p+127:0x7f7fffff) flags=OVERFLOW INEXACT (25/2) +op : f32(0x1.c0bab600000000000000p+99:0x71605d5b) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(inf:0x7f800000) flags=OK (26/0) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(0x1.c0bab600000000000000p+99:0x71605d5b) +res: f32(inf:0x7f800000) flags=OK (26/1) +op : f32(inf:0x7f800000) * f32(0x1.c0bab600000000000000p+99:0x71605d5b) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(inf:0x7f800000) flags=OK (26/2) +op : f32(0x1.fffffe00000000000000p+127:0x7f7fffff) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=OK (27/0) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(0x1.fffffe00000000000000p+127:0x7f7fffff) +res: f32(-nan:0xffffffff) flags=OK (27/1) +op : f32(-nan:0x7fc00000) * f32(0x1.fffffe00000000000000p+127:0x7f7fffff) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=OK (27/2) +op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/0) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(inf:0x7f800000) +res: f32(-nan:0xffffffff) flags=INVALID (28/1) +op : f32(-nan:0x7fa00000) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (28/2) +op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/0) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0x7fc00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/1) +op : f32(-nan:0xffa00000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (29/2) +op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/0) +op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-nan:0x7fa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/1) +op : f32(-nan:0xffc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) +res: f32(-nan:0xffffffff) flags=INVALID (30/2) +# LP184149 +op : f32(0x0.00000000000000000000p+0:0000000000) * f32(0x1.00000000000000000000p-1:0x3f000000) + f32(0x0.00000000000000000000p+0:0000000000) +res: f32(0x0.00000000000000000000p+0:0000000000) flags=OK (31/0) +op : f32(0x1.00000000000000000000p-149:0x00000001) * f32(0x1.00000000000000000000p-149:0x00000001) + f32(0x1.00000000000000000000p-149:0x00000001) +res: f32(0x1.00000000000000000000p-149:0x00000001) flags=UNDERFLOW INEXACT (32/0) From patchwork Thu Oct 29 23:58:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316564 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, 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bh=YVsXoRCKAZNPEpK4XIGOin1bYm66rsiY07JCxl50F1c=; b=g+dXfEnfgigS7+hMitkA32zriVwaHRcNQ93Y+hxah6ronpXQ4rvJDMK+ suC3H8xWpx/6NAttsgLCbSvDDvY0buU7qsASFQheo26sM9bIBniery2Dr ZZEhZmBiUbBXPkXidbkIWGa/u0IYHHCRd09GOI4IBegS92M1hyFOn10Bp 8=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 29 Oct 2020 16:58:57 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg04-sd.qualcomm.com with ESMTP; 29 Oct 2020 16:58:56 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id B80854119; Thu, 29 Oct 2020 18:58:56 -0500 (CDT) From: Taylor Simpson To: tsimpson@quicinc.com Subject: [RFC PATCH v5 33/33] Add Dockerfile for hexagon Date: Thu, 29 Oct 2020 18:58:50 -0500 Message-Id: <1604015931-23005-34-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604015931-23005-1-git-send-email-tsimpson@quicinc.com> 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qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alessandro Di Federico Signed-off-by: Taylor Simpson --- .../debian-hexagon-cross.build-toolchain.sh | 141 +++++++++++++++++++++ .../docker/dockerfiles/debian-hexagon-cross.docker | 18 +++ 2 files changed, 159 insertions(+) create mode 100755 tests/docker/dockerfiles/debian-hexagon-cross.build-toolchain.sh create mode 100644 tests/docker/dockerfiles/debian-hexagon-cross.docker diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.build-toolchain.sh b/tests/docker/dockerfiles/debian-hexagon-cross.build-toolchain.sh new file mode 100755 index 0000000..a08c6cd --- /dev/null +++ b/tests/docker/dockerfiles/debian-hexagon-cross.build-toolchain.sh @@ -0,0 +1,141 @@ +#!/bin/bash + +set -e + +BASE=$(readlink -f ${PWD}) + +TOOLCHAIN_INSTALL=$(readlink -f "$TOOLCHAIN_INSTALL") +ROOTFS=$(readlink -f "$ROOTFS") + +TOOLCHAIN_BIN=${TOOLCHAIN_INSTALL}/bin +HEX_SYSROOT=${TOOLCHAIN_INSTALL}/hexagon-unknown-linux-musl +HEX_TOOLS_TARGET_BASE=${HEX_SYSROOT}/usr + +function cdp() { + DIR="$1" + mkdir -p "$DIR" + cd "$DIR" +} + +function fetch() { + DIR="$1" + URL="$2" + TEMP="$(readlink -f "$PWD/tmp.tar.gz")" + wget --quiet "$URL" -O "$TEMP" + cdp "$DIR" + tar xaf "$TEMP" --strip-components=1 + rm "$TEMP" + cd - +} + +build_llvm_clang() { + fetch "$BASE/llvm-project" "$LLVM_URL" + cdp "$BASE/build-llvm" + + cmake -G Ninja \ + -DCMAKE_BUILD_TYPE=Release \ + -DCMAKE_INSTALL_PREFIX=${TOOLCHAIN_INSTALL} \ + -DLLVM_ENABLE_LLD=ON \ + -DLLVM_TARGETS_TO_BUILD="X86;Hexagon" \ + -DLLVM_ENABLE_PROJECTS="clang;lld" \ + "$BASE/llvm-project/llvm" + ninja all install + cd ${TOOLCHAIN_BIN} + ln -sf clang hexagon-unknown-linux-musl-clang + ln -sf clang++ hexagon-unknown-linux-musl-clang++ + ln -sf llvm-ar hexagon-unknown-linux-musl-ar + ln -sf llvm-objdump hexagon-unknown-linux-musl-objdump + ln -sf llvm-objcopy hexagon-unknown-linux-musl-objcopy + ln -sf llvm-readelf hexagon-unknown-linux-musl-readelf + ln -sf llvm-ranlib hexagon-unknown-linux-musl-ranlib + + # workaround for now: + cat < hexagon-unknown-linux-musl.cfg +-G0 --sysroot=${HEX_SYSROOT} +EOF +} + +build_clang_rt() { + cdp "$BASE/build-clang_rt" + cmake -G Ninja \ + -DCMAKE_BUILD_TYPE=Release \ + -DLLVM_CONFIG_PATH="$BASE/build-llvm/bin/llvm-config" \ + -DCMAKE_ASM_FLAGS="-G0 -mlong-calls -fno-pic --target=hexagon-unknown-linux-musl " \ + -DCMAKE_SYSTEM_NAME=Linux \ + -DCMAKE_C_COMPILER="${TOOLCHAIN_BIN}/hexagon-unknown-linux-musl-clang" \ + -DCMAKE_ASM_COMPILER="${TOOLCHAIN_BIN}/hexagon-unknown-linux-musl-clang" \ + -DCMAKE_INSTALL_PREFIX=${HEX_TOOLS_TARGET_BASE} \ + -DCMAKE_CROSSCOMPILING=ON \ + -DCMAKE_C_COMPILER_FORCED=ON \ + -DCMAKE_CXX_COMPILER_FORCED=ON \ + -DCOMPILER_RT_BUILD_BUILTINS=ON \ + -DCOMPILER_RT_BUILTINS_ENABLE_PIC=OFF \ + -DCMAKE_SIZEOF_VOID_P=4 \ + -DCOMPILER_RT_OS_DIR= \ + -DCAN_TARGET_hexagon=1 \ + -DCAN_TARGET_x86_64=0 \ + -DCOMPILER_RT_SUPPORTED_ARCH=hexagon \ + -DLLVM_ENABLE_PROJECTS="compiler-rt" \ + "$BASE/llvm-project/compiler-rt" + ninja install-compiler-rt +} + +build_musl_headers() { + fetch "$BASE/musl" "$MUSL_URL" + cd "$BASE/musl" + make clean + CC=${TOOLCHAIN_BIN}/hexagon-unknown-linux-musl-clang \ + CROSS_COMPILE=hexagon-unknown-linux-musl \ + LIBCC=${HEX_TOOLS_TARGET_BASE}/lib/libclang_rt.builtins-hexagon.a \ + CROSS_CFLAGS="-G0 -O0 -mv65 -fno-builtin -fno-rounding-math --target=hexagon-unknown-linux-musl" \ + ./configure --target=hexagon --prefix=${HEX_TOOLS_TARGET_BASE} + PATH=${TOOLCHAIN_BIN}:$PATH make CROSS_COMPILE= install-headers + + cd ${HEX_SYSROOT}/.. + ln -sf hexagon-unknown-linux-musl hexagon +} + +build_kernel_headers() { + fetch "$BASE/linux" "$LINUX_URL" + mkdir -p "$BASE/build-linux" + cd "$BASE/linux" + make O=../build-linux ARCH=hexagon \ + KBUILD_CFLAGS_KERNEL="-mlong-calls" \ + CC=${TOOLCHAIN_BIN}/hexagon-unknown-linux-musl-clang \ + LD=${TOOLCHAIN_BIN}/ld.lld \ + KBUILD_VERBOSE=1 comet_defconfig + make mrproper + + cd "$BASE/build-linux" + make \ + ARCH=hexagon \ + CC=${TOOLCHAIN_BIN}/clang \ + INSTALL_HDR_PATH=${HEX_TOOLS_TARGET_BASE} \ + V=1 \ + headers_install +} + +build_musl() { + cd "$BASE/musl" + make clean + CROSS_COMPILE=hexagon-unknown-linux-musl- \ + AR=llvm-ar \ + RANLIB=llvm-ranlib \ + STRIP=llvm-strip \ + CC=clang \ + LIBCC=${HEX_TOOLS_TARGET_BASE}/lib/libclang_rt.builtins-hexagon.a \ + CFLAGS="-G0 -O0 -mv65 -fno-builtin -fno-rounding-math --target=hexagon-unknown-linux-musl" \ + ./configure --target=hexagon --prefix=${HEX_TOOLS_TARGET_BASE} + PATH=${TOOLCHAIN_BIN}/:$PATH make -j CROSS_COMPILE= install + cd ${HEX_TOOLS_TARGET_BASE}/lib + ln -sf libc.so ld-musl-hexagon.so + ln -sf ld-musl-hexagon.so ld-musl-hexagon.so.1 + cdp ${HEX_TOOLS_TARGET_BASE}/../lib + ln -sf ../usr/lib/ld-musl-hexagon.so.1 +} + +build_llvm_clang +build_kernel_headers +build_musl_headers +build_clang_rt +build_musl diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.docker b/tests/docker/dockerfiles/debian-hexagon-cross.docker new file mode 100644 index 0000000..355adbf --- /dev/null +++ b/tests/docker/dockerfiles/debian-hexagon-cross.docker @@ -0,0 +1,18 @@ +FROM debian:10 + +RUN apt update && \ + DEBIAN_FRONTEND=noninteractive \ + apt install -y --no-install-recommends \ + ca-certificates build-essential cmake clang lld ninja-build \ + flex bison pkg-config wget python3 rsync + +ENV TOOLCHAIN_INSTALL /usr +ENV ROOTFS /usr + +ENV LLVM_URL https://github.com/llvm/llvm-project/archive/3d8149c2a1228609fd7d7c91a04681304a2f0ca9.tar.gz +ENV MUSL_URL https://github.com/quic/musl/archive/aff74b395fbf59cd7e93b3691905aa1af6c0778c.tar.gz +ENV LINUX_URL https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.6.18.tar.xz + +COPY debian-hexagon-cross.build-toolchain.sh /root/hexagon-toolchain/ + +RUN cd /root/hexagon-toolchain/ && ./debian-hexagon-cross.build-toolchain.sh && cd / && rm -rf /root/hexagon-toolchain/