From patchwork Thu Dec 28 15:10:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 122842 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3567451qgn; Thu, 28 Dec 2017 07:12:05 -0800 (PST) X-Google-Smtp-Source: ACJfBospfrGCHvpZp3BE2p/SW7SHwSbFGSeC3lzYNDYar39KuxLLbQVwdD9qyQ+vXYU/nJHhjMWA X-Received: by 10.80.163.138 with SMTP id s10mr39967212edb.302.1514473925675; Thu, 28 Dec 2017 07:12:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1514473925; cv=none; d=google.com; s=arc-20160816; b=VzfNQWG2dFJH8UZwyQo3uidEwTr1w14FMV2S8tkWTW9GZWyzFeGeNT5z+4/Lrh6pZS Cg2Z1o5DBk0r0t9/lZrDPdHEMTkSgOkuzsZezl4FgfvfGTCEad4CNdReKHualcDwgQf+ e7xtuy/v2xNh7B48Iu6EtDctBZa6TVYbqVDQ51wIz/Fp35608rxHpNxauaQF5A4nywbz /ufN/VIGNOneE/2OSnCZcL5PGLqxuldDHPPRWT5fpzIQsA4zFX+jLjLBL9TcYZSmJR6l m4iZB1CFv7Ywj3meSpwhkjIZE1mHAwrkU5Xvav69W6eE/SBEAlCIeSi/vihtEjbvm4tt ozBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=L4W7b301fk6kxGvYmUr0d5eg7pthZpShBTA8/RzchBg=; b=VKqzfSkSd/k0TAHyGvYrifQNMeWM5cxy2Janj9rQa0E18b8LADvLQ6yGkIIW4gzofS Eyg8F0//d1KrHizmSw0En2kKrApa0a/+6g5GnKgeqdG5oAQReE5wpkxtTT5b2owZ8Ke+ gmfOqBDaqzGS7z6Vrh52XmIhgMs7IJ7hKtAyPdVrQsgAw10DBjiiWkbMKGhonK51iM7F Ch8TgL/5Jd9ot71nHANg+sGVZdbzi4qLSNheYWIe7lkPJjuJmWtblLzSbLwhZWitGFbN whdaaYWr9OCvMPNeAVgrHYWB3mPB1ud1clivteMx4M3LXB5DbwfBuBGYWr6SU3Z8joQ8 Q9Iw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=h3SffQ+x; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id o59si835587edb.232.2017.12.28.07.12.05; Thu, 28 Dec 2017 07:12:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=h3SffQ+x; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 111DDC21DDB; Thu, 28 Dec 2017 15:11:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 82619C21DDF; Thu, 28 Dec 2017 15:10:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 98235C21D5D; Thu, 28 Dec 2017 15:10:54 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 7B80FC21DB2 for ; Thu, 28 Dec 2017 15:10:50 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBSFAm5f031714; Thu, 28 Dec 2017 09:10:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1514473848; bh=AcAFRplinuCCSq8UHw+6jrjXfApu6TYc71CA4+2TKS4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=h3SffQ+xVGGQFAUBLsqVk2ZiFIzzfh8fQbAaPb0Sc+Dvm2mTta5BuxpE0fNiH3XdQ x8fkwUC0Y8lGsVdnE33v+4yN42U5AgBaGETjboA7VxsBkSUEN68QS2F4NNqp9fiE5q Se0XL0JjsHFJzsBOFBYJHsmq/hK+CP6SeTXf4n+0= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBSFAm3m023945; Thu, 28 Dec 2017 09:10:48 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 28 Dec 2017 09:10:48 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 28 Dec 2017 09:10:48 -0600 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBSFAcfc024443; Thu, 28 Dec 2017 09:10:47 -0600 From: Lokesh Vutla To: Tom Rini , Date: Thu, 28 Dec 2017 20:40:02 +0530 Message-ID: <20171228151003.19500-6-lokeshvutla@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171228151003.19500-1-lokeshvutla@ti.com> References: <20171228151003.19500-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH v3 5/6] board: ti: dra76: mux wakeup2 as gpio1_2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tomi Valkeinen gpio1_2 is used for HPD interrupt with DRA76's DVI add-on board, so mux the pin as gpio and PIN_INPUT. Signed-off-by: Tomi Valkeinen --- board/ti/dra7xx/mux_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 3c3a19a0e1..b5dcaa584a 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -882,7 +882,7 @@ const struct pad_conf_entry dra76x_core_padconf_array[] = { {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */ {WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */ {WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */ - {WAKEUP2, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq2 */ + {WAKEUP2, (M14 | PIN_INPUT)}, /* N/A.gpio1_2 */ {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */ };