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[23.128.96.18]) by mx.google.com with ESMTP id dx26si8766553ejb.593.2020.11.02.02.13.00; Mon, 02 Nov 2020 02:13:00 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fHL7+C0F; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728473AbgKBKMg (ORCPT + 6 others); Mon, 2 Nov 2020 05:12:36 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39250 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728464AbgKBKMf (ORCPT ); Mon, 2 Nov 2020 05:12:35 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ACSPK012582; Mon, 2 Nov 2020 04:12:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604311948; bh=VwsFBA0ieDn50BfS5Y1sE5jJ3zG5NZYGHo75lDjg+oY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fHL7+C0FFMAL66arLR1VmSlyGPh2D6zDil+jDxn+PjqdJ2hmIveAhK9jvHaYr/yfZ tftypxYkXb14pSzB95G0vNfaH56J2ae+5neGj6Y9xURs4KPAOKBcWFXKirnTyRxQXe MzwjFGp3QToFrWNIOmZ6xQJfUpR3LgqxmqJXPGzo= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A2ACRx2067878 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 04:12:27 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 04:12:04 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 04:12:04 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ABtuY059084; Mon, 2 Nov 2020 04:12:01 -0600 From: Kishon Vijay Abraham I To: Lee Jones , Rob Herring , Bjorn Helgaas , Tero Kristo , Nishanth Menon CC: Roger Quadros , , , , Subject: [PATCH 1/8] dt-bindings: mfd: ti, j721e-system-controller.yaml: Document "pcie-ctrl" Date: Mon, 2 Nov 2020 15:41:47 +0530 Message-ID: <20201102101154.13598-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201102101154.13598-1-kishon@ti.com> References: <20201102101154.13598-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding documentation for "pcie-ctrl" which should be a subnode of the system controller. Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/mfd/ti,j721e-system-controller.yaml | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml index 19fcf59fd2fe..fd985794e419 100644 --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml @@ -50,6 +50,12 @@ patternProperties: specified in Documentation/devicetree/bindings/mux/reg-mux.txt + "^pcie-ctrl@[0-9a-f]+$": + type: object + description: | + This is the PCIe controller configuration required to configre PCIe + mode, lane width and speed. + required: - compatible - reg From patchwork Mon Nov 2 10:11:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320188 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp3599192ilc; Mon, 2 Nov 2020 02:12:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJyBq1FjcPdGTzMVT4o2oekuSURmHyZZ0RoyeK08K7FDiQnm+YEsnij+hqMdXlRyZOLMEgIr X-Received: by 2002:a17:906:3ada:: with SMTP id z26mr14312835ejd.151.1604311943962; Mon, 02 Nov 2020 02:12:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604311943; cv=none; d=google.com; s=arc-20160816; b=RFpZWT2krgBWSLpG/NE46iBsukwmtp+RB3e3huJbRnaDH1aNSa8KK43SBrFv0pjJSP 1xI8c9O+URi/EOWFrTb0Zi9Gr289Xxidl0Pv/YIwH4IRD0CvL5oJBog7WI5FKlzzpuYT WmHXal0EfKPYd1orgy94dhi8+AqnpFgyb8aOM64HgEQB3hCUtKVqczGlfGDz7fvI/u48 Iz5qTQ0LkgSo0wI+PRrbgB/phqi9gzlPg+EFlxyoPAXyu/22Yl+DJjwPMx1mWlYb5kII D8te2isxFeYJLIwGaYLo2oLGgmWUVyrIyEYu8hAM9f22ysmLELe0pysn7/5rb/QbJ0ik ksLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=FYw90D37wL2gJHE27Zpjj2Ud8OCfF055vtP6q/qywAw=; b=P5IDPlRlfwZ3g/kVSCfo4tkZaVBIsn2GFWCIAaQj7kXIC45JkZDEchUvGaPQZ0TVuz NI+QO3RubDdfRHmmd/uGUsbr4I3RkMSRpbyANkuhhpSOeLrkWksx8MRRGCsq8m4mlPPg /kDUM3HiboMaosuS+KjCyy3WCvASoFqNX2H8/SqLyMbgk++sGVCMYaK9lrRbqwehSFqs r6jGu1QgU+uZrzKLt+MGMUdlJ6UXup3ls9ziE25CYiQ2MxaYJ0lf0idpraKblC+OVAm3 T56RjeG02QZfxi4Kl2Sh0OAxyKADTRRAd88y/NsQlox91k5K6ZQVhqsVx+vcUcQcDVBK MbfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=thHe3GPo; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- .../bindings/pci/ti,j721e-pci-host.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) -- 2.17.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index ee7a8eade3f6..ecec36c02883 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -15,8 +15,14 @@ allOf: properties: compatible: - enum: - - ti,j721e-pcie-host + oneOf: + - description: PCIe controller in J7200 + items: + - const: ti,j7200-pcie-host + - const: ti,j721e-pcie-host + - description: PCIe controller in J721E + items: + - const: ti,j721e-pcie-host reg: maxItems: 4 @@ -48,7 +54,11 @@ properties: const: 0x104c device-id: - const: 0xb00d + oneOf: + - items: + - const: 0xb00d + - items: + - const: 0xb00f msi-map: true From patchwork Mon Nov 2 10:11:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 314576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FE7DC4742C for ; Mon, 2 Nov 2020 10:13:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE888223BD for ; Mon, 2 Nov 2020 10:12:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="cmrqTADV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728471AbgKBKMf (ORCPT ); Mon, 2 Nov 2020 05:12:35 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:38302 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728467AbgKBKMf (ORCPT ); Mon, 2 Nov 2020 05:12:35 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ACSdC003121; Mon, 2 Nov 2020 04:12:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604311948; bh=4EnqAmwlw82FiJ23Vk3WWXJCCIA3eH6H7JCGMc3LOoc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cmrqTADV+sQ+ClRKqSI+VwUNLlYqd0xOHqXb0SRfyKeXKlcEXfkJ3OzYOtycASgkD 4M4uRvaboxOtyzth++zkqw5Rt+j+fDmG/vTN52/BE0W8cmx9Y31zFfJMGT2KcuzsWb YO6QyHKR8WVSn1Htz9i0jCLo2SdzAc+tzmg2r1fU= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A2ACSJ0067927 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 04:12:28 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 04:12:12 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 04:12:12 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ABtua059084; Mon, 2 Nov 2020 04:12:09 -0600 From: Kishon Vijay Abraham I To: Lee Jones , Rob Herring , Bjorn Helgaas , Tero Kristo , Nishanth Menon CC: Roger Quadros , , , , Subject: [PATCH 3/8] dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC Date: Mon, 2 Nov 2020 15:41:49 +0530 Message-ID: <20201102101154.13598-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201102101154.13598-1-kishon@ti.com> References: <20201102101154.13598-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PCIe EP mode dt-bindings for TI's J7200 SoC. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 3ae3e1a2d4b0..da8c5b892104 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -15,8 +15,14 @@ allOf: properties: compatible: - enum: - - ti,j721e-pcie-ep + oneOf: + - description: PCIe EP controller in J7200 + items: + - const: ti,j7200-pcie-ep + - const: ti,j721e-pcie-ep + - description: PCIe EP controller in J721E + items: + - const: ti,j721e-pcie-ep reg: maxItems: 4 From patchwork Mon Nov 2 10:11:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320192 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp3599616ilc; Mon, 2 Nov 2020 02:12:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJy4mYmte4feHDQYs+DskoG/m1DVA4CLXKZDen4xkE603Ff+/rmm6oRn41Jq5UpJUyFyVcRn X-Received: by 2002:aa7:da44:: with SMTP id w4mr3867946eds.131.1604311978276; Mon, 02 Nov 2020 02:12:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604311978; cv=none; d=google.com; s=arc-20160816; b=GifmnWWNe2N8rTbmnnYQSMWkvlKKRol2hJhWnO9Fg+Vr12DDkXO4ftFmN/GF+ymZFg ee3wd4cSJNom1ZoZCmiD0ZmG6tBCKOcZvaluvhrJLW2+Xnb4ITPpjnQ0fEKOoEPKKjVh KkFatAE8LQD7BpAmcSBA6AgTdXaCLQPc0JLPcPvw2DEkehUUuyQf5Eo9T6cjdQo+aNFr 1Q+uACzwHrQB6YgBh8JqC+33LZRR044eAuICsHt0kficrLES4weGUJ1PajrassRs2+KA QdZAnGzYVPUKo6RsN0Nstl83lBwP3TiUwZq9tIaCLouV9K3ZtLwkY+e2G2TCf9BSWtt5 qMNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=yXkEa7Q+nG4lbV+xXUuIkCvfRCO63DcaQ86Sm5PsyrY=; b=gums9uJ5sh6jjSin7TZXwjraGOuXdn+Jqyj+Cmw9e9jLLjYI8cBhUhwMb95aQX30v8 rTM97teMrbJ60vF6x8dSv9wlzrnjtJ8czAJMTYeyP+M/lzP4FOioQATrvUVZvKGpQr0e 7d3VBAo0JUSY/yCzx9N64u5483Y4CoZg1bJVQYJzMTHS6tr0HWpcXAIxyt3eTlY+qp+g O9i0eYeKk3fdYjs66PzkD0NwLg6h34wEo11cSeva6037gEn52Pnq9j/+tzbjn2/+fBO5 boR9TCDAmTXEo9KpkK1BEKu+0bCd+yJVIuJyZLu6ZWnu6Gv/0KP/H4JWAnQ3OBoYzpdL Rgzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UTUqDBUM; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dx26si8766553ejb.593.2020.11.02.02.12.58; Mon, 02 Nov 2020 02:12:58 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UTUqDBUM; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728491AbgKBKMh (ORCPT + 6 others); Mon, 2 Nov 2020 05:12:37 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:38340 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728479AbgKBKMh (ORCPT ); Mon, 2 Nov 2020 05:12:37 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ACTld003136; Mon, 2 Nov 2020 04:12:29 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604311949; bh=yXkEa7Q+nG4lbV+xXUuIkCvfRCO63DcaQ86Sm5PsyrY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UTUqDBUMKXIO7GL9WZxepuqNIaulWOGSYzs/tHJ68mzOeP2jj7zFNbB+wZrMUkmiH /V4vwCrJtil53sNuPrSAmjUMEtiL+hMP/UPZZrMQJ0Su1fm74AQ0Zur9lArAoA87lv k/ZWJWgswdF6r/vYJnVd3Mb1IhpZ/qSStR1A0JA4= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A2ACTUw068031 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 04:12:29 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 04:12:17 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 04:12:17 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ABtub059084; Mon, 2 Nov 2020 04:12:13 -0600 From: Kishon Vijay Abraham I To: Lee Jones , Rob Herring , Bjorn Helgaas , Tero Kristo , Nishanth Menon CC: Roger Quadros , , , , Subject: [PATCH 4/8] arm64: dts: ti: k3-j7200-main: Add DT for WIZ and SERDES Date: Mon, 2 Nov 2020 15:41:50 +0530 Message-ID: <20201102101154.13598-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201102101154.13598-1-kishon@ti.com> References: <20201102101154.13598-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dt node for the single instance of WIZ and SERDES module shared by PCIe, CPSW (SGMII/QSGMII) and USB. Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 61 +++++++++++++++++++++++ 1 file changed, 61 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 72d6496e88dd..7668404c178b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -417,6 +417,67 @@ dma-coherent; }; + serdes_refclk: serdes_refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + serdes_wiz0: wiz@5060000 { + compatible = "ti,j721e-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks = <&k3_clks 292 85>; + assigned-clock-parents = <&k3_clks 292 89>; + + wiz0_pll0_refclk: pll0-refclk { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_pll0_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll0_refclk>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_pll1_refclk: pll1-refclk { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_pll1_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_refclk_dig: refclk-dig { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_refclk_dig"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { + clocks = <&wiz0_refclk_dig>; + #clock-cells = <0>; + }; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&wiz0_pll0_refclk>; + clock-names = "refclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; From patchwork Mon Nov 2 10:11:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320190 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp3599366ilc; Mon, 2 Nov 2020 02:12:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJw6v0/fQJbFrdJmQbO37HVI3+wQibaiSt30IKN+yvwlnCgDrA5b6yPXo0Bxc6RT+xVvVPN/ X-Received: by 2002:a17:907:b01:: with SMTP id h1mr5132952ejl.10.1604311957126; Mon, 02 Nov 2020 02:12:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604311957; cv=none; d=google.com; s=arc-20160816; b=ccNNnaZToybkXgRRn1VXzgakvrzc9FVfB2zdq0dhvrK+mRGpY0O9CAY93RolKkEBZi YobsJfkR3nKvFOA+oPpFcBidur2OHU21T7HJPW8b4rQ+0RPcMzsLHRfjlvfknZ9TPLMe RV4scywvIOLNHeGBcAAfntro/9zVAVa8CEzuW/QT3uR2sWhCG4bY7ay1RMofqEfotcaz oF85ri9lppyhTEKlhKNmE6f7FCXCMNQ4nsbpWZehCBdqTF65aTgk6MCi61XGaAzUsHP7 rPcQZUuQEQ35TyEve0U6zCuUXUsTTVj6/jlDuSqBRl96SSAmPdCkDXn02WXAfbOIuww4 Wz1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=3Zn/1sH7odFvA8rHuF9tw0urF09pmV/QyOh+uZpfYck=; b=dS/SGctEW5uesEfVDw58xvjNeh9llIyLsw86zzPDFehbREmQ+Nd7oGJtMDO9PMLYfj Q1r22fSiNDc550VCe6zOuLgYZ9sjRMo9nCt/EX0hD6Wx45+84NQvyf35ULki0Y1G7K/o YRhZ0MvQZRu0OtoaLi/y5W7m7w1q0Qj2L9O4GeWi/Y1QeOx4xAwnCIpqtiEGOAruf28t bFdQMw0RA4hR1Cd0Su5keMghqgwUFgGFILIK2To1XLJb6rzQJRvwZKjUubPQnkE+5EQ5 9vSEJ3NTJZwhJF2CRJeWBl22mpipGGIEIqq8JRgJqsY8MwmpK6j0SHGw5kZQcKWhx0hU sf+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="xO/Q2JiM"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k7si10029829ejp.590.2020.11.02.02.12.36; Mon, 02 Nov 2020 02:12:37 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="xO/Q2JiM"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728481AbgKBKMg (ORCPT + 6 others); Mon, 2 Nov 2020 05:12:36 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:38290 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728005AbgKBKMf (ORCPT ); Mon, 2 Nov 2020 05:12:35 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ACOdD003064; Mon, 2 Nov 2020 04:12:24 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604311945; bh=3Zn/1sH7odFvA8rHuF9tw0urF09pmV/QyOh+uZpfYck=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xO/Q2JiMz+kSeMW/AY9zNEBfRB7HXBKfI4XHwThua4dvWEleNSXj+6pgaQy0b0CvJ nPkg1yOgaGW7nXnKoUnj8Wptdb9OHnMsegiKWBjm3nbq1/V/VJcCIKyCJlgJzRdhJe hN+DW5Si/wPEAjmq3OeAba3tDd7ILDFq2Nui0cFM= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A2ACO83074593 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 04:12:24 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 04:12:21 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 04:12:21 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ABtuc059084; Mon, 2 Nov 2020 04:12:17 -0600 From: Kishon Vijay Abraham I To: Lee Jones , Rob Herring , Bjorn Helgaas , Tero Kristo , Nishanth Menon CC: Roger Quadros , , , , Subject: [PATCH 5/8] arm64: dts: ti: k3-j7200-main: Add PCIe device tree node Date: Mon, 2 Nov 2020 15:41:51 +0530 Message-ID: <20201102101154.13598-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201102101154.13598-1-kishon@ti.com> References: <20201102101154.13598-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PCIe device tree node (both RC and EP) for the single PCIe instance present in j7200. Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 7668404c178b..9892704d4b67 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -25,6 +25,14 @@ #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + pcie1_ctrl: pcie-ctrl@4074 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00004074 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x4074 0x4074 0x4>; + }; + serdes_ln_ctrl: serdes-ln-ctrl@4080 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -478,6 +486,56 @@ }; }; + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + cdns,max-outbound-regions = <32>; + cdns,no-bar-match-nbits = <64>; + vendor-id = /bits/ 16 <0x104c>; + device-id = /bits/ 16 <0xb00f>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie1_ctrl>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 240 6>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + dma-coherent; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>; From patchwork Mon Nov 2 10:11:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 314579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01595C388F2 for ; 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Mon, 2 Nov 2020 04:12:25 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 04:12:25 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 04:12:25 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ABtud059084; Mon, 2 Nov 2020 04:12:22 -0600 From: Kishon Vijay Abraham I To: Lee Jones , Rob Herring , Bjorn Helgaas , Tero Kristo , Nishanth Menon CC: Roger Quadros , , , , Subject: [PATCH 6/8] arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0 Date: Mon, 2 Nov 2020 15:41:52 +0530 Message-ID: <20201102101154.13598-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201102101154.13598-1-kishon@ti.com> References: <20201102101154.13598-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe and QSGMII (multi-link SERDES). Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j7200-common-proc-board.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index ef03e7636b66..65a2e5aeb050 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -8,6 +8,7 @@ #include "k3-j7200-som-p0.dtsi" #include #include +#include / { chosen { @@ -213,3 +214,25 @@ dr_mode = "otg"; maximum-speed = "high-speed"; }; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_qsgmii_link: phy@1 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 3>; + }; +}; From patchwork Mon Nov 2 10:11:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 314577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D301C55179 for ; Mon, 2 Nov 2020 10:12:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE776223EA for ; Mon, 2 Nov 2020 10:12:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="G6cFQoqz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728488AbgKBKMh (ORCPT ); Mon, 2 Nov 2020 05:12:37 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39282 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728478AbgKBKMg (ORCPT ); Mon, 2 Nov 2020 05:12:36 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ACU6S012628; Mon, 2 Nov 2020 04:12:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604311950; bh=IpwM0VYjFst7O7GZPtDw/QKWR6xLDCT8pa2h5EbOyBs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=G6cFQoqzyjpVf/XGVk6VzOfg7fO3kMzmPtnhDa/JvQm2Pjw1FZvnjBqlxCtpBMaSn gWEg4lPLrXB8ZrGxr0WtyDlPp/V7CkwZtLCRy4cDtjOorhlaVk2+Q8ZfCqpc272z9t iXTzhiDJJHnG4mpC3gsWb2EfjFl/M7GSR964aKBE= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A2ACU4o045730 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 04:12:30 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 04:12:29 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 04:12:29 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ABtue059084; Mon, 2 Nov 2020 04:12:25 -0600 From: Kishon Vijay Abraham I To: Lee Jones , Rob Herring , Bjorn Helgaas , Tero Kristo , Nishanth Menon CC: Roger Quadros , , , , Subject: [PATCH 7/8] arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe Date: Mon, 2 Nov 2020 15:41:53 +0530 Message-ID: <20201102101154.13598-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201102101154.13598-1-kishon@ti.com> References: <20201102101154.13598-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org x2 lane PCIe slot in the common processor board is enabled and connected to j7200 SOM. Add PCIe DT node in common processor board to reflect the same. Signed-off-by: Kishon Vijay Abraham I --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 65a2e5aeb050..174a55a18522 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include #include #include #include @@ -236,3 +237,17 @@ resets = <&serdes_wiz0 3>; }; }; + +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie1_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + status = "disabled"; +}; From patchwork Mon Nov 2 10:11:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 314578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2A66C00A89 for ; Mon, 2 Nov 2020 10:12:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9CFCE222B9 for ; Mon, 2 Nov 2020 10:12:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VbOqdolu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728527AbgKBKMn (ORCPT ); Mon, 2 Nov 2020 05:12:43 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39320 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728005AbgKBKMk (ORCPT ); Mon, 2 Nov 2020 05:12:40 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ACXbL012681; Mon, 2 Nov 2020 04:12:33 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604311953; bh=y3F0mMpTS94GzADfCO1F6dKsbjUP2ytKdFaTXQxi3lU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VbOqdolufMEpSSScR+//d6t6X+VIx29k2FhYkELFxDLh/Yjr3avq34z3lnFZmJ91L Yxa8NrJK2JZ7TNBMZj02aMOi3YdEtaZY+ImHIxP/RfKg9tziU272itcL9B5HY+8wNj WTSxUF52L73LkAeEzbKfgFJxQ64dP9ShQTC4Xd4k= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A2ACXTL045818 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 04:12:33 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 04:12:33 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 04:12:33 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A2ABtuf059084; Mon, 2 Nov 2020 04:12:29 -0600 From: Kishon Vijay Abraham I To: Lee Jones , Rob Herring , Bjorn Helgaas , Tero Kristo , Nishanth Menon CC: Roger Quadros , , , , Subject: [PATCH 8/8] arm64: dts: ti: k3-j721e-main: Fix PCIe maximum outbound regions Date: Mon, 2 Nov 2020 15:41:54 +0530 Message-ID: <20201102101154.13598-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201102101154.13598-1-kishon@ti.com> References: <20201102101154.13598-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PCIe controller in J721E supports a maximum of 32 outbound regions. commit 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") incorrectly added maximum number of outbound regions to 16. Fix it here. Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes") Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index e2a96b2c423c..61b533130ed1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -652,7 +652,7 @@ power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 239 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; + cdns,max-outbound-regions = <32>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -701,7 +701,7 @@ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 240 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; + cdns,max-outbound-regions = <32>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -750,7 +750,7 @@ power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 241 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; + cdns,max-outbound-regions = <32>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent; @@ -799,7 +799,7 @@ power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 242 1>; clock-names = "fck"; - cdns,max-outbound-regions = <16>; + cdns,max-outbound-regions = <32>; max-functions = /bits/ 8 <6>; max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; dma-coherent;