From patchwork Tue Nov 3 03:55:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320383 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp4260996ilc; Mon, 2 Nov 2020 19:56:19 -0800 (PST) X-Google-Smtp-Source: ABdhPJyLNrMUDx+NVyZKaW3nxZwIhHVGwsr4iIg7VnTGw/n4rARx1Mt0MB+FJpLu2oLHxFIiUZO7 X-Received: by 2002:a17:906:3b89:: with SMTP id u9mr4741188ejf.436.1604375779495; Mon, 02 Nov 2020 19:56:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604375779; cv=none; d=google.com; s=arc-20160816; b=lTttYMSwFSQAnDkXtwZeB1lp9q+Etsnv+obFrTTTvbebATRAKpfMqfVpAD3VbhVJbI kouWTVd/fZfyhfaS5rFxzt2fLgf3KsP4tCL4kKdYH4FnkWaCemjQ1VtiYnlTWXe3QWVk 0Cfc+DNkv9bnbDkIChtoG+hHQxm86zrTyUPOEd2IVpZdNGQIkbRyj11OdI8sKDVAfNbr LHhPJlMfq9rLgHrqnYzz/40KvfL5YD402FwzALK3Zi3H8gIUptEkrM6/jqsxnitJ1V6e JomyJVAjgZbuggUz5tDRQn2DxaxHaXzx3xSWlnMGA+syhgWbLKjQcVq0CbRdAb38EmlK B4Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ejqVodygEsgAslfKzhoklm22eEg4+DvOyLToSf8bIJ0=; b=mhEwmtJqaAq48/1it1iQ/vcA+hyMPPF5mAcwCy7xC4Sk5aeSveBv6g2wxglKl14Eae iTl1OEEYfY4HfQBIm+bXWooXl8fRWs+Rbl6H+QPl1gOfaff+OX58Vkr6EcgmJ07i4N+c hwuZGEepjzUL5BLp7OGeoMlnBt4RtORr5kBlZz45shBr5yrpPzIM5IBdzPFTMuv9xltP o8Sm0gjKbC2GruDUbOSg2/6KZvoCfxQzgkfA/xDPl2oNezT/YwqeQ1zkdEyEExyJAqXU J0Sg8C/qPrKuWCQiLNR7SbWlSx5ElCDSg7cupVY1KpHctoqSgIGlmsdQtElg6nnYuStd Lrbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=H3Qpbcrg; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i21si11296477ejc.179.2020.11.02.19.56.19; Mon, 02 Nov 2020 19:56:19 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=H3Qpbcrg; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725980AbgKCD4S (ORCPT + 6 others); Mon, 2 Nov 2020 22:56:18 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:41818 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725921AbgKCD4S (ORCPT ); Mon, 2 Nov 2020 22:56:18 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A33u9XT034020; Mon, 2 Nov 2020 21:56:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604375769; bh=ejqVodygEsgAslfKzhoklm22eEg4+DvOyLToSf8bIJ0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=H3QpbcrgVREMN93VvKn/wuU5XDuttCNrAzxR032qL3DBACQiMzCYU+xzDpsf5tvQ5 tnARdFHzzw2n1ary31FXd3AakTJyAmvpQhHExQj+HeZgcJ8FOP9RAIyWc22IsbjVob nTigYBVCK89pJJR1EpOwidEmzBy5yJFkRdfZzyt8= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A33u9Uf090537 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 21:56:09 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 21:56:04 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 21:56:04 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A33tuqM101157; Mon, 2 Nov 2020 21:56:01 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel CC: Swapnil Kashinath Jakhade , Milind Parab , Yuti Suresh Amonkar , , Subject: [PATCH 1/9] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES Date: Tue, 3 Nov 2020 09:25:48 +0530 Message-ID: <20201103035556.21260-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201103035556.21260-1-kishon@ti.com> References: <20201103035556.21260-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for the PLLs within SERDES. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/phy-cadence-sierra.yaml | 89 ++++++++++++++++++- 1 file changed, 86 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml index d210843863df..f574b8ed358c 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml @@ -49,12 +49,14 @@ properties: const: serdes clocks: - maxItems: 2 + maxItems: 4 clock-names: items: - const: cmn_refclk_dig_div - const: cmn_refclk1_dig_div + - const: pll_cmnlc + - const: pll_cmnlc1 cdns,autoconf: type: boolean @@ -107,6 +109,58 @@ patternProperties: additionalProperties: false + "^refrcv1?$": + type: object + description: | + Reference receivers that enables routing external clocks to the alternate + PLLCMNLC. + properties: + clocks: + maxItems: 1 + description: Phandle to clock nodes representing the input to the + reference receiver. + + clock-names: + items: + - const: pll_refclk + + "#clock-cells": + const: 0 + + required: + - clocks + - "#clock-cells" + + "^pll_cmnlc1?$": + type: object + description: | + SERDES node should have subnodes for each of the PLLs present in + the SERDES. + properties: + clocks: + maxItems: 2 + description: Phandle to clock nodes representing the two inputs to PLL. + + clock-names: + items: + - const: pll_refclk + - const: refrcv + + "#clock-cells": + const: 0 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + required: + - clocks + - "#clock-cells" + - assigned-clocks + - assigned-clock-parents + required: - compatible - "#address-cells" @@ -130,10 +184,39 @@ examples: reg = <0x0 0xfd240000 0x0 0x40000>; resets = <&phyrst 0>, <&phyrst 1>; reset-names = "sierra_reset", "sierra_apb"; - clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>, <&serdes_pll_cmnlc>, <&serdes_pll_cmnlc1>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1"; #address-cells = <1>; #size-cells = <0>; + + serdes_refrcv: refrcv { + clocks = <&pll0_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes_refrcv1: refrcv1 { + clocks = <&pll1_refclk>; + clock-names = "pll_refclk"; + #clock-cells = <0>; + }; + + serdes_pll_cmnlc: pll_cmnlc { + clocks = <&pll0_refclk>, <&serdes_refrcv1>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes_pll_cmnlc>; + assigned-clock-parents = <&pll0_refclk>; + }; + + serdes_pll_cmnlc1: pll_cmnlc1 { + clocks = <&pll1_refclk>, <&serdes_refrcv>; + clock-names = "pll_refclk", "refrcv"; + #clock-cells = <0>; + assigned-clocks = <&serdes_pll_cmnlc1>; + assigned-clock-parents = <&pll1_refclk>; + }; + pcie0_phy0: phy@0 { reg = <0>; resets = <&phyrst 2>; From patchwork Tue Nov 3 03:55:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 314535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92F21C388F2 for ; Tue, 3 Nov 2020 03:56:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 59A662222B for ; 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Mon, 2 Nov 2020 21:56:18 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 21:56:07 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 21:56:07 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A33tuqN101157; Mon, 2 Nov 2020 21:56:04 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel CC: Swapnil Kashinath Jakhade , Milind Parab , Yuti Suresh Amonkar , , Subject: [PATCH 2/9] phy: ti: j721e-wiz: Get PHY properties only for "phy" subnode Date: Tue, 3 Nov 2020 09:25:49 +0530 Message-ID: <20201103035556.21260-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201103035556.21260-1-kishon@ti.com> References: <20201103035556.21260-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org "serdes" node (child node of WIZ) can have sub-nodes for representing links or it can have sub-nodes for representing the various clocks within the serdes. Instead of trying to read "reg" from every child node used for assigning "lane_phy_type", read only if the child node's name is "phy". Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/phy-j721e-wiz.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index c9cfafe89cbf..d57d29382ce4 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -787,6 +787,9 @@ static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) u32 reg, num_lanes = 1, phy_type = PHY_NONE; int ret, i; + if (!(of_node_name_eq(subnode, "phy"))) + continue; + ret = of_property_read_u32(subnode, "reg", ®); if (ret) { dev_err(dev, From patchwork Tue Nov 3 03:55:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320385 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp4261092ilc; Mon, 2 Nov 2020 19:56:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJzy30SReTCfnlHYb4xKH53d0lHlQa6Tgu6N2FiZcScEnI6x65cq7klTbvCUuvrv0npI8MPF X-Received: by 2002:a17:906:854b:: with SMTP id h11mr9859775ejy.273.1604375789483; Mon, 02 Nov 2020 19:56:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604375789; cv=none; d=google.com; s=arc-20160816; b=SsuPZvIo3/UZ3l9V+a4wzCvpvx3seA12bO+JdBk4wAZYaIAJz17PJPzuueHBwbD05n pr1puMVUsUtxqoHFKkkO0UVcFLABr2/EAgnn8MvPvGpHX6ARMStuBdLakp6cQ7eAzKan N2IkboOaqS8/bRiZdbICVF00K6ISJiN7m7ibLvrXPNCmG2/D3rYbwCVHdCH+iX1MAAyq icssvPuLbNYKbfY1F8C0wU2DL932sDDhbhogJliQmZF9T86Kp/IMp2zkX2Fm+ik8/y9u S2atfsg/IViQZlpYr3D/kVYGUmyvMVLzAbxdBq+M8c1gg1akwp4G4GfGGuBsoeOnzoR4 W4Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ietypxVfSkAgchVIF6msMfozYmCMk6Fw9P27DKZM/7o=; b=lmj1jXSCLKp4NjNW0BXZE+HBybasJXJ2uTByVyWQqmYP+1B6DwBZtZ5e5IlfgEmwgZ P5N2wShd47pUm7nKrJSnwmnBO+Y2bX9RBS5xnhE1hDhaQSEhnV57/kemc7unnEfVcse1 OPb1uqKeKZWFCRy0h8PMpJF4MoArK3g7ituUQJAUYnzE6go0Vwq9R2n5i3FtQ1UNowqL 7DjRgfPDkuBlRtYGpNE0K3AJ886Vh/JNXTQlBmmh3556ulkqL6HyLiaTFVudgCvCYObW xdyIBoIrBI7t7myGWJnMuvoVuKXA4vBRRpKY0zS6k5W2xT1bOY9+HGCwxVuqu1M2S70v NLxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eBplhuu5; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bo5si5757747ejb.102.2020.11.02.19.56.29; Mon, 02 Nov 2020 19:56:29 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eBplhuu5; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727438AbgKCD40 (ORCPT + 6 others); Mon, 2 Nov 2020 22:56:26 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:41834 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727385AbgKCD4Z (ORCPT ); Mon, 2 Nov 2020 22:56:25 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A33uICH034032; Mon, 2 Nov 2020 21:56:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604375778; bh=ietypxVfSkAgchVIF6msMfozYmCMk6Fw9P27DKZM/7o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eBplhuu5EJl0zUFolYW3wW4eAzN8xDGqd5IBXXVR/5EQotYEjcguYAmOtzBkkaF// kruAyFKh22i/OyhizN0cJ0x4IOmfj0MQeQcYt81fYiL1WeSuhibp9HsD7PSrkGLCKt BjzOzkyDlpghulw8w87u7fBiLGaK5nLnksn02fQQ= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A33uI6V031528 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 21:56:18 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 21:56:11 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 21:56:11 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A33tuqO101157; Mon, 2 Nov 2020 21:56:08 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel CC: Swapnil Kashinath Jakhade , Milind Parab , Yuti Suresh Amonkar , , Subject: [PATCH 3/9] phy: ti: j721e-wiz: Don't configure wiz if its already configured Date: Tue, 3 Nov 2020 09:25:50 +0530 Message-ID: <20201103035556.21260-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201103035556.21260-1-kishon@ti.com> References: <20201103035556.21260-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Faiz Abbas Serdes lanes might be shared between multiple cores in some usecases and its not possible to lock PLLs for both the lanes independently by the two cores. This requires a bootloader to configure both the lanes at early boot time. To handle this case, skip all configuration if any of the lanes has already been enabled. While we are here, also fix the wiz_init() to be called before the of_platform_device_create() call. Signed-off-by: Faiz Abbas Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/phy-j721e-wiz.c | 36 +++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 14 deletions(-) -- 2.17.1 diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index d57d29382ce4..9786e8aec252 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -816,13 +816,14 @@ static int wiz_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; struct platform_device *serdes_pdev; + bool already_configured = false; struct device_node *child_node; struct regmap *regmap; struct resource res; void __iomem *base; struct wiz *wiz; u32 num_lanes; - int ret; + int ret, val, i; wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); if (!wiz) @@ -944,10 +945,26 @@ static int wiz_probe(struct platform_device *pdev) goto err_get_sync; } - ret = wiz_clock_init(wiz, node); - if (ret < 0) { - dev_warn(dev, "Failed to initialize clocks\n"); - goto err_get_sync; + for (i = 0; i < wiz->num_lanes; i++) { + regmap_field_read(wiz->p_enable[i], &val); + if (val & (P_ENABLE | P_ENABLE_FORCE)) { + already_configured = true; + break; + } + } + + if (!already_configured) { + ret = wiz_clock_init(wiz, node); + if (ret < 0) { + dev_warn(dev, "Failed to initialize clocks\n"); + goto err_get_sync; + } + + ret = wiz_init(wiz); + if (ret) { + dev_err(dev, "WIZ initialization failed\n"); + goto err_pdev_create; + } } serdes_pdev = of_platform_device_create(child_node, NULL, dev); @@ -958,18 +975,9 @@ static int wiz_probe(struct platform_device *pdev) } wiz->serdes_pdev = serdes_pdev; - ret = wiz_init(wiz); - if (ret) { - dev_err(dev, "WIZ initialization failed\n"); - goto err_wiz_init; - } - of_node_put(child_node); return 0; -err_wiz_init: - of_platform_device_destroy(&serdes_pdev->dev, NULL); - err_pdev_create: wiz_clock_cleanup(wiz, node); From patchwork Tue Nov 3 03:55:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 314536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B4A2C388F2 for ; Tue, 3 Nov 2020 03:56:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D3EC622226 for ; Tue, 3 Nov 2020 03:56:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="BsnbF3G1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727201AbgKCD4X (ORCPT ); Mon, 2 Nov 2020 22:56:23 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:39526 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726938AbgKCD4W (ORCPT ); Mon, 2 Nov 2020 22:56:22 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A33uFx5023685; Mon, 2 Nov 2020 21:56:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604375775; bh=eMj8XstivoruLPX0OnPBgk0XuR0TBVAsG5hVa9Q7tIA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BsnbF3G1zRX1dgqBObs0+in5CdLIkDvhAxc5VKnOAnXuoQpxgUuC8ttTZdZYWwhxz 51f4H5CMcM77NNrQhzZAE0fl/v0pcVN43BExw3BVx2uyzW6h+jj6czA/0CmOPavEoy oMUE1t/IMrRDy3xvVeCeQuPzngsVpvJOIKXKEsig= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A33uFLM126296 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 21:56:15 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 21:56:15 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 21:56:15 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A33tuqP101157; Mon, 2 Nov 2020 21:56:12 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel CC: Swapnil Kashinath Jakhade , Milind Parab , Yuti Suresh Amonkar , , Subject: [PATCH 4/9] phy: cadence: cadence-sierra: Create PHY only for "phy" sub-nodes Date: Tue, 3 Nov 2020 09:25:51 +0530 Message-ID: <20201103035556.21260-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201103035556.21260-1-kishon@ti.com> References: <20201103035556.21260-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" which represent the actual PHY. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 453ef26fa1c7..4429f41a8f58 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -573,6 +573,9 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) for_each_available_child_of_node(dn, child) { struct phy *gphy; + if (!(of_node_name_eq(child, "phy"))) + continue; + sp->phys[node].lnk_rst = of_reset_control_array_get_exclusive(child); From patchwork Tue Nov 3 03:55:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320391 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp4261300ilc; Mon, 2 Nov 2020 19:56:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJxubraAlegGQ0VzTrwUz2qnyYEbcsdZnm1xIifm5nqjDDycZYfF3RVlpLFK6hyKY3q62pCu X-Received: by 2002:a05:6402:4d:: with SMTP id f13mr19905192edu.306.1604375814494; Mon, 02 Nov 2020 19:56:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604375814; cv=none; d=google.com; s=arc-20160816; b=z9fxud4O9QOabnDo2AScuqjqPNCtyGqIPuNFBLGePaPRfId4xE4wnTbwvt8TsOBf5e C6uZwo1//7DhAhnHrFgP/uBrxVyVqdffe+n7+ZoqVoBpxSIfm0Vv8pbGlIXKtdc2RhKt qpAeZfaTHD9KhXW3A4BXeZmH5BsB54ya+9FO6QGciTZetRF9UY2qm81IdBG538pKDtqw qScQnsGsi83moWB2fGoXY+nmao15yDwjcNMihIYYOw/hztS6BPNdy8u1oHgh640G6N7m swlOvdBZNe+C8cxrrdT0g0V/p6UitcnKn3VAG0EZ7YqPi2U22N1KwYpODAUbv1DnAUcY pAvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=hZea0eYsVNvA04vqZbladeZtJPWX5S3T1/tgGYMH90w=; b=kjKJ3dhKlWuq/k6D8HoX4inxIb+Jd+Jym32MWQPbNhOQf5MaxlSiCVRkffkP/jQhkM aMLTn41d0k4R5eGTKhv2M1YQEj/vqbfMS8cw1Nw3dKkKk1R7uhMz5ITo6bFrcXsKhQ3d byd1AKd05GVi2fpIrJaUO4oFC+uhkb/c0PqNqCdtE3dxB2NKdr+gnWUYfXqFoHCIuJN0 IiZWleiFofZC0oBfLqFh4SMYe1EPatYYGCql0JBEJq3uhs6oAxu3OHOhCXB2A7IwxzTy AaMf3bdqYevwuBTiCmyVRfpKIoKwsz7zQCgOP3Gndru/8e4qUwyMlmZleC8F+DzGuvPv 9vWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FObGxQAB; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a13si7044536edm.538.2020.11.02.19.56.54; Mon, 02 Nov 2020 19:56:54 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FObGxQAB; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727525AbgKCD4n (ORCPT + 6 others); Mon, 2 Nov 2020 22:56:43 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:41936 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727524AbgKCD4h (ORCPT ); Mon, 2 Nov 2020 22:56:37 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A33uVKo034219; Mon, 2 Nov 2020 21:56:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604375791; bh=hZea0eYsVNvA04vqZbladeZtJPWX5S3T1/tgGYMH90w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FObGxQAB0JTtsgi1LopWVW5t6V+naJ6Y5+uakrUI0wlbaps3dl1xV8qVpbBt3AOdP 0Yl5XVLbOc+lGlxhyJgMiiU40CuA52HRCtfFQ3M0dqIG8HZeJ+SpgLC3bs+mgG4o4S pJH6bozlvDbIxJbKxhRjWzFi4WPSVbR45hx+YuGs= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A33uVrE112400 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 21:56:31 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 21:56:19 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 21:56:19 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A33tuqQ101157; Mon, 2 Nov 2020 21:56:15 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel CC: Swapnil Kashinath Jakhade , Milind Parab , Yuti Suresh Amonkar , , Subject: [PATCH 5/9] phy: cadence: Sierra: Fix PHY power_on sequence Date: Tue, 3 Nov 2020 09:25:52 +0530 Message-ID: <20201103035556.21260-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201103035556.21260-1-kishon@ti.com> References: <20201103035556.21260-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 4429f41a8f58..e08548417bce 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -319,6 +319,12 @@ static int cdns_sierra_phy_on(struct phy *gphy) u32 val; int ret; + ret = reset_control_deassert(sp->phy_rst); + if (ret) { + dev_err(dev, "Failed to take the PHY out of reset\n"); + return ret; + } + /* Take the PHY lane group out of reset */ ret = reset_control_deassert(ins->lnk_rst); if (ret) { @@ -621,7 +627,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) pm_runtime_enable(dev); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - reset_control_deassert(sp->phy_rst); return PTR_ERR_OR_ZERO(phy_provider); put_child: From patchwork Tue Nov 3 03:55:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 314534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50F87C388F2 for ; Tue, 3 Nov 2020 03:56:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0F314206D8 for ; Tue, 3 Nov 2020 03:56:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="dkGR4Dwo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727418AbgKCD4g (ORCPT ); Mon, 2 Nov 2020 22:56:36 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:41912 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727476AbgKCD4f (ORCPT ); Mon, 2 Nov 2020 22:56:35 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A33uU2c034185; Mon, 2 Nov 2020 21:56:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604375790; bh=HStXkv9wFRR3rD6VCpH4H1fcX4qHUGOEUyg7wkRYohU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dkGR4DwoJwf2vhy19+tDW+hDcWCpsqRrPYHSeeJsbmV+WpeyFZjuiCedmKCPTMXgU 1jnV3kKmBJgtchGT2OqLnilECM7zMn3N9zJfP5itMm/DnQmxPqabLl32OeZkbGbyKm mzUUvH8cXJuc2z6WjxPMEAUfcv8lAcAtT4QzZ/1E= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A33uTmb126643 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 21:56:30 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 21:56:23 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 21:56:23 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A33tuqR101157; Mon, 2 Nov 2020 21:56:20 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel CC: Swapnil Kashinath Jakhade , Milind Parab , Yuti Suresh Amonkar , , Subject: [PATCH 6/9] phy: cadence: sierra: Don't configure if any plls are already locked Date: Tue, 3 Nov 2020 09:25:53 +0530 Message-ID: <20201103035556.21260-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201103035556.21260-1-kishon@ti.com> References: <20201103035556.21260-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Faiz Abbas Serdes lanes might be shared between multiple cores in some usecases and its not possible to lock PLLs for both the lanes independently by the two cores. This requires a bootloader to configure both the lanes at early boot time. To handle this case, skip all configuration if any of the plls are already locked. This is done by adding an already_configured flag and using it to gate every register access as well as any phy_ops. Signed-off-by: Faiz Abbas Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 127 ++++++++++++++--------- 1 file changed, 78 insertions(+), 49 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index e08548417bce..145e42837b7b 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -364,6 +364,10 @@ static const struct phy_ops ops = { .owner = THIS_MODULE, }; +static const struct phy_ops noop_ops = { + .owner = THIS_MODULE, +}; + static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, struct device_node *child) { @@ -477,6 +481,49 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, + struct device *dev) +{ + struct clk *clk; + int ret; + + sp->clk = devm_clk_get_optional(dev, "phy_clk"); + if (IS_ERR(sp->clk)) { + dev_err(dev, "failed to get clock phy_clk\n"); + return PTR_ERR(sp->clk); + } + + sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); + if (IS_ERR(sp->phy_rst)) { + dev_err(dev, "failed to get reset\n"); + return PTR_ERR(sp->phy_rst); + } + + sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); + if (IS_ERR(sp->apb_rst)) { + dev_err(dev, "failed to get apb reset\n"); + return PTR_ERR(sp->apb_rst); + } + + clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk_dig_div = clk; + + clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); + if (IS_ERR(clk)) { + dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->cmn_refclk1_dig_div = clk; + + return 0; +} + static int cdns_sierra_phy_probe(struct platform_device *pdev) { struct cdns_sierra_phy *sp; @@ -486,10 +533,10 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) struct cdns_sierra_data *data; unsigned int id_value; struct resource *res; - int i, ret, node = 0; + int i, val, ret, node = 0; void __iomem *base; - struct clk *clk; struct device_node *dn = dev->of_node, *child; + bool already_configured = false; if (of_get_child_count(dn) == 0) return -ENODEV; @@ -524,54 +571,33 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) return ret; - platform_set_drvdata(pdev, sp); - - sp->clk = devm_clk_get_optional(dev, "phy_clk"); - if (IS_ERR(sp->clk)) { - dev_err(dev, "failed to get clock phy_clk\n"); - return PTR_ERR(sp->clk); - } - - sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); - if (IS_ERR(sp->phy_rst)) { - dev_err(dev, "failed to get reset\n"); - return PTR_ERR(sp->phy_rst); - } - - sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); - if (IS_ERR(sp->apb_rst)) { - dev_err(dev, "failed to get apb reset\n"); - return PTR_ERR(sp->apb_rst); - } - - clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); - if (IS_ERR(clk)) { - dev_err(dev, "cmn_refclk_dig_div clock not found\n"); - ret = PTR_ERR(clk); - return ret; - } - sp->cmn_refclk_dig_div = clk; - - clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); - if (IS_ERR(clk)) { - dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); - ret = PTR_ERR(clk); - return ret; + for (i = 0; i < SIERRA_MAX_LANES; i++) { + regmap_field_read(sp->pllctrl_lock[i], &val); + if (val) { + already_configured = true; + break; + } } - sp->cmn_refclk1_dig_div = clk; - ret = clk_prepare_enable(sp->clk); - if (ret) - return ret; - - /* Enable APB */ - reset_control_deassert(sp->apb_rst); + platform_set_drvdata(pdev, sp); - /* Check that PHY is present */ - regmap_field_read(sp->macro_id_type, &id_value); - if (sp->init_data->id_value != id_value) { - ret = -EINVAL; - goto clk_disable; + if (!already_configured) { + ret = cdns_sierra_phy_get_clocks(sp, dev); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->clk); + if (ret) + return ret; + /* Enable APB */ + reset_control_deassert(sp->apb_rst); + + /* Check that PHY is present */ + regmap_field_read(sp->macro_id_type, &id_value); + if (sp->init_data->id_value != id_value) { + ret = -EINVAL; + goto clk_disable; + } } sp->autoconf = of_property_read_bool(dn, "cdns,autoconf"); @@ -603,7 +629,10 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) sp->num_lanes += sp->phys[node].num_lanes; - gphy = devm_phy_create(dev, child, &ops); + if (already_configured) + gphy = devm_phy_create(dev, child, &noop_ops); + else + gphy = devm_phy_create(dev, child, &ops); if (IS_ERR(gphy)) { ret = PTR_ERR(gphy); @@ -622,7 +651,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) } /* If more than one subnode, configure the PHY as multilink */ - if (!sp->autoconf && sp->nsubnodes > 1) + if (!sp->autoconf && sp->nsubnodes > 1 && !already_configured) regmap_field_write(sp->phy_pll_cfg_1, 0x1); pm_runtime_enable(dev); From patchwork Tue Nov 3 03:55:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320387 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp4261146ilc; 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[23.128.96.18]) by mx.google.com with ESMTP id bo5si5757747ejb.102.2020.11.02.19.56.34; Mon, 02 Nov 2020 19:56:34 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tmG8jJwP; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727457AbgKCD4d (ORCPT + 6 others); Mon, 2 Nov 2020 22:56:33 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:39586 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727424AbgKCD4d (ORCPT ); Mon, 2 Nov 2020 22:56:33 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A33uR5b023738; Mon, 2 Nov 2020 21:56:27 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604375787; bh=Eyd66bu/B8nY3Xw74Q3lf9TGmxbpqwZIEnWaSeJlbKk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tmG8jJwPgW0x0UpJdg/2giJSj1fhFT6Sb8+xW05+yZ2/sD0n5e7RjpR5zANvjTN4K cbbWCKKmUOrbDHVvhTBcEToFAeTNCBnL6Hhq09xtEGW2F4gsxCaI6XoQ9jT7vtuzWd OALLXvlhvDQVIVv1xmBSkJzvW+26U5p+PCwHM8XY= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A33uRtb031691 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 21:56:27 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 21:56:27 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 21:56:27 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A33tuqS101157; Mon, 2 Nov 2020 21:56:24 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel CC: Swapnil Kashinath Jakhade , Milind Parab , Yuti Suresh Amonkar , , Subject: [PATCH 7/9] phy: cadence: sierra: Model reference receiver as clocks (gate clocks) Date: Tue, 3 Nov 2020 09:25:54 +0530 Message-ID: <20201103035556.21260-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201103035556.21260-1-kishon@ti.com> References: <20201103035556.21260-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Sierra has two reference recievers REFRCV and REFRCV1. REFRCV is used to drive reference clock cmn_refclk_m/p to PLL_CMNLC1 and REFRCV1 is used to drive reference clock cmn_refclk1_m/p to PLL_CMNLC. Model these reference receivers as clocks in order for PLL_CMNLC and PLL_CMNLC1 to be able to seamlessly use any of the external reference clocks. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 177 +++++++++++++++++++++++ 1 file changed, 177 insertions(+) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 145e42837b7b..ab7a3e2795cd 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -7,6 +7,7 @@ * */ #include +#include #include #include #include @@ -31,6 +32,8 @@ #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 +#define SIERRA_CMN_REFRCV_PREG 0x98 +#define SIERRA_CMN_REFRCV1_PREG 0xB8 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ ((0x4000 << (block_offset)) + \ @@ -151,6 +154,35 @@ static const struct reg_field phy_pll_cfg_1 = static const struct reg_field pllctrl_lock = REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); +enum cdns_sierra_cmn_refrcv { + CMN_REFRCV, + CMN_REFRCV1, +}; + +#define SIERRA_NUM_REFRCV 0x2 + +static const struct reg_field cmn_refrcv_refclk_plllc1en_preg[] = { + [CMN_REFRCV] = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8), + [CMN_REFRCV1] = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8), +}; + +static const struct reg_field cmn_refrcv_refclk_termen_preg[] = { + [CMN_REFRCV] = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), + [CMN_REFRCV1] = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0), +}; + +static char *refrcv_node_name[] = { "refrcv", "refrcv1" }; + +struct cdns_sierra_refrcv { + struct clk_hw hw; + struct regmap_field *plllc1en_field; + struct regmap_field *termen_field; + struct clk_init_data clk_data; +}; + +#define to_cdns_sierra_refrcv(_hw) \ + container_of(_hw, struct cdns_sierra_refrcv, hw) + struct cdns_sierra_inst { struct phy *phy; u32 phy_type; @@ -197,6 +229,8 @@ struct cdns_sierra_phy { struct regmap_field *macro_id_type; struct regmap_field *phy_pll_cfg_1; struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; + struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_REFRCV]; + struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_REFRCV]; struct clk *clk; struct clk *cmn_refclk_dig_div; struct clk *cmn_refclk1_dig_div; @@ -368,6 +402,93 @@ static const struct phy_ops noop_ops = { .owner = THIS_MODULE, }; +static int cdns_sierra_refrcv_enable(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + struct regmap_field *termen_field = refrcv->termen_field; + + regmap_field_write(plllc1en_field, 1); + regmap_field_write(termen_field, 1); + + return 0; +} + +static void cdns_sierra_refrcv_disable(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + struct regmap_field *termen_field = refrcv->termen_field; + + regmap_field_write(plllc1en_field, 0); + regmap_field_write(termen_field, 0); +} + +static int cdns_sierra_refrcv_is_enabled(struct clk_hw *hw) +{ + struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); + struct regmap_field *plllc1en_field = refrcv->plllc1en_field; + int val; + + regmap_field_read(plllc1en_field, &val); + + return !!val; +} + +static const struct clk_ops cdns_sierra_refrcv_ops = { + .enable = cdns_sierra_refrcv_enable, + .disable = cdns_sierra_refrcv_disable, + .is_enabled = cdns_sierra_refrcv_is_enabled, +}; + +static int cdns_sierra_refrcv_register(struct cdns_sierra_phy *sp, + struct device_node *node, + struct regmap_field *plllc1en_field, + struct regmap_field *termen_field) +{ + struct cdns_sierra_refrcv *refrcv; + struct device *dev = sp->dev; + struct clk_init_data *init; + unsigned int num_parents; + const char *parent_name; + char clk_name[100]; + struct clk *clk; + int ret; + + refrcv = devm_kzalloc(dev, sizeof(*refrcv), GFP_KERNEL); + if (!refrcv) + return -ENOMEM; + + num_parents = of_clk_get_parent_count(node); + parent_name = of_clk_get_parent_name(node, 0); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &refrcv->clk_data; + + init->ops = &cdns_sierra_refrcv_ops; + init->flags = 0; + init->parent_names = parent_name ? &parent_name : NULL; + init->num_parents = num_parents ? 1 : 0; + init->name = clk_name; + + refrcv->plllc1en_field = plllc1en_field; + refrcv->termen_field = termen_field; + refrcv->hw.init = init; + + clk = devm_clk_register(dev, &refrcv->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Failed to add refrcv clock provider: %s\n", + clk_name); + + return ret; +} + static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, struct device_node *child) { @@ -406,6 +527,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) { struct device *dev = sp->dev; struct regmap_field *field; + struct reg_field reg_field; struct regmap *regmap; int i; @@ -417,6 +539,24 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) } sp->macro_id_type = field; + for (i = 0; i < SIERRA_NUM_REFRCV; i++) { + reg_field = cmn_refrcv_refclk_plllc1en_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i); + return PTR_ERR(field); + } + sp->cmn_refrcv_refclk_plllc1en_preg[i] = field; + + reg_field = cmn_refrcv_refclk_termen_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i); + return PTR_ERR(field); + } + sp->cmn_refrcv_refclk_termen_preg[i] = field; + } + regmap = sp->regmap_phy_config_ctrl; field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); if (IS_ERR(field)) { @@ -481,6 +621,38 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, return 0; } +static int cdns_sierra_phy_register_refrcv(struct cdns_sierra_phy *sp, + struct device_node *dn) +{ + struct regmap_field *plllc1en_field; + struct device_node *of_node = NULL; + struct regmap_field *termen_field; + struct device *dev = sp->dev; + int ret = 0, i; + + for (i = 0; i < SIERRA_NUM_REFRCV; i++) { + of_node = of_get_child_by_name(dn, refrcv_node_name[i]); + if (!of_node) + return 0; + + plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i]; + termen_field = sp->cmn_refrcv_refclk_termen_preg[i]; + + ret = cdns_sierra_refrcv_register(sp, of_node, plllc1en_field, + termen_field); + if (ret) { + dev_err(dev, "Fail to register reference receiver %s\n", + refrcv_node_name[i]); + goto err; + } + } + +err: + of_node_put(of_node); + + return ret; +} + static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, struct device *dev) { @@ -582,6 +754,10 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); if (!already_configured) { + ret = cdns_sierra_phy_register_refrcv(sp, dn); + if (ret) + return ret; + ret = cdns_sierra_phy_get_clocks(sp, dev); if (ret) return ret; @@ -589,6 +765,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) ret = clk_prepare_enable(sp->clk); if (ret) return ret; + /* Enable APB */ reset_control_deassert(sp->apb_rst); From patchwork Tue Nov 3 03:55:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 320389 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp4261178ilc; Mon, 2 Nov 2020 19:56:38 -0800 (PST) X-Google-Smtp-Source: ABdhPJzi8WTfZ1H8VhpaQ4ppp8h/3n4mhYjex6tPN8kX1LVCS5x6RSQzu79VZAQ4SA7QMq/TQzUn X-Received: by 2002:a17:906:c0ce:: with SMTP id bn14mr9411520ejb.105.1604375798796; Mon, 02 Nov 2020 19:56:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604375798; cv=none; d=google.com; s=arc-20160816; b=c3Ta6EDYANwLvBvh3dDMJOG2DETlgQvxLBfF3WKk8inAgKA80L2LaXsXFNXLtRN+Cs 1i5874rKqXEh2Jq5TiY+rsvGrvnoDyluN9ZXCzTDvL0itE58ver/aKDnp/297dcJHXjs nBixN+xREhFGz8yK7jJ6wP419kSRQwDyadEKRvGyXDqjQuiZz3JlzQaalx0dME4ZrTzf cBIXCbwS4qjXhUlc/2kRFj1JYI4u1GlhmLLfem4Q51aKNMzsTt5OpegY4y/MejL/HzNu H9haRBFgK+gZqb3wipCAuafFeeSuwuv4yqhx4xTLmaU5C7OzFWi/G85/paxKU36FcBxt 6SHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=RIVx4Nuxu5qZjDapNR/qyXoVvAzyEQ5UPTMKLfWMEWY=; b=y383HomK2uW4GW9g9QaHMyjec08PDKxvct/EgZ/srPnvF++wfNu2dCgsN365E4xttB KL0O0GXPIbLl3vccWfFQhmCIBTOV1UD7Zv9qAkGQvMtLLq1Wb85h/JTwt8FnO+FHZhSF TzbLlWmgymUmd+JiDy6DorUn81szYmrnh9YGPWsuLww8FOg4U8KEHozNJlNLF2kW1xVs QNw5THvA7NUR8Yw8vVf1s0SxfH47gdzreXgBOujFXJNVc0AjUzqhlNiRAY7OK8n1dZkf vELWcPaYNNsCg9L5G4aiFZnu0qxnwz2bFUh/1Kk5XEiGGIURCytDV40Rz+FNQy6Vnwvr 5uYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DRuWjLQT; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bo5si5757747ejb.102.2020.11.02.19.56.38; Mon, 02 Nov 2020 19:56:38 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DRuWjLQT; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727463AbgKCD4g (ORCPT + 6 others); Mon, 2 Nov 2020 22:56:36 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:41920 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727511AbgKCD4g (ORCPT ); Mon, 2 Nov 2020 22:56:36 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0A33uVAX034215; Mon, 2 Nov 2020 21:56:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1604375791; bh=RIVx4Nuxu5qZjDapNR/qyXoVvAzyEQ5UPTMKLfWMEWY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DRuWjLQTMnEbxEHEdLT7eSWsauKfVpK2R0KwXD8Tx4iPg4x3Trwg9nuF52mT8QXSO N2E/CPPbAemyYyL2c67ydfZWJ89PJir9nXWN5wo6W+PLHDWaguDG6HzfB3VtepeC0P rZbVtjpRYbr713W7VhN9Cuyn0TBVihuqOAbEIMPg= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0A33uVTk112377 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Nov 2020 21:56:31 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 21:56:30 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 21:56:30 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A33tuqT101157; Mon, 2 Nov 2020 21:56:28 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel CC: Swapnil Kashinath Jakhade , Milind Parab , Yuti Suresh Amonkar , , Subject: [PATCH 8/9] phy: cadence: sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Date: Tue, 3 Nov 2020 09:25:55 +0530 Message-ID: <20201103035556.21260-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201103035556.21260-1-kishon@ti.com> References: <20201103035556.21260-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk and refrcv. Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's possible to select one of these two inputs from device tree. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 158 +++++++++++++++++++++++ 1 file changed, 158 insertions(+) -- 2.17.1 diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index ab7a3e2795cd..c4751fe9edfd 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -25,6 +25,7 @@ /* PHY register offsets */ #define SIERRA_COMMON_CDB_OFFSET 0x0 #define SIERRA_MACRO_ID_REG 0x0 +#define SIERRA_CMN_PLLLC_GEN_PREG 0x42 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A @@ -34,6 +35,7 @@ #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 #define SIERRA_CMN_REFRCV_PREG 0x98 #define SIERRA_CMN_REFRCV1_PREG 0xB8 +#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ ((0x4000 << (block_offset)) + \ @@ -183,6 +185,36 @@ struct cdns_sierra_refrcv { #define to_cdns_sierra_refrcv(_hw) \ container_of(_hw, struct cdns_sierra_refrcv, hw) +enum cdns_sierra_cmn_plllc { + CMN_PLLLC, + CMN_PLLLC1, +}; + +#define SIERRA_NUM_CMN_PLLC 0x2 + +static const struct reg_field cmn_plllc_pfdclk1_sel_preg[] = { + [CMN_PLLLC] = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), + [CMN_PLLLC1] = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), +}; + +static char *cmn_plllc_node_name[] = { "pll_cmnlc", "pll_cmnlc1" }; + +struct cdns_sierra_pll_mux { + struct clk_hw hw; + struct regmap_field *pfdclk_sel_preg; + u32 *table; + struct clk_init_data clk_data; +}; + +#define to_cdns_sierra_pll_mux(_hw) \ + container_of(_hw, struct cdns_sierra_pll_mux, hw) + +/* + * Mux value to be configured for each of the input clocks + * in the order populated in device tree + */ +static u32 cdns_sierra_pll_mux_table[] = { 0, 1 }; + struct cdns_sierra_inst { struct phy *phy; u32 phy_type; @@ -231,6 +263,7 @@ struct cdns_sierra_phy { struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_REFRCV]; struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_REFRCV]; + struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; struct clk *clk; struct clk *cmn_refclk_dig_div; struct clk *cmn_refclk1_dig_div; @@ -402,6 +435,117 @@ static const struct phy_ops noop_ops = { .owner = THIS_MODULE, }; +static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) +{ + struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); + struct regmap_field *field = mux->pfdclk_sel_preg; + unsigned int val; + + regmap_field_read(field, &val); + return clk_mux_val_to_index(hw, mux->table, 0, val); +} + +static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); + struct regmap_field *field = mux->pfdclk_sel_preg; + int val; + + val = mux->table[index]; + return regmap_field_write(field, val); +} + +static const struct clk_ops cdns_sierra_pll_mux_ops = { + .set_parent = cdns_sierra_pll_mux_set_parent, + .get_parent = cdns_sierra_pll_mux_get_parent, +}; + +static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, + struct device_node *node, + struct regmap_field *field) +{ + struct cdns_sierra_pll_mux *mux; + struct device *dev = sp->dev; + struct clk_init_data *init; + const char **parent_names; + unsigned int num_parents; + char clk_name[100]; + struct clk *clk; + int ret; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + dev_err(dev, "SERDES clock must have parents\n"); + return -EINVAL; + } + + parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), + GFP_KERNEL); + if (!parent_names) + return -ENOMEM; + + of_clk_parent_fill(node, parent_names, num_parents); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &mux->clk_data; + + init->ops = &cdns_sierra_pll_mux_ops; + init->flags = CLK_SET_RATE_NO_REPARENT; + init->parent_names = parent_names; + init->num_parents = num_parents; + init->name = clk_name; + + mux->pfdclk_sel_preg = field; + mux->table = cdns_sierra_pll_mux_table; + mux->hw.init = init; + + clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "Fail to add pll mux clock provider: %s\n", + clk_name); + + return ret; +} + +static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp, + struct device_node *dn) +{ + struct regmap_field *pfdclk1_sel_field; + struct device_node *of_node = NULL; + struct device *dev = sp->dev; + int ret = 0, i; + + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + of_node = of_get_child_by_name(dn, cmn_plllc_node_name[i]); + if (!of_node) + return 0; + + pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i]; + ret = cdns_sierra_pll_mux_register(sp, of_node, + pfdclk1_sel_field); + if (ret) { + dev_err(dev, "Fail to register cmn plllc mux %s\n", + cmn_plllc_node_name[i]); + goto err; + } + } + +err: + of_node_put(of_node); + + return 0; +} + static int cdns_sierra_refrcv_enable(struct clk_hw *hw) { struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw); @@ -557,6 +701,16 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp) sp->cmn_refrcv_refclk_termen_preg[i] = field; } + for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { + reg_field = cmn_plllc_pfdclk1_sel_preg[i]; + field = devm_regmap_field_alloc(dev, regmap, reg_field); + if (IS_ERR(field)) { + dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i); + return PTR_ERR(field); + } + sp->cmn_plllc_pfdclk1_sel_preg[i] = field; + } + regmap = sp->regmap_phy_config_ctrl; field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); if (IS_ERR(field)) { @@ -758,6 +912,10 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) return ret; + ret = cdns_sierra_phy_register_pll_mux(sp, dn); + if (ret) + return ret; + ret = cdns_sierra_phy_get_clocks(sp, dev); if (ret) return ret; From patchwork Tue Nov 3 03:55:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 314533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71F5BC388F2 for ; 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Mon, 2 Nov 2020 21:56:34 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 2 Nov 2020 21:56:34 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 2 Nov 2020 21:56:34 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0A33tuqU101157; Mon, 2 Nov 2020 21:56:31 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel CC: Swapnil Kashinath Jakhade , Milind Parab , Yuti Suresh Amonkar , , Subject: [PATCH 9/9] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Date: Tue, 3 Nov 2020 09:25:56 +0530 Message-ID: <20201103035556.21260-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201103035556.21260-1-kishon@ti.com> References: <20201103035556.21260-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/cadence/phy-cadence-sierra.c | 39 +++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index c4751fe9edfd..94fd9ce4223e 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -267,6 +267,8 @@ struct cdns_sierra_phy { struct clk *clk; struct clk *cmn_refclk_dig_div; struct clk *cmn_refclk1_dig_div; + struct clk *pll_cmnlc; + struct clk *pll_cmnlc1; int nsubnodes; u32 num_lanes; bool autoconf; @@ -847,6 +849,41 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, } sp->cmn_refclk1_dig_div = clk; + clk = devm_clk_get_optional(dev, "pll_cmnlc"); + if (IS_ERR(clk)) { + dev_err(dev, "pll_cmnlc clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->pll_cmnlc = clk; + + clk = devm_clk_get_optional(dev, "pll_cmnlc1"); + if (IS_ERR(clk)) { + dev_err(dev, "pll_cmnlc1 clock not found\n"); + ret = PTR_ERR(clk); + return ret; + } + sp->pll_cmnlc1 = clk; + + return 0; +} + +static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) +{ + int ret; + + ret = clk_prepare_enable(sp->clk); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->pll_cmnlc); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->pll_cmnlc1); + if (ret) + return ret; + return 0; } @@ -920,7 +957,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) if (ret) return ret; - ret = clk_prepare_enable(sp->clk); + ret = cdns_sierra_phy_enable_clocks(sp); if (ret) return ret;