From patchwork Tue Nov 3 07:56:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 314523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA141C2D0A3 for ; Tue, 3 Nov 2020 07:57:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9DF212222B for ; Tue, 3 Nov 2020 07:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727916AbgKCH5G (ORCPT ); Tue, 3 Nov 2020 02:57:06 -0500 Received: from mga09.intel.com ([134.134.136.24]:62969 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725958AbgKCH5G (ORCPT ); Tue, 3 Nov 2020 02:57:06 -0500 IronPort-SDR: FcM4pCPR4t0h7ISKMW6GtYNoKtsLNFiQjAMhd8xxuX4A+76FxweMCcpIhfWBAXDWMeISltqiH7 BAPOgfsOPOiw== X-IronPort-AV: E=McAfee;i="6000,8403,9793"; a="169146143" X-IronPort-AV: E=Sophos;i="5.77,447,1596524400"; d="scan'208";a="169146143" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2020 23:57:05 -0800 IronPort-SDR: Jmo+KgRJo++aNC/jdXmYJFDVuLRkaC5V3g+Lpr6UtJhmCjB72jTYmI3JAxk1gwbQjQA57//+1B wlMp/nu4tpbA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,447,1596524400"; d="scan'208";a="426232833" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by fmsmga001.fm.intel.com with ESMTP; 02 Nov 2020 23:57:02 -0800 From: "Ramuthevar,Vadivel MuruganX" To: miquel.raynal@bootlin.com, vigneshr@ti.com, tudor.ambarus@microchip.com, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org, richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v16 1/2] dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC Date: Tue, 3 Nov 2020 15:56:54 +0800 Message-Id: <20201103075655.18699-2-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20201103075655.18699-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201103075655.18699-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ramuthevar Vadivel Murugan Add YAML file for dt-bindings to support NAND Flash Controller on Intel's Lightning Mountain SoC. Signed-off-by: Ramuthevar Vadivel Murugan Reviewed-by: Rob Herring --- .../devicetree/bindings/mtd/intel,lgm-nand.yaml | 99 ++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml new file mode 100644 index 000000000000..313daec4d783 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel LGM SoC NAND Controller Device Tree Bindings + +allOf: + - $ref: "nand-controller.yaml" + +maintainers: + - Ramuthevar Vadivel Murugan + +properties: + compatible: + const: intel,lgm-nand + + reg: + maxItems: 6 + + reg-names: + items: + - const: ebunand + - const: hsnand + - const: nand_cs0 + - const: nand_cs1 + - const: addr_sel0 + - const: addr_sel1 + + clocks: + maxItems: 1 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^nand@[a-f0-9]+$": + type: object + properties: + reg: + minimum: 0 + maximum: 7 + + nand-ecc-mode: true + + nand-ecc-algo: + const: hw + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - clocks + - dmas + - dma-names + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + nand-controller@e0f00000 { + compatible = "intel,lgm-nand"; + reg = <0xe0f00000 0x100>, + <0xe1000000 0x300>, + <0xe1400000 0x8000>, + <0xe1c00000 0x1000>, + <0x17400000 0x4>, + <0x17c00000 0x4>; + reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", + "addr_sel0", "addr_sel1"; + clocks = <&cgu0 125>; + dmas = <&dma0 8>, <&dma0 9>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + nand-ecc-mode = "hw"; + }; + }; + +...