From patchwork Fri Oct 30 16:34:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 320004 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp1563409ilc; Fri, 30 Oct 2020 09:34:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxCjxfYYK49EE/ZbsOv4gh2mr1jH0/eusl1z01YJLT4plS+DAAtRemwcHii0yRLetPq7WSb X-Received: by 2002:a50:cf45:: with SMTP id d5mr3256915edk.225.1604075671563; Fri, 30 Oct 2020 09:34:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1604075671; cv=none; d=google.com; s=arc-20160816; b=skzzBNJxZ1IRGwK7gOjCL46/ZiiAcQ4g1LeQGnv/rPGUjq/G3mt+awOc+BNkGHJFvt ME85OJpRU2xvmK9OdOEReE1iyntmzueeJB2nnZoWZaYZd7k/Y135H6WYNyPK5NLci6iK iZiwctNCwoSjZ9YaBHwSMqsIpLZO8plt+xAL014XneYnbW3XG/y56be/cDGORx0ivjGz D3AJG/RzXU/t5ciy/O6uUE5GiVsEzFRjQ5wH5WuHBbp9tCCXR1EMBLPUrGpP/pAXH5SV kEJkV++gZyJoNO/kwrSnrGgDjfD8DLkUacV0SQ07fM/BbdnzAFDu/2URWbmi3sDptveX 1GcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OYYG+bPEQAKrvnUyay3Ge798oMm5TIrWSkpr0tXXXgA=; b=f9Jb4O2tPNeyNP8HdgvNrDszQoGRmlT3AF03GOJzHKjnxTjfupAc3yWGMDORy5dYB/ 1Z+4vvak2ZzfHHsl+6/Oy/ojqahqkOwk5wXQ4/6OVQo676pQbLl/Wncah2vdbBjsVTvA 7djrm3ZVA7CwdExdS/bbbIf5D3lKRwe8iSFDta58FzmrT01pzsDqfDaqcUwdxxcYTXEY nWHtSc2JwQhzAAR3b7VSPAXUw2Or9nJ9tYqXIY0bEf09X7x0EWmm1XBWibX4OlBt2Rb7 NqjZavPzTHNite7ZREKc4j8dMZC1vnir15+qHmyhlDE1rH84Zkl5gRCRRCKnG0Ki+fs9 MaGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IPXpUuBY; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id z6sm5031989wmi.1.2020.10.30.09.34.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2020 09:34:27 -0700 (PDT) From: Srinivas Kandagatla To: linus.walleij@linaro.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 1/2] dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings Date: Fri, 30 Oct 2020 16:34:20 +0000 Message-Id: <20201030163421.14041-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20201030163421.14041-1-srinivas.kandagatla@linaro.org> References: <20201030163421.14041-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree binding Documentation details for Qualcomm SM8250 LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver. Signed-off-by: Srinivas Kandagatla --- .../pinctrl/qcom,lpass-lpi-pinctrl.yaml | 129 ++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml -- 2.21.0 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..8a0732574aee --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) + Low Power Island (LPI) TLMM block + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + LPASS LPI IP on most Qualcomm SoCs + +properties: + compatible: + const: qcom,sm8250-lpass-lpi-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '^.*$': + if: + type: object + then: + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9])$" + minItems: 1 + maxItems: 14 + + function: + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data1, qua_mi2s_ws, + swr_tx_data2, qua_mi2s_data0, swr_rx_clk, qua_mi2s_data1, + swr_rx_data1, qua_mi2s_data2, swr_tx_data3, swr_rx_data2, + dmic1_clk, i2s1_clk, dmic1_data, i2s1_ws, dmic2_clk, + i2s1_data0, dmic2_data, i2s1_data1, i2s2_clk, wsa_swr_clk, + i2s2_ws, wsa_swr_data, dmic3_clk, i2s2_data0, dmic3_data, + i2s2_data1 ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + lpi_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm8250-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x355a000 0x1000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 14>; + }; From patchwork Fri Oct 30 16:34:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 314293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75C38C55178 for ; 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id z6sm5031989wmi.1.2020.10.30.09.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2020 09:34:28 -0700 (PDT) From: Srinivas Kandagatla To: linus.walleij@linaro.org, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver Date: Fri, 30 Oct 2020 16:34:21 +0000 Message-Id: <20201030163421.14041-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20201030163421.14041-1-srinivas.kandagatla@linaro.org> References: <20201030163421.14041-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add initial pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. Signed-off-by: Srinivas Kandagatla --- drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 781 +++++++++++++++++++++++ 3 files changed, 790 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 5fe7b8aaf69d..af26f4c51f77 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -236,4 +236,12 @@ config PINCTRL_SM8250 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8250 platform. +config PINCTRL_LPASS_LPI + tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" + depends on GPIOLIB && OF + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SoCs. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 9e3d9c91a444..c8520155fb1b 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o +obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c new file mode 100644 index 000000000000..88937485e3bb --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -0,0 +1,781 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../core.h" +#include "../pinctrl-utils.h" + +#define LPI_GPIO_REG_VAL_CTL 0x00 +#define LPI_GPIO_REG_DIR_CTL 0x04 +#define LPI_SLEW_REG_VAL_CTL 0x00 +#define LPI_SLEW_RATE_MAX 0x03 +#define LPI_SLEW_BITS_SIZE 0x02 +#define LPI_GPIO_REG_PULL_SHIFT 0x0 +#define LPI_GPIO_REG_PULL_MASK GENMASK(1, 0) +#define LPI_GPIO_REG_FUNCTION_SHIFT 0x2 +#define LPI_GPIO_REG_FUNCTION_MASK GENMASK(5, 2) +#define LPI_GPIO_REG_OUT_STRENGTH_SHIFT 0x6 +#define LPI_GPIO_REG_OUT_STRENGTH_MASK GENMASK(8, 6) +#define LPI_GPIO_REG_OE_SHIFT 0x9 +#define LPI_GPIO_REG_OE_MASK BIT(9) +#define LPI_GPIO_REG_DIR_SHIFT 0x1 +#define LPI_GPIO_REG_DIR_MASK 0x2 +#define LPI_GPIO_BIAS_DISABLE 0x0 +#define LPI_GPIO_PULL_DOWN 0x1 +#define LPI_GPIO_KEEPER 0x2 +#define LPI_GPIO_PULL_UP 0x3 + +#define LPI_FUNCTION(fname) \ + [LPI_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define LPI_PINGROUP(id, f1, f2, f3, f4) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .pin = id, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + }, \ + .nfuncs = 5, \ + } +struct lpi_pingroup { + const char *name; + const unsigned int *pins; + unsigned int npins; + unsigned int pin; + unsigned int *funcs; + unsigned int nfuncs; +}; + +struct lpi_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +struct lpi_pinctrl_variant_data { + int tlmm_reg_offset; + const struct pinctrl_pin_desc *pins; + int npins; + const struct lpi_pingroup *groups; + int ngroups; + const struct lpi_function *functions; + int nfunctions; + int *slew_reg_pin_offsets; +}; + +struct lpi_pinctrl { + struct device *dev; + struct pinctrl_dev *ctrl; + struct gpio_chip chip; + struct pinctrl_desc desc; + char __iomem *tlmm_base; + char __iomem *slew_base; + struct clk *core_vote; + struct clk *audio_vote; + struct mutex slew_access_lock; + const struct lpi_pinctrl_variant_data *data; +}; + +/* sm8250 variant specific data */ +#define SM8250_LPASS_PINS 14 + +static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), +}; + +enum sm8250_lpi_functions { + LPI_MUX_swr_tx_clk, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_swr_tx_data1, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_tx_data2, + LPI_MUX_qua_mi2s_data0, + LPI_MUX_swr_rx_clk, + LPI_MUX_qua_mi2s_data1, + LPI_MUX_swr_rx_data1, + LPI_MUX_qua_mi2s_data2, + LPI_MUX_swr_tx_data3, + LPI_MUX_swr_rx_data2, + LPI_MUX_dmic1_clk, + LPI_MUX_i2s1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_dmic2_clk, + LPI_MUX_i2s1_data0, + LPI_MUX_dmic2_data, + LPI_MUX_i2s1_data1, + LPI_MUX_i2s2_clk, + LPI_MUX_wsa_swr_clk, + LPI_MUX_i2s2_ws, + LPI_MUX_wsa_swr_data, + LPI_MUX_dmic3_clk, + LPI_MUX_i2s2_data0, + LPI_MUX_dmic3_data, + LPI_MUX_i2s2_data1, + LPI_MUX_gpio, + LPI_MUX_NA, +}; + +static const unsigned int gpio0_pins[] = { 0 }; +static const unsigned int gpio1_pins[] = { 1 }; +static const unsigned int gpio2_pins[] = { 2 }; +static const unsigned int gpio3_pins[] = { 3 }; +static const unsigned int gpio4_pins[] = { 4 }; +static const unsigned int gpio5_pins[] = { 5 }; +static const unsigned int gpio6_pins[] = { 6 }; +static const unsigned int gpio7_pins[] = { 7 }; +static const unsigned int gpio8_pins[] = { 8 }; +static const unsigned int gpio9_pins[] = { 9 }; +static const unsigned int gpio10_pins[] = { 10 }; +static const unsigned int gpio11_pins[] = { 11 }; +static const unsigned int gpio12_pins[] = { 12 }; +static const unsigned int gpio13_pins[] = { 13 }; +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data1_groups[] = { "gpio1" }; +static const char * const swr_tx_data2_groups[] = { "gpio2" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data1_groups[] = { "gpio4" }; +static const char * const swr_tx_data3_groups[] = { "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data0_groups[] = { "gpio2" }; +static const char * const qua_mi2s_data1_groups[] = { "gpio3" }; +static const char * const qua_mi2s_data2_groups[] = { "gpio4" }; +static const char * const swr_rx_data2_groups[] = { "gpio5" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data0_groups[] = { "gpio8" }; +static const char * const i2s1_data1_groups[] = { "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data0_groups[] = { "gpio12" }; +static const char * const i2s2_data1_groups[] = { "gpio13" }; + +static const struct lpi_pingroup sm8250_groups[] = { + LPI_PINGROUP(0, swr_tx_clk, qua_mi2s_sclk, NA, NA), + LPI_PINGROUP(1, swr_tx_data1, qua_mi2s_ws, NA, NA), + LPI_PINGROUP(2, swr_tx_data2, qua_mi2s_data0, NA, NA), + LPI_PINGROUP(3, swr_rx_clk, qua_mi2s_data1, NA, NA), + LPI_PINGROUP(4, swr_rx_data1, qua_mi2s_data2, NA, NA), + LPI_PINGROUP(5, swr_tx_data3, swr_rx_data2, NA, NA), + LPI_PINGROUP(6, dmic1_clk, i2s1_clk, NA, NA), + LPI_PINGROUP(7, dmic1_data, i2s1_ws, NA, NA), + LPI_PINGROUP(8, dmic2_clk, i2s1_data0, NA, NA), + LPI_PINGROUP(9, dmic2_data, i2s1_data1, NA, NA), + LPI_PINGROUP(10, i2s2_clk, wsa_swr_clk, NA, NA), + LPI_PINGROUP(11, i2s2_ws, wsa_swr_data, NA, NA), + LPI_PINGROUP(12, dmic3_clk, i2s2_data0, NA, NA), + LPI_PINGROUP(13, dmic3_data, i2s2_data1, NA, NA), +}; + +static const struct lpi_function sm8250_functions[] = { + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(swr_tx_data1), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_tx_data2), + LPI_FUNCTION(qua_mi2s_data0), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(qua_mi2s_data1), + LPI_FUNCTION(swr_rx_data1), + LPI_FUNCTION(qua_mi2s_data2), + LPI_FUNCTION(swr_tx_data3), + LPI_FUNCTION(swr_rx_data2), + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(i2s1_data0), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(i2s1_data1), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(wsa_swr_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(i2s2_data0), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s2_data1), +}; + +static int sm8250_slew_reg_offsets[] = { + 0x0, 0x2, 0x4, 0x8, 0xa, + 0xc, 0x0, 0x0, 0x0, 0x0, + 0x10, 0x12, 0x0, 0x0, +}; + +static struct lpi_pinctrl_variant_data sm8250_lpi_data = { + .tlmm_reg_offset = 0x1000, + .pins = sm8250_lpi_pins, + .npins = ARRAY_SIZE(sm8250_lpi_pins), + .slew_reg_pin_offsets = sm8250_slew_reg_offsets, + .groups = sm8250_groups, + .ngroups = ARRAY_SIZE(sm8250_groups), + .functions = sm8250_functions, + .nfunctions = ARRAY_SIZE(sm8250_functions), +}; + +static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, + unsigned int addr) +{ + return ioread32(state->tlmm_base + + state->data->tlmm_reg_offset * pin + addr); +} + +static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, + unsigned int addr, unsigned int val) +{ + iowrite32(val, state->tlmm_base + + state->data->tlmm_reg_offset * pin + addr); + + return 0; +} + +static int lpi_gpio_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->ngroups; +} + +static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->groups[group].name; +} + +static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctrl->data->groups[group].pins; + *num_pins = pctrl->data->groups[group].npins; + + return 0; +} + +static const struct pinctrl_ops lpi_gpio_pinctrl_ops = { + .get_groups_count = lpi_gpio_get_groups_count, + .get_group_name = lpi_gpio_get_group_name, + .get_group_pins = lpi_gpio_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->nfunctions; +} + +static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->functions[function].name; +} + +static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char *const **groups, + unsigned *const num_qgroups) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->data->functions[function].groups; + *num_qgroups = pctrl->data->functions[function].ngroups; + + return 0; +} + +static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, + unsigned int group_num) +{ + const struct lpi_pingroup *g = &sm8250_groups[group_num]; + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned int val; + int i, pin = g->pin; + + for (i = 0; i < g->nfuncs; i++) { + if (g->funcs[i] == function) + break; + } + + if (WARN_ON(i == g->nfuncs)) + return -EINVAL; + + val = lpi_gpio_read(pctrl, pin, LPI_GPIO_REG_VAL_CTL); + val &= ~(LPI_GPIO_REG_FUNCTION_MASK); + val |= i << LPI_GPIO_REG_FUNCTION_SHIFT; + lpi_gpio_write(pctrl, pin, LPI_GPIO_REG_VAL_CTL, val); + + return 0; +} + +static const struct pinmux_ops lpi_gpio_pinmux_ops = { + .get_functions_count = lpi_gpio_get_functions_count, + .get_function_name = lpi_gpio_get_function_name, + .get_function_groups = lpi_gpio_get_function_groups, + .set_mux = lpi_gpio_set_mux, +}; + +static int lpi_config_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + unsigned int param = pinconf_to_config_param(*config); + struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev); + unsigned int arg = 0; + int is_out; + int pull; + u32 ctl_reg; + + ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_REG_DIR_CTL); + + is_out = (ctl_reg & LPI_GPIO_REG_DIR_MASK) >> LPI_GPIO_REG_DIR_SHIFT; + + ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_REG_VAL_CTL); + + pull = (ctl_reg & LPI_GPIO_REG_PULL_MASK) >> LPI_GPIO_REG_PULL_SHIFT; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (pull == LPI_GPIO_BIAS_DISABLE) + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (pull == LPI_GPIO_PULL_DOWN) + arg = 1; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + if (pull == LPI_GPIO_KEEPER) + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (pull == LPI_GPIO_PULL_UP) + arg = 1; + break; + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT: + if (is_out) + arg = 1; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static unsigned int lpi_drive_to_regval(u32 arg) +{ + return (arg/2 - 1); +} + +static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int nconfs) +{ + unsigned int param, arg; + int i, ret = 0; + unsigned long val; + struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev); + bool output_enabled; + unsigned int pullup; + unsigned int strength; + unsigned int offset; + bool value; + + for (i = 0; i < nconfs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + pullup = LPI_GPIO_BIAS_DISABLE; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + pullup = LPI_GPIO_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + pullup = LPI_GPIO_KEEPER; + break; + case PIN_CONFIG_BIAS_PULL_UP: + pullup = LPI_GPIO_PULL_UP; + break; + case PIN_CONFIG_INPUT_ENABLE: + output_enabled = false; + break; + case PIN_CONFIG_OUTPUT: + output_enabled = true; + lpi_gpio_write(state, pin, LPI_GPIO_REG_DIR_CTL, + output_enabled << LPI_GPIO_REG_DIR_SHIFT); + value = arg; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + strength = arg; + break; + case PIN_CONFIG_SLEW_RATE: + if (arg > LPI_SLEW_RATE_MAX) { + dev_err(pctldev->dev, "%s: invalid slew rate %u for pin: %d\n", + __func__, arg, pin); + goto set_gpio; + } + + mutex_lock(&state->slew_access_lock); + + val = ioread32(state->slew_base + LPI_SLEW_REG_VAL_CTL); + + offset = state->data->slew_reg_pin_offsets[pin]; + for (i = 0; i < LPI_SLEW_BITS_SIZE; i++) { + if (arg & 0x01) + set_bit(offset, &val); + else + clear_bit(offset, &val); + offset++; + arg = arg >> 1; + } + + iowrite32(val, state->slew_base + LPI_SLEW_REG_VAL_CTL); + + mutex_unlock(&state->slew_access_lock); + break; + default: + ret = -EINVAL; + goto done; + } + } + +set_gpio: + + val = lpi_gpio_read(state, pin, LPI_GPIO_REG_VAL_CTL); + val &= ~(LPI_GPIO_REG_PULL_MASK | LPI_GPIO_REG_OUT_STRENGTH_MASK | + LPI_GPIO_REG_OE_MASK); + val |= pullup << LPI_GPIO_REG_PULL_SHIFT; + val |= lpi_drive_to_regval(strength) << LPI_GPIO_REG_OUT_STRENGTH_SHIFT; + if (output_enabled) + val |= value << LPI_GPIO_REG_OE_SHIFT; + + lpi_gpio_write(state, pin, LPI_GPIO_REG_VAL_CTL, val); + lpi_gpio_write(state, pin, LPI_GPIO_REG_DIR_CTL, + output_enabled << LPI_GPIO_REG_DIR_SHIFT); +done: + return ret; +} + +static const struct pinconf_ops lpi_gpio_pinconf_ops = { + .is_generic = true, + .pin_config_group_get = lpi_config_get, + .pin_config_group_set = lpi_config_set, +}; + +static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); + + return lpi_config_set(state->ctrl, pin, &config, 1); +} + +static int lpi_gpio_direction_output(struct gpio_chip *chip, + unsigned int pin, int val) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); + + return lpi_config_set(state->ctrl, pin, &config, 1); +} + +static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + int value; + + value = lpi_gpio_read(state, pin, LPI_GPIO_REG_VAL_CTL); + return value; +} + +static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); + + lpi_config_set(state->ctrl, pin, &config, 1); +} + +#ifdef CONFIG_DEBUG_FS +#include + +static unsigned int lpi_regval_to_drive(u32 val) +{ + return (val + 1) * 2; +} + +static void lpi_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned int offset, + unsigned int gpio) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + struct pinctrl_pin_desc pindesc; + unsigned int func; + int is_out; + int drive; + int pull; + u32 ctl_reg; + + static const char * const pulls[] = { + "no pull", + "pull down", + "keeper", + "pull up" + }; + + pctldev = pctldev ? : state->ctrl; + pindesc = pctldev->desc->pins[offset]; + ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_REG_DIR_CTL); + is_out = (ctl_reg & LPI_GPIO_REG_DIR_MASK) >> LPI_GPIO_REG_DIR_SHIFT; + ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_REG_VAL_CTL); + + func = (ctl_reg & LPI_GPIO_REG_FUNCTION_MASK) >> + LPI_GPIO_REG_FUNCTION_SHIFT; + drive = (ctl_reg & LPI_GPIO_REG_OUT_STRENGTH_MASK) >> + LPI_GPIO_REG_OUT_STRENGTH_SHIFT; + pull = (ctl_reg & LPI_GPIO_REG_PULL_MASK) >> LPI_GPIO_REG_PULL_SHIFT; + + seq_printf(s, " %-8s: %-3s %d", + pindesc.name, is_out ? "out" : "in", func); + seq_printf(s, " %dmA", lpi_regval_to_drive(drive)); + seq_printf(s, " %s", pulls[pull]); +} + +static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned int gpio = chip->base; + unsigned int i; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio); + seq_puts(s, "\n"); + } +} + +#else +#define lpi_gpio_dbg_show NULL +#endif + +static const struct gpio_chip lpi_gpio_template = { + .direction_input = lpi_gpio_direction_input, + .direction_output = lpi_gpio_direction_output, + .get = lpi_gpio_get, + .set = lpi_gpio_set, + .request = gpiochip_generic_request, + .free = gpiochip_generic_free, + .dbg_show = lpi_gpio_dbg_show, +}; + +static int lpi_pinctrl_probe(struct platform_device *pdev) +{ + int ret, npins; + struct clk *core_vote = NULL; + struct clk *audio_vote = NULL; + + struct lpi_pinctrl *pctrl; + const struct lpi_pinctrl_variant_data *data; + struct device *dev = &pdev->dev; + struct resource *res; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctrl); + + data = of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + pctrl->data = data; + pctrl->dev = &pdev->dev; + npins = data->npins; + + /* Register LPASS core hw vote */ + core_vote = devm_clk_get(&pdev->dev, "core"); + if (IS_ERR(core_vote)) { + dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n", + __func__, "core_vote", ret); + return PTR_ERR(core_vote); + } + pctrl->core_vote = core_vote; + + /* Register LPASS audio hw vote */ + audio_vote = devm_clk_get(&pdev->dev, "audio"); + if (IS_ERR(audio_vote)) { + dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n", + __func__, "audio_vote", ret); + return PTR_ERR(audio_vote); + } + clk_prepare_enable(pctrl->core_vote); + clk_prepare_enable(pctrl->audio_vote); + + pctrl->audio_vote = audio_vote; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pctrl->tlmm_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctrl->tlmm_base)) { + ret = PTR_ERR(pctrl->tlmm_base); + goto err; + } + + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + pctrl->slew_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctrl->slew_base)) { + ret = PTR_ERR(pctrl->slew_base); + goto err; + } + + pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops; + pctrl->desc.pmxops = &lpi_gpio_pinmux_ops; + pctrl->desc.confops = &lpi_gpio_pinconf_ops; + + pctrl->desc.owner = THIS_MODULE; + pctrl->desc.name = dev_name(dev); + pctrl->desc.pins = data->pins; + pctrl->desc.npins = data->npins; + + pctrl->chip = lpi_gpio_template; + pctrl->chip.parent = dev; + pctrl->chip.base = -1; + pctrl->chip.ngpio = npins; + pctrl->chip.label = dev_name(dev); + pctrl->chip.of_gpio_n_cells = 2; + pctrl->chip.can_sleep = false; + + mutex_init(&pctrl->slew_access_lock); + + pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->ctrl)) { + ret = PTR_ERR(pctrl->ctrl); + goto err_pinctrl; + } + + ret = gpiochip_add_data(&pctrl->chip, pctrl); + if (ret) { + dev_err(pctrl->dev, "can't add gpio chip\n"); + goto err_pinctrl; + } + + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(dev), 0, 0, npins); + if (ret) { + dev_err(dev, "failed to add pin range\n"); + goto err_range; + } + + return 0; + +err_range: + gpiochip_remove(&pctrl->chip); +err_pinctrl: + mutex_destroy(&pctrl->slew_access_lock); +err: + clk_disable_unprepare(pctrl->core_vote); + clk_disable_unprepare(pctrl->audio_vote); + + return ret; +} + +static int lpi_pinctrl_remove(struct platform_device *pdev) +{ + struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev); + + gpiochip_remove(&pctrl->chip); + mutex_destroy(&pctrl->slew_access_lock); + clk_disable_unprepare(pctrl->core_vote); + clk_disable_unprepare(pctrl->audio_vote); + + return 0; +} + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm8250-lpass-lpi-pinctrl", + .data = &sm8250_lpi_data, + }, + { }, +}; + +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); + +MODULE_DESCRIPTION("QTI LPI GPIO pin control driver"); +MODULE_LICENSE("GPL v2");