From patchwork Mon Oct 5 22:59:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 314082 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp82411ilm; Mon, 5 Oct 2020 15:59:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy3couZuK6eWsvAgZLjE05tAjlmgjZQM8GPbrp9/eWNHXNa5nHDuetIowAGqWpdsJYUBkej X-Received: by 2002:a17:907:270f:: with SMTP id w15mr1999126ejk.505.1601938767775; Mon, 05 Oct 2020 15:59:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601938767; cv=none; d=google.com; s=arc-20160816; b=OqA51TgGiR7sxRFmUZFMKFRFyn2E9tfYyzDDHmrlwU5gK3LK8LMqmqu1O17ol6Wlo7 uGQMOekh5WOmYssU0uRLUjDPuj2pjeV0fcbuvKelxMv+9vOyDgT2QdFifenGI3dVJHtl AAcVCL0vqrdklY2hKsxKRBmOIQhvQQZaqRmvr7tP9vgGefve0nlgkqAMp+zEynlv5+pK 6+afuexWuRPREFW8gBxvuhHZvWqHAyKs4675HitlQFUqaopUchurJmWawhf7XVUTEgtg BDnL59g79tPFQl51YuQQCLxH8dD2DkeX728/HDkpbHz1TEiXX0HtMQUf+jXy6bShyooG wggw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ec+lFJXXpYdKVcAgS5nPom7szthl3JZjRQTJpgctzh8=; b=j6OBdvGiJbl+903xrfnOhK1rOrMNyoPzxS8xgD/ZEGLdFf28BmPVVcevax6KeT1xF7 YA4vjYbbYPLCYIw6eaA/yaSc4hrhqvlvGj8vJUsEvvaBXcCp9wOPfAjv1giTnMLLbIBk npyK/qWT58Q83c2juFN1LpA7IeRqiYkMm7rFdp4mvW4JA7eGpKtmVDXpKroj9PjhluxL ldLdReWoeAn9p+k92/kCoUonAVQJAovrhawxQQWXqXgfGJiwkULbc+Ii9mem5sVEZywf W2BizpLPAeLH2ZZRKOz3ch6a10A8mlQl23k2N4xetHEjmmFOhnIZCSMZntzflbsPl+pg eG3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Np6/nG/e"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id s18si663958ejr.128.2020.10.05.15.59.27; Mon, 05 Oct 2020 15:59:27 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Np6/nG/e"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725861AbgJEW7Y (ORCPT + 6 others); Mon, 5 Oct 2020 18:59:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725917AbgJEW7X (ORCPT ); Mon, 5 Oct 2020 18:59:23 -0400 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B3A8C0613A7 for ; Mon, 5 Oct 2020 15:59:23 -0700 (PDT) Received: by mail-lj1-x243.google.com with SMTP id 133so5976365ljj.0 for ; Mon, 05 Oct 2020 15:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ec+lFJXXpYdKVcAgS5nPom7szthl3JZjRQTJpgctzh8=; b=Np6/nG/eJvBBMJLrAgvsX1rVlX8XCQOEJb0clj70XhtGRdyKiyeOBwUVTBucC/u5kf 47NjAtgZK69FJUtmEbCvRqm+A2CPkOQ2UONrAitFKQGyhs0giW1c4OkLW3rerCDtTekK mEEuH7Y7vH483S6+BXG4ufi7pPeDBIcG0jXMBvyhTqnEVgumunXeZWj02d+isIZEwKrQ 34+42k+jwDSHB+HvH7V5KCyJ8/+XI4//cLhn4SRFu7bIdJ8TgKbapqbONqzCihjyrcDE Gdf7gkQgkK6O58YRPQwN9HMdB9R2HX5nZAXw5fFVn8ZeVBieMRz4pfvjvOD5OVyZz3o0 G3Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ec+lFJXXpYdKVcAgS5nPom7szthl3JZjRQTJpgctzh8=; b=MIAsEFomRVdCCXhaTMYQWlv8zrq5zKpwmZa3VIfweMnPQhAaS9OJzkE9oyRlIc802b 5KsBOi8EX5swkGJ+xt7klpN9oP2TGKp8Xst17EWbZcUDOlY0Uo/F9wyfUtS41i27se8i QzNgTBg1IYXwTiep6ZCFdz7bWFwTdrcNdlkQDj97XRTKmwauPse+EBIboLCxKQvecxfo jrHxjCGzxLIZp8xQF32MjTn+yt1OFpG/pvmQLCEjr1w9NFYfFyIVy27xlI6fImmfMrrj HQjNAtXkUbikpHo6ZqqefA1aU2HyTKJd8jbZ2SJ2xZ1yVXa9f1glJsQ4dlqxdd3ijW8k GDwg== X-Gm-Message-State: AOAM531l5BE01vHApRz6fbEui/NbV7UtPGuLLwah5hLVaRIHSIyZPjT7 EDuKfspKbFv5iFBTluq2y8yegqrkj+XOTA== X-Received: by 2002:a2e:c49:: with SMTP id o9mr647629ljd.296.1601938761840; Mon, 05 Oct 2020 15:59:21 -0700 (PDT) Received: from eriador.lan ([188.162.64.219]) by smtp.gmail.com with ESMTPSA id x4sm353831ljc.80.2020.10.05.15.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Oct 2020 15:59:21 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Jonathan Marek , Stephen Boyd , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Rob Herring Subject: [PATCH v1 1/3] dt-bindings: clock: qcom, dispcc: document power domain bindings Date: Tue, 6 Oct 2020 01:59:12 +0300 Message-Id: <20201005225914.315852-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201005225914.315852-1-dmitry.baryshkov@linaro.org> References: <20201005225914.315852-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SM8250 requires special power domain for accessing MMDS_GDSC registers. Add bindings for the MMCX power domain. Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring --- .../bindings/clock/qcom,sdm845-dispcc.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) -- 2.28.0 diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml index 4a3be733d042..ff0db55470ac 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml @@ -58,6 +58,16 @@ properties: reg: maxItems: 1 + power-domains: + maxItems: 1 + + power-domain-names: + items: + - const: mmcx + + required-opps: + maxItems: 1 + required: - compatible - reg @@ -73,6 +83,7 @@ examples: - | #include #include + #include clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; reg = <0x0af00000 0x10000>; @@ -97,5 +108,22 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + /* this is a part of sm8250 setup the power domain example */ + power-domains = <&rpmhpd SDM845_CX>; + power-domain-names = "mmcx"; + required-opps = <&rpmhpd_opp_low_svs>; + }; + rpmhpd: power-controller { + compatible = "qcom,sdm845-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + }; }; ... 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MMCX needs to be enabled to be able to access GDSC registers and to enable display clocks. Use dev_pm/opp to enable corresponding power domain. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gdsc.c | 56 ++++++++++++++++++++++++++++++++++++++--- drivers/clk/qcom/gdsc.h | 5 ++++ 2 files changed, 57 insertions(+), 4 deletions(-) -- 2.28.0 diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index bfc4ac02f9ea..c9e1619074f8 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -110,13 +111,31 @@ static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) return -ETIMEDOUT; } +static int gdsc_toggle_supply_on(struct gdsc *sc) +{ + if (sc->rsupply) + return regulator_enable(sc->rsupply); + if (sc->pd_dev) + return dev_pm_genpd_set_performance_state(sc->pd_dev, sc->pd_opp); + return 0; +} + +static int gdsc_toggle_supply_off(struct gdsc *sc) +{ + if (sc->pd_dev) + return dev_pm_genpd_set_performance_state(sc->pd_dev, 0); + if (sc->rsupply) + return regulator_disable(sc->rsupply); + return 0; +} + static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) { int ret; u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK; - if (status == GDSC_ON && sc->rsupply) { - ret = regulator_enable(sc->rsupply); + if (status == GDSC_ON) { + ret = gdsc_toggle_supply_on(sc); if (ret < 0) return ret; } @@ -153,8 +172,8 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) ret = gdsc_poll_status(sc, status); WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n"); - if (!ret && status == GDSC_OFF && sc->rsupply) { - ret = regulator_disable(sc->rsupply); + if (!ret && status == GDSC_OFF) { + ret = gdsc_toggle_supply_off(sc); if (ret < 0) return ret; } @@ -407,6 +426,27 @@ int gdsc_register(struct gdsc_desc *desc, return PTR_ERR(scs[i]->rsupply); } + for (i = 0; i < num; i++) { + if (!scs[i] || !scs[i]->domain) + continue; + + scs[i]->pd_opp = of_get_required_opp_performance_state(dev->of_node, scs[i]->perf_idx); + if (scs[i]->pd_opp < 0) + return scs[i]->pd_opp; + + scs[i]->pd_dev = dev_pm_domain_attach_by_name(dev, scs[i]->domain); + if (IS_ERR(scs[i]->pd_dev)) { + ret = PTR_ERR(scs[i]->pd_dev); + /* Single domain has been already attached, so reuse dev */ + if (ret == -EEXIST) { + scs[i]->pd_dev = dev; + } else { + scs[i]->pd_dev = NULL; + goto pm_detach; + } + } + } + data->num_domains = num; for (i = 0; i < num; i++) { if (!scs[i]) @@ -428,6 +468,12 @@ int gdsc_register(struct gdsc_desc *desc, } return of_genpd_add_provider_onecell(dev->of_node, data); + +pm_detach: + for (i = 0; i < num; i++) + if (scs[i]->pd_dev && scs[i]->pd_dev != dev) + dev_pm_domain_detach(scs[i]->pd_dev, false); + return ret; } void gdsc_unregister(struct gdsc_desc *desc) @@ -443,6 +489,8 @@ void gdsc_unregister(struct gdsc_desc *desc) continue; if (scs[i]->parent) pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); + if (scs[i]->pd_dev && scs[i]->pd_dev != dev) + dev_pm_domain_detach(scs[i]->pd_dev, true); } of_genpd_del_provider(dev->of_node); } diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index bd537438c793..d58575f8f25f 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -57,6 +57,11 @@ struct gdsc { const char *supply; struct regulator *rsupply; + + const char *domain; + unsigned int perf_idx; + struct device *pd_dev; + int pd_opp; }; struct gdsc_desc { From patchwork Mon Oct 5 22:59:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 314084 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp82445ilm; Mon, 5 Oct 2020 15:59:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxnmC/DtpgVyjVigbb7fpmqernKEjP8ldWAmn0yA5uUW1Dp3E+5S3at0upGvts6oq2M2cPQ X-Received: by 2002:a17:906:9588:: with SMTP id r8mr2102242ejx.389.1601938770767; Mon, 05 Oct 2020 15:59:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601938770; cv=none; d=google.com; s=arc-20160816; b=Ec+c19Ct775otHphcsrla68YAX1fbl2Lv6PCrB9Lmvz15poCxu6jBFyOTxkZogMGhk +08fw+CT0e8TITJ1G+1Hs6DUoL6flndxeOhmic3Xii3/SOP0JtJOW6oVj9pXQyR9nIXu 0iI7kSsG9P2M4GXM1qPDgwdWu1733WeZMr9gUkV8/sWIxPsML94Q3200iLfeMM13iRqn 0yvKD2zr2dUBXShcRX4il7nzrlSnkhaHG3q9L4+kzGu/cWWbuJWMdUXORPcHx9mFZ0Id 928oeBjhU/DXNaWR2+6rz2SHCRCWvCpYIQ5qNj4w3DamGF+zO14Dfsrr75utd8xHwB4X Jt0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=URbRbK8Q61G+2pVymEoBNgHS+ZaND/H3JCVWYbn/B1M=; b=zLFUYxebYalfLoNf+D3gMgwZ9DlRtQJNU7Z0MZlHpBsQuz2LakWzY1eypTZWZLDIlF YBRDZ/iFqzMXhSyTeKymwby7JvRmOEsLbIjbBLVRwcIjeJZ/IcxvAI6iWShiTnG0DehP Q0B9iiZhCEGUIPO7u3D0sY5eJ1FZpTtYNAdcY7sYFFzTyzpNuHVyKRIXUbpA/iVDaEOv 9j8eqOFzmQMgVILrlW8VCn+CR7YKVn/fVm7d00OHBN6dtfjRctEe8ExZRA2htbfPQ+D4 Vsp6JxSLqQKSVhSU9z6vnON/sLPOuaNQE4LZQFd+QqVSd+59iQn17WvLjfAEtTihhnte ssWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xgC22HA4; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Enable using this power domain for the gdsc. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.28.0 diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 07a98d3f882d..3941054a7b07 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -963,6 +963,8 @@ static struct gdsc mdss_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = HW_CTRL, + .domain = "mmcx", + .perf_idx = 0, }; static struct clk_regmap *disp_cc_sm8250_clocks[] = {