From patchwork Wed Sep 30 15:09:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 313904 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:1081:0:0:0:0 with SMTP id r1csp296394ilj; Wed, 30 Sep 2020 08:10:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx/Pkl42deSuOvxSTkTIKQW9W+ViMB0FLDoM9zLmqVcw52f3xPgswQCAqea5O5o6aV0BnfU X-Received: by 2002:a17:906:b097:: with SMTP id x23mr3218627ejy.21.1601478615087; Wed, 30 Sep 2020 08:10:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601478615; cv=none; d=google.com; s=arc-20160816; b=d5rNpk8bS0Ey9ZVC7TU59g0Sbou1IPh0Wx118+sibj90oHIyZQpFbv+jdJxrIAWfYI ZV0CfsmbAqCRsnEhyN0VM11BE+M2JtBVDzIZEI3ZL/dhPYo+vwsrB7qnA8NXeJLiktvv p6xjuzPVuj7nejHbTN6d+ZwyBN5dLuwaNhTd98hENp8rdO6g7JWFhmXWsmnxzGrVCelA rEv6/pko6d09h+xFyO8ND7KOwxMIU+3e15PRXyv+6Ds4fruwUs/fb0GqYE+c4MjI7c/P 3LAv7UR6pkMghGoQ9MlskcgqAeiaAmAfvoFAJFddN9BU1iqqWnQv+ZmvcEMn7Ac3Fxvp i1QA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=0ChHcHi6Ji1r+llty/7EuPk/EuojfII4VV6B3JIzI5g=; b=AHGVce3rC6mbi1ODdj7wUUTTA3quvwvFQLB6tPD5xu57FejkBV2yk8PJ1BqBQpAtPk 3oYHfgUa52vxkTtuaLVIlLRsjFn2tKZumhiGpjrt6jFUHExoyqx7k8sqqztHNu6UZnsS OkHAVoIZeo5mhaeDXOYgaMFVKBF23kx3stZZW3UXXNdzt0p6ej8aHxwXcUwD6sFVG+Zm 5+0mA4iV0qBN6PVn+bkQUWCbN/66mVvv4jlS/b2782owBmrR/M2xWTXCQvvQtEfHsD3K RyAgAKsp8OqtUDfEHu2qja/UutaDwnF5k+UafYuRnUp1xe+VNesiFkGPnBdXuaYyW/zx W9FA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NQhqVoP9; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n5si1403051ejk.375.2020.09.30.08.10.14; Wed, 30 Sep 2020 08:10:15 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NQhqVoP9; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730737AbgI3PKO (ORCPT + 6 others); Wed, 30 Sep 2020 11:10:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730707AbgI3PKN (ORCPT ); Wed, 30 Sep 2020 11:10:13 -0400 Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43219C0613D2 for ; Wed, 30 Sep 2020 08:10:12 -0700 (PDT) Received: by mail-pg1-x543.google.com with SMTP id g29so1294349pgl.2 for ; Wed, 30 Sep 2020 08:10:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0ChHcHi6Ji1r+llty/7EuPk/EuojfII4VV6B3JIzI5g=; b=NQhqVoP9cYIyfFnw9k09wKwqLsbH49x5IC5GDEwAcLjUdNRR5756qj3mo/pPvivvQH vfRNzsT/mBdWhClDg9f2SpHLf8rMFt7wAukhnTkVI8s4Yp64//zU6YGtYPYfvEyqcUIi xuKmtwsa+ResLjY8eIw1nDRlE2dcjlKS4AdlITloMbDOk8Rorp/YGef7ZGgPF8HGKUzI XqmRCYYLurQw1cRznFu46U+alB5k2ksrYHoOxFyeEwTN/Uc1SYiWYxSQk2KynBdpZ0ic GWi0Qxojhv7K4CPOWd9zsDB2COYYvRedcUKPzqFW58aTEJE+VxZByi4fH2FuRQBvl1Cs amzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0ChHcHi6Ji1r+llty/7EuPk/EuojfII4VV6B3JIzI5g=; b=s/pZJ5//catQXCSLBCRVaz9Sllrw4Ti2M2QL+adl+myZ+96WOSpvW57MXjg6R4brud +dXkn172v4tdHRcql6D5uAdX+j/yWywSOSHj8Ebm7TKCn5M4pw4ynnKVIcu96HxA/jyb LwSHjdy1yyMyfjahe3JM5mLwMv96jSfnMWsqy4PEzhhhQf8MMKjlSRrQqt6b4Z1CHvT4 4hLsUjZ9eTbKHiMmw6dkapXOtI8omHNJF88jT5ll78dBGcuviZqO3tlA/8NZscMBwqJ/ ThmtpGp40+e8DHFBLGbTldsRtyK0c6meBJFMk+8MSEUT5V3JmkQV5l/t9G/5Yb4WZCCN jdZQ== X-Gm-Message-State: AOAM5303JEHEGdG1c1V5oqGf8nei/HQIbgAuyzxHWN82/1r8tRzKzqQ6 QbTH44emY+N5p4LF/G9393wr X-Received: by 2002:a65:68c4:: with SMTP id k4mr2425222pgt.18.1601478611770; Wed, 30 Sep 2020 08:10:11 -0700 (PDT) Received: from Mani-XPS-13-9360.localdomain ([2409:4072:6004:2356:f1f4:5bc8:894a:8c50]) by smtp.gmail.com with ESMTPSA id o6sm2456444pjp.33.2020.09.30.08.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2020 08:10:10 -0700 (PDT) From: Manivannan Sadhasivam To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, robh@kernel.org Cc: svarbanov@mm-sol.com, bhelgaas@google.com, lorenzo.pieralisi@arm.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 3/5] dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC Date: Wed, 30 Sep 2020 20:39:23 +0530 Message-Id: <20200930150925.31921-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930150925.31921-1-manivannan.sadhasivam@linaro.org> References: <20200930150925.31921-1-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the PCIe DT bindings for SM8250 SoC. The PCIe IP is similar to the one used on SDM845, hence just add the compatible along with the optional "atu" register region. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 02bc81bb8b2d..3b55310390a0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -13,6 +13,7 @@ - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sdm845" for sdm845 + - "qcom,pcie-sm8250" for sm8250 - reg: Usage: required @@ -27,6 +28,7 @@ - "dbi" DesignWare PCIe registers - "elbi" External local bus interface registers - "config" PCIe configuration space + - "atu" ATU address space (optional) - device_type: Usage: required @@ -131,7 +133,7 @@ - "slave_bus" AXI Slave clock -clock-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -206,7 +208,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: Definition: Should contain the following entries - "pci" PCIe core reset From patchwork Wed Sep 30 15:09:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 313906 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:1081:0:0:0:0 with SMTP id r1csp296653ilj; Wed, 30 Sep 2020 08:10:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyqg2HH23PW1xiSLuTbpfiCS6BX7weZJGO+OU31HWo7T/dakT/I+HgU2s7M71YYYwDirUEf X-Received: by 2002:a17:906:fa81:: with SMTP id lt1mr3236270ejb.459.1601478629760; Wed, 30 Sep 2020 08:10:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601478629; cv=none; d=google.com; s=arc-20160816; b=BPvDUGuZce8O2C29+Gyp8Mw+gIy4mS5yKDZkPrEH4WokGyu4BxT+s/LI1+Qbn/DUPq 7+7k/WOUifbRaJsPh7dOkk76SJQ/TyNKMuMgoUVvtlCWnjPzT4AhU9t+GYO+HpyN5iJp VbBXKxZ4JpCoJZnSTNurGj+Mlrhtglqn3frpJXfpy9wJ27koQ/a4uVMsmZc5cE4l5skF 6TmfGgcvVOvaTo9c0sQcijNztY609Uak9xhjqP9GscI59WXWnaNGN2Lt40uBfRFL0sIs JHHwnh9CxCTnKnNdiFt8FJegtXkpayZWUEeDEHANUjuXjwqXxulnxyEimk1oukPuemMU 3Vpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=WhwMtdikDEzHjRtFcm4TCx29sJ5RkUwcjaQiJ5505Ng=; b=BVI1e58G+anQtbC5YS5VT1nG2KgLsTgVk7yBtUx2Rxtuw9hugug+Re10n0zijkxBK7 51y5Q7xJBIqRJOHNTtf6/8bkfBT0+f0zkoDyK5SmM2EgZpvRaNpI+fw1LG2SMmHkfMOt AQ81K+/3Orv8AdoL1WkGemQH6+j/khedBAD/S7UUcV6oRMS/jGjC+aHGm/CbnMBEg3No 5qksJgFY6M2R8RdH5yeLh8+G4NCQ29CF0Klthc54YsoHYt7m1Lz4dmUkM6G8suUB3CTv K/UUcy9MwNveeHlPkSc80nOR2uvIlZ9PmCu+9JEuFETC+Wa6ui3+n2tI+6qHlRifVB7B sbow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OIciySyN; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v24si1361329eju.655.2020.09.30.08.10.29; Wed, 30 Sep 2020 08:10:29 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OIciySyN; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727426AbgI3PK3 (ORCPT + 6 others); Wed, 30 Sep 2020 11:10:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730805AbgI3PK2 (ORCPT ); Wed, 30 Sep 2020 11:10:28 -0400 Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DDBEC0613D2 for ; Wed, 30 Sep 2020 08:10:28 -0700 (PDT) Received: by mail-pf1-x443.google.com with SMTP id b124so1347779pfg.13 for ; Wed, 30 Sep 2020 08:10:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WhwMtdikDEzHjRtFcm4TCx29sJ5RkUwcjaQiJ5505Ng=; b=OIciySyNgf/WZFzRhp0Vz168dBRTzttOPICfw6sitXtaws3LXK73XY/ia/5lcuyOGl Qf4TslwCjjgVKALbtRhzjyIUw1sLEOo948vLnOWg+yjmQdyTh7DVOa/caEOYUUJiqa7i dEDSfCOanyAgIVqhHTM8vHk5XGN8+fkQIe/mkMWMjccIw5f2ZwDt8wgb8qlJN5fy0YtR g02Q19CuRSRIsXHTkD61dUWNP8xdkGq08FMFC9+xAvA3jJUbaJZfqC7q050wKomBQb0O xTEkgBquREsrbemPPVI3H398eFHWshArqZJDw+Nd39ZgHSAHEn2sRvUAzK68284PGNGj QREg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WhwMtdikDEzHjRtFcm4TCx29sJ5RkUwcjaQiJ5505Ng=; b=sIVEFAxzcfou5pD+WQH/HtblOe4Beu4WavEICWP/dCxbpVu9f6nqhnAIvXPMs0z8iK eq2g1tHcfc+HeoeaZI8UxTDYvOHylOG6Vx4U1o8GKtSUCO7zTFxEZARsBaKy2glSRtaa 7uXXrSoSrW1cEaYMI0cr7oUFIRlWcdfIclKa24zXShdnSXnEIEzLIpsiK19mLEB3Aifr v0VaA1QLfQKvE2NyPJURZoj+jHB/yr6ipWvErUmATMe67fWT/RixlRbbfs7DqGsM1kLE dOBjY6mYAHf7UumaE7x5OWGYyfdElJzAidF5WJRqHnuikCMmGogUwaak4Bj/AYxMwGX3 zPTw== X-Gm-Message-State: AOAM530fyFwhDf1Gs1rVR8CJZ+F1LeEdOmEPyMeVEtXeyi/jqP3YAda4 UvPE4llPazGY5T/OHkHAVgH1 X-Received: by 2002:a62:7e13:0:b029:14b:fcbd:60dd with SMTP id z19-20020a627e130000b029014bfcbd60ddmr2829411pfc.46.1601478627330; Wed, 30 Sep 2020 08:10:27 -0700 (PDT) Received: from Mani-XPS-13-9360.localdomain ([2409:4072:6004:2356:f1f4:5bc8:894a:8c50]) by smtp.gmail.com with ESMTPSA id o6sm2456444pjp.33.2020.09.30.08.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2020 08:10:26 -0700 (PDT) From: Manivannan Sadhasivam To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, robh@kernel.org Cc: svarbanov@mm-sol.com, bhelgaas@google.com, lorenzo.pieralisi@arm.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 5/5] PCI: qcom: Add support for configuring BDF to SID mapping for SM8250 Date: Wed, 30 Sep 2020 20:39:25 +0530 Message-Id: <20200930150925.31921-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930150925.31921-1-manivannan.sadhasivam@linaro.org> References: <20200930150925.31921-1-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For SM8250, we need to write the BDF to SID mapping in PCIe controller register space for proper working. This is accomplished by extracting the BDF and SID values from "iommu-map" property in DT and writing those in the register address calculated from the hash value of BDF. In case of collisions, the index of the next entry will also be written. For the sake of it, let's introduce a "config_sid" callback and do it conditionally for SM8250. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 138 +++++++++++++++++++++++++ 2 files changed, 139 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 044a3761c44f..3e9ccdc45ee1 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -169,6 +169,7 @@ config PCIE_QCOM depends on OF && (ARCH_QCOM || COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST + select CRC8 help Say Y here to enable PCIe controller support on Qualcomm SoCs. The PCIe controller uses the DesignWare core plus Qualcomm-specific diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 44db91861b47..a7f05b78315b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -57,6 +58,7 @@ #define PCIE20_PARF_SID_OFFSET 0x234 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C #define PCIE20_PARF_DEVICE_TYPE 0x1000 +#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000 #define PCIE20_ELBI_SYS_CTRL 0x04 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) @@ -101,6 +103,9 @@ #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 + +#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) + struct qcom_pcie_resources_2_1_0 { struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; struct reset_control *pci_reset; @@ -183,6 +188,16 @@ struct qcom_pcie_ops { void (*deinit)(struct qcom_pcie *pcie); void (*post_deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); + int (*config_sid)(struct qcom_pcie *pcie); +}; + +/* sid info structure */ +struct qcom_pcie_sid_info_t { + u16 bdf; + u8 pcie_sid; + u8 hash; + u32 smmu_sid; + u32 value; }; struct qcom_pcie { @@ -193,6 +208,8 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; + struct qcom_pcie_sid_info_t *sid_info; + u32 sid_info_len; int gen; }; @@ -1257,6 +1274,120 @@ static int qcom_pcie_link_up(struct dw_pcie *pci) return !!(val & PCI_EXP_LNKSTA_DLLLA); } +static int qcom_pcie_get_iommu_map(struct qcom_pcie *pcie) +{ + /* iommu map structure */ + struct { + u32 bdf; + u32 phandle; + u32 smmu_sid; + u32 smmu_sid_len; + } *map; + struct device *dev = pcie->pci->dev; + int i, size = 0; + u32 smmu_sid_base; + + of_get_property(dev->of_node, "iommu-map", &size); + if (!size) + return 0; + + map = kzalloc(size, GFP_KERNEL); + if (!map) + return -ENOMEM; + + of_property_read_u32_array(dev->of_node, + "iommu-map", (u32 *)map, size / sizeof(u32)); + + pcie->sid_info_len = size / (sizeof(*map)); + pcie->sid_info = devm_kcalloc(dev, pcie->sid_info_len, + sizeof(*pcie->sid_info), GFP_KERNEL); + if (!pcie->sid_info) { + kfree(map); + return -ENOMEM; + } + + /* Extract the SMMU SID base from the first entry of iommu-map */ + smmu_sid_base = map[0].smmu_sid; + for (i = 0; i < pcie->sid_info_len; i++) { + pcie->sid_info[i].bdf = map[i].bdf; + pcie->sid_info[i].smmu_sid = map[i].smmu_sid; + pcie->sid_info[i].pcie_sid = + pcie->sid_info[i].smmu_sid - smmu_sid_base; + } + + kfree(map); + + return 0; +} + +static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie) +{ + void __iomem *bdf_to_sid_base = pcie->parf + + PCIE20_PARF_BDF_TO_SID_TABLE_N; + u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; + int ret, i; + + ret = qcom_pcie_get_iommu_map(pcie); + if (ret) + return ret; + + if (!pcie->sid_info) + return 0; + + crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); + + /* Registers need to be zero out first */ + memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); + + /* Initial setup for boot */ + for (i = 0; i < pcie->sid_info_len; i++) { + struct qcom_pcie_sid_info_t *sid_info = &pcie->sid_info[i]; + u16 bdf_be = cpu_to_be16(sid_info->bdf); + u32 val; + u8 hash; + + hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), + 0); + + val = readl(bdf_to_sid_base + hash * sizeof(u32)); + + /* If there is a collision, look for next available entry */ + while (val) { + u8 current_hash = hash++; + u8 next_mask = 0xff; + + /* If NEXT field is NULL then update it with next hash */ + if (!(val & next_mask)) { + int j; + + val |= (u32)hash; + writel(val, bdf_to_sid_base + + current_hash * sizeof(u32)); + + /* Look for sid_info of current hash and update it */ + for (j = 0; j < pcie->sid_info_len; j++) { + if (pcie->sid_info[j].hash != + current_hash) + continue; + + pcie->sid_info[j].value = val; + break; + } + } + + val = readl(bdf_to_sid_base + hash * sizeof(u32)); + } + + val = sid_info->bdf << 16 | sid_info->pcie_sid << 8 | 0; + writel(val, bdf_to_sid_base + hash * sizeof(u32)); + + sid_info->hash = hash; + sid_info->value = val; + } + + return 0; +} + static int qcom_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -1290,6 +1421,12 @@ static int qcom_pcie_host_init(struct pcie_port *pp) if (ret) goto err; + if (pcie->ops->config_sid) { + ret = pcie->ops->config_sid(pcie); + if (ret) + goto err; + } + return 0; err: qcom_ep_reset_assert(pcie); @@ -1367,6 +1504,7 @@ static const struct qcom_pcie_ops ops_sm8250 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, .post_deinit = qcom_pcie_post_deinit_2_7_0, + .config_sid = qcom_pcie_config_sid_sm8250, }; static const struct dw_pcie_ops dw_pcie_ops = {