From patchwork Wed Sep 30 07:45:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 313846 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4806773ilg; Wed, 30 Sep 2020 00:46:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkGG5K5+KEjaBgRBSuWrkziL8+L6zlIj63wx6pAXasFyAHMSYVQqIaSIVJTY4dGuEsGmXc X-Received: by 2002:a17:906:c447:: with SMTP id ck7mr1514117ejb.358.1601451969601; Wed, 30 Sep 2020 00:46:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601451969; cv=none; d=google.com; s=arc-20160816; b=O2n3be8Ns9EtbCVcNQB8gSVFj+IjT5jY0H1bAufMmrb9XyjlnwEwPGzNszN7qcqV8m LKEzXpoOadS35XL+tSMuzU4vpzKn+7hGF/0xcmoUFBeiVY2UMfaqi3RA/2ObSk3mnP8+ 4F+lYdm1Pk2pReH2kI+Jykny1ZD/NhG8X1nPzBHIb+xe8AbVKttJqgDja6JI8VN65OK+ p0A/qQHTKMBSbJ28vW/B+Ko3oHBAAe4yTJJrgqwJdh4W5hE3CUscK34eIIIPwm9aroo4 MKJRkGCyB+pH8V/g2J9hlELLUZqDoB6En7jbL1Vyz/kK8HEBaX6GQy5GoY3Db0KBUh8L TcEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=z4PPovzQEANzFGlTucphev3Y2X5Xdtk/9cOGjAz9NEk=; b=Iegv0DKg0krUzg3XPU8L+cu9m5mhbRugQqh5SCh//wEjqGUUyublV4OLGrGZhpAnLd QTdSkSDavSrTVxjp7uVXhMPNlRuLd6OItkn+VlfBbtTB52D3oDNNAZ+1RYEIqmC99u2X yBTgWC7FLoeFfepWpQcTb/rvW5TZbse7vIS0k98enxsIlzV5eLY7hGFXZ3Uz5mAnsWoV 26PdZVfiIFoyuYX6ELpCoQL2vPDZJMWWTG/LrmB3sVOMaIwSROYke08zaMDWqss22rpS 50Cf+rwWNdtg6HITYhfr+f1UlY0XdpEAa+oyxRKH2eLlXlVrHz8jD8aEX0A5Uu189Fug lntg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nKuqftBW; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n17si447164edq.422.2020.09.30.00.46.09; Wed, 30 Sep 2020 00:46:09 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nKuqftBW; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727657AbgI3HqI (ORCPT + 6 others); Wed, 30 Sep 2020 03:46:08 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43332 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725440AbgI3HqI (ORCPT ); Wed, 30 Sep 2020 03:46:08 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08U7jntN129950; Wed, 30 Sep 2020 02:45:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1601451949; bh=z4PPovzQEANzFGlTucphev3Y2X5Xdtk/9cOGjAz9NEk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nKuqftBW8Wodi3LDqr3p/roFj8wLDBXD4ShGB9CazK9cp90SVb4HSgiVObq+lPCw/ pjEsRXWLj+a98xVbsROSmcu0vqKunBN7yZbnl4BrFaox2DPayBrivCHZQBazS56WMp iKxtHHIjegFKaG5e6NG7K2AZMQB4LH7lvIRgke/0= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08U7jnGY037585 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 30 Sep 2020 02:45:49 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 30 Sep 2020 02:45:48 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 30 Sep 2020 02:45:48 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08U7jhDm078449; Wed, 30 Sep 2020 02:45:46 -0500 From: Peter Ujfalusi To: , , , , , , , CC: , , Subject: [PATCH v2 1/2] dt-bindings: irqchip: ti, sci-inta: Update for unmapped event handling Date: Wed, 30 Sep 2020 10:45:58 +0300 Message-ID: <20200930074559.18028-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200930074559.18028-1-peter.ujfalusi@ti.com> References: <20200930074559.18028-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The new DMA architecture introduced with AM64 introduced new event types: unampped events. These events are mapped within INTA in contrast to other K3 devices where the events with similar function was originating from the UDMAP or ringacc. The ti,unmapped-event-sources should contain phandle array to the devices in the system (typically DMA controllers) from where the unmapped events originate. Signed-off-by: Peter Ujfalusi Reviewed-by: Rob Herring --- .../bindings/interrupt-controller/ti,sci-inta.yaml | 5 +++++ 1 file changed, 5 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml index c7cd05656a3e..2837b90bbb56 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml @@ -70,6 +70,11 @@ properties: - description: | "limit" specifies the limit for translation + ti,unmapped-event-sources: + $ref: /schemas/types.yaml#definitions/phandle-array + description: + Array of phandles to DMA controllers where the unmapped events originate. + required: - compatible - reg From patchwork Wed Sep 30 07:45:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 313848 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4808938ilg; Wed, 30 Sep 2020 00:51:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzsZ1hOMZK0xYp2mpiRoD+yM04+k8xfKIfQ1ufstnSCkwadRnt7Bn4lxuhsD7MFw0ta4s4d X-Received: by 2002:aa7:cc8d:: with SMTP id p13mr1435642edt.136.1601452265900; Wed, 30 Sep 2020 00:51:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601452265; cv=none; d=google.com; s=arc-20160816; b=q3XSSYH5ZMkuKHGJjCVNmei212f8po37gEM+pqMpTSd9IYFr+P032mzU6vbrPHLg7y 3wd/DR/eXO1/3aXx5zBD5pP/Z+fqC23i2b52segV9wiw6rNKyJTCPPChisKL8DIcpZde N1p9AU7The6GESIxFS0gRznTbxMX08I+brcAK2SagInc4dfOjtewlsyojCQTabQYfnbl ZX0duplvD97ymHNP3uEmul5FbEM6+RMNGhPn9WXNEADPUoAq5GzgnqfEAvDLOYCXgeQ/ E3CN23TWD/4km3rY1ou1C69hyzkWrSUic8iq6z6GExKrlvdTSPRZYWmsY8cok78O0Cf7 FZxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5qtanVzEh28bAg4VGE9ykZDe066N0zlhLSP+cichi6I=; b=nU5FWwTq80/xD931IJwk2K7xKape8NrGg1OYCm6vkniTLBPf45TwqP6VRS27doBenW eiVUqiAydJWuL2JPm/YhboMNLdb5ebVr7lOAIokipAmpesNHBY+bTAikmX+0O38uA+0O IuaLvYyEU3nnb/dfiijxEb27sAwDxKxHQ1/x0iixY2XNcXoT8VldWxML32bNYGloQGvV dDFscRbyIGDpaneithBmoUD0tE3kcpH4xqlxCptyDeoMeEYT3vlDlGOMsqKEnN/mHc4F ZrULkihffMunxWNVuTSpsz12sm5CX3Sh9tRe2eVCvamOMdQTxWWHGmEjM/bqxfO6lO/d UjkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="u175Yo/s"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r8si516892edw.288.2020.09.30.00.51.05; Wed, 30 Sep 2020 00:51:05 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="u175Yo/s"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728192AbgI3HvF (ORCPT + 6 others); Wed, 30 Sep 2020 03:51:05 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:34294 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728149AbgI3HvF (ORCPT ); Wed, 30 Sep 2020 03:51:05 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08U7jqn2033060; Wed, 30 Sep 2020 02:45:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1601451952; bh=5qtanVzEh28bAg4VGE9ykZDe066N0zlhLSP+cichi6I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=u175Yo/sEOm7/nUdXMgESf64UzD1Hxoij0nf8sFKAbu9RRIWWX1DyEtAMWcDana/9 SB4TyQy9Knl16NP+OcokesecL7KsjKKb3+xU3xhi1gLsH+oGmAVvgciuz5NI8WfB2X qVc5JfbJUUjkuUALxQPCJZLqG9n71M/20/1eUipw= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08U7jqB7094542 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 30 Sep 2020 02:45:52 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 30 Sep 2020 02:45:51 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 30 Sep 2020 02:45:51 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08U7jhDn078449; Wed, 30 Sep 2020 02:45:49 -0500 From: Peter Ujfalusi To: , , , , , , , CC: , , Subject: [PATCH v2 2/2] irqchip/ti-sci-inta: Add support for unmapped event handling Date: Wed, 30 Sep 2020 10:45:59 +0300 Message-ID: <20200930074559.18028-3-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200930074559.18028-1-peter.ujfalusi@ti.com> References: <20200930074559.18028-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The DMA (BCDMA/PKTDMA and their rings/flows) events are under the INTA's supervision as unmapped events in AM64. In order to keep the current SW stack working, the INTA driver must replace the dev_id with it's own when a request comes for BCDMA or PKTDMA resources. Implement parsing of the optional "ti,unmapped-event-sources" phandle array to get the sci-dev-ids of the devices where the unmapped events originate. Signed-off-by: Peter Ujfalusi --- drivers/irqchip/irq-ti-sci-inta.c | 72 +++++++++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 4 deletions(-) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/irqchip/irq-ti-sci-inta.c b/drivers/irqchip/irq-ti-sci-inta.c index bc863ef7998d..00f5b34863c5 100644 --- a/drivers/irqchip/irq-ti-sci-inta.c +++ b/drivers/irqchip/irq-ti-sci-inta.c @@ -85,6 +85,8 @@ struct ti_sci_inta_vint_desc { * @base: Base address of the memory mapped IO registers * @pdev: Pointer to platform device. * @ti_sci_id: TI-SCI device identifier + * @difu_cnt: Number of TI-SCI device identifiers for unmapped events + * @dev_ids_for_unmapped: Pointer to an array of TI-SCI device identifiers */ struct ti_sci_inta_irq_domain { const struct ti_sci_handle *sci; @@ -96,11 +98,33 @@ struct ti_sci_inta_irq_domain { void __iomem *base; struct platform_device *pdev; u32 ti_sci_id; + + int difu_cnt; + u32 *dev_ids_for_unmapped; }; #define to_vint_desc(e, i) container_of(e, struct ti_sci_inta_vint_desc, \ events[i]) +static u16 ti_sci_inta_get_dev_id(struct ti_sci_inta_irq_domain *inta, + u32 hwirq) +{ + u16 dev_id = HWIRQ_TO_DEVID(hwirq); + int i; + + if (inta->difu_cnt == 0) + return dev_id; + + for (i = 0; i < inta->difu_cnt; i++) { + if (dev_id == inta->dev_ids_for_unmapped[i]) { + dev_id = inta->ti_sci_id; + break; + } + } + + return dev_id; +} + /** * ti_sci_inta_irq_handler() - Chained IRQ handler for the vint irqs * @desc: Pointer to irq_desc corresponding to the irq @@ -251,7 +275,7 @@ static struct ti_sci_inta_event_desc *ti_sci_inta_alloc_event(struct ti_sci_inta u16 dev_id, dev_index; int err; - dev_id = HWIRQ_TO_DEVID(hwirq); + dev_id = ti_sci_inta_get_dev_id(inta, hwirq); dev_index = HWIRQ_TO_IRQID(hwirq); event_desc = &vint_desc->events[free_bit]; @@ -352,14 +376,15 @@ static void ti_sci_inta_free_irq(struct ti_sci_inta_event_desc *event_desc, { struct ti_sci_inta_vint_desc *vint_desc; struct ti_sci_inta_irq_domain *inta; + u16 dev_id; vint_desc = to_vint_desc(event_desc, event_desc->vint_bit); inta = vint_desc->domain->host_data; + dev_id = ti_sci_inta_get_dev_id(inta, hwirq); /* free event irq */ mutex_lock(&inta->vint_mutex); inta->sci->ops.rm_irq_ops.free_event_map(inta->sci, - HWIRQ_TO_DEVID(hwirq), - HWIRQ_TO_IRQID(hwirq), + dev_id, HWIRQ_TO_IRQID(hwirq), inta->ti_sci_id, vint_desc->vint_id, event_desc->global_event, @@ -562,7 +587,6 @@ static void ti_sci_inta_msi_set_desc(msi_alloc_info_t *arg, arg->desc = desc; arg->hwirq = TO_HWIRQ(pdev->id, desc->inta.dev_index); } - static struct msi_domain_ops ti_sci_inta_msi_ops = { .set_desc = ti_sci_inta_msi_set_desc, }; @@ -574,6 +598,42 @@ static struct msi_domain_info ti_sci_inta_msi_domain_info = { .chip = &ti_sci_inta_msi_irq_chip, }; +static int ti_sci_inta_get_unmapped_sources(struct ti_sci_inta_irq_domain *inta) +{ + struct device *dev = &inta->pdev->dev; + struct device_node *node = dev_of_node(dev); + struct of_phandle_iterator it; + int count, err, ret, i; + + count = of_count_phandle_with_args(node, "ti,unmapped-event-sources", + NULL); + if (count <= 0) + return 0; + + inta->dev_ids_for_unmapped = devm_kcalloc(dev, count, + sizeof(*inta->dev_ids_for_unmapped), + GFP_KERNEL); + if (!inta->dev_ids_for_unmapped) + return -ENOMEM; + + i = 0; + of_for_each_phandle(&it, err, node, "ti,unmapped-event-sources", + NULL, 0) { + ret = of_property_read_u32(it.node, "ti,sci-dev-id", + &inta->dev_ids_for_unmapped[i++]); + if (ret) { + dev_err(dev, "ti,sci-dev-id read failure for %s\n", + of_node_full_name(it.node)); + of_node_put(it.node); + return ret; + } + } + + inta->difu_cnt = count; + + return 0; +} + static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev) { struct irq_domain *parent_domain, *domain, *msi_domain; @@ -629,6 +689,10 @@ static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev) if (IS_ERR(inta->base)) return PTR_ERR(inta->base); + ret = ti_sci_inta_get_unmapped_sources(inta); + if (ret) + return ret; + domain = irq_domain_add_linear(dev_of_node(dev), ti_sci_get_num_resources(inta->vint), &ti_sci_inta_irq_domain_ops, inta);