From patchwork Wed Sep 30 03:16:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313819 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679514ilg; Tue, 29 Sep 2020 20:18:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxp26qqRa3X8nuY2j8K/Zy3Bi1owCf/hrdx7sM4KjwP1hni43wdlk5qxe+jj5uWUNyB4/OU X-Received: by 2002:aa7:d60f:: with SMTP id c15mr607470edr.102.1601435920938; Tue, 29 Sep 2020 20:18:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435920; cv=none; d=google.com; s=arc-20160816; b=RXd4s4JpNfF0cva2DInyE15CxeClU27tP5mO85sKtpqM7EzIngA88oOp0LmGTBY7lS i0eHWYAzXd5UWKVvwA2fwriA3hG4xHBA/EFsmTVXF+ymh4D3iB7Njl6ud5hk0XSMVXg3 K61aSJdMa4gB0qP/FrubyFTYOLkOO9vH1AwNKvKnA7riokGMnVNn7sHYbiRIEGhSiRC2 y6QdFi2HOYRzVCWDIYPK28SOs6hmRbNrlk0VmNjBxGbRUDJ6Xu2tE2a811ZRvsC+P8zJ kvTW4WbL4YeauLLEGBkJu9ZnzvCh8x6kovll9vwFDOIgDQH1xt2p/Qy8ZgDxpxowNgRs tCVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=lGxpHeEn/39zIIUb3FIE3CjugydFdSOb+TztoLeaWWs=; b=VXPwy/zRlvBeiO3jGQad1WvybtH64CDfZFkM35DRfEBUae1aq7/7akDCQW9/M0xtiZ PeYORbqwgg4oh8N/Itm7F7s1Gn7xAIdDjmVmfiR8KSzka9Vg5pGAoilSlXk7tZ/WfavD Ubyo7yHboWDrsHVzt3G3ALCZ07mloIoLisJesSZEVKNmrS3QbE9CHBwHMjxY4j5swcA5 yccPpdHfi/Y2GRk+B4AVaombpx8YtIaAUOfmCT6HGKlJubyD7eFGG/fRQL6SzmFcczyj JFRp5Egheo7uwl+egGQ1LQXdJsBICFraDhRQ6xndHABYQQhKg3QlhdAPxrKqZztYHRDP h9EA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a8si292590ejv.661.2020.09.29.20.18.40; Tue, 29 Sep 2020 20:18:40 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729859AbgI3DSk (ORCPT + 6 others); Tue, 29 Sep 2020 23:18:40 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14733 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729774AbgI3DSk (ORCPT ); Tue, 29 Sep 2020 23:18:40 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 642DD1A83B73529C7CA1; Wed, 30 Sep 2020 11:18:37 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:28 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 01/17] dt-bindings: mfd: syscon: add some compatible strings for Hisilicon Date: Wed, 30 Sep 2020 11:16:56 +0800 Message-ID: <20200930031712.2365-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add some compatible strings for Hisilicon controllers: hisilicon,hi6220-sramctrl --> Hi6220 SRAM controller hisilicon,pcie-sas-subctrl --> HiP05/HiP06 PCIe-SAS subsystem controller hisilicon,peri-subctrl --> HiP05/HiP06 PERI subsystem controller hisilicon,dsa-subctrl --> HiP05/HiP06 DSA subsystem controller Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/mfd/syscon.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 049ec2ffc7f97e4..fc2e85004d363bf 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -40,7 +40,10 @@ properties: - allwinner,sun50i-a64-system-controller - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep - + - hisilicon,hi6220-sramctrl + - hisilicon,pcie-sas-subctrl + - hisilicon,peri-subctrl + - hisilicon,dsa-subctrl - const: syscon - contains: From patchwork Wed Sep 30 03:16:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313822 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679556ilg; Tue, 29 Sep 2020 20:18:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwUtVHKMI/fo7o6SdAI/DkRl3lLAo2G105bN5g8QrL+Rm0r7jHY/KPoRWseCnDxUTaWmNrW X-Received: by 2002:a17:906:5812:: with SMTP id m18mr801153ejq.204.1601435927431; Tue, 29 Sep 2020 20:18:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435927; cv=none; d=google.com; s=arc-20160816; b=H8BvcnOd9iQ+bO4wyFB59KFopoWlPf8oXo3C7hO7LIBPBs2FiX+kmJdEBJUMU4/1c5 jet2ffIJ9bd2KmRdwrj5w++wY5fa+hQ6TmqJHE6CBF3Ts+Fy0olBpvl9XZPxRiSEw329 S8imWfcrLnI6yJDNd2ZA60qeG3VtamZvUWLm9IdGJYW6hhqiVvIXk9si/j5A4AgT0TL2 47x5nFOcDKnYsY41He7M2D0j3WagtJRClF0K14bpNWZFftgbb7MVOiu1bdvK6fQMjYac +gdEeV2BPvi+fNW5tjGwoymG/3CpWAknvggcSdr4JbK4A8gmhPP3PID8Xme/+2gnCsS/ nA7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=eC6vBFcx0B8FKp7TtWRxVLZF5tfza8kVadEMd87eRTQ=; b=C37KRWGHO/CdzmEGcMqJaoz7lxQBvp+4Qb91wRNEkvcgM6pYiVGCfxZASWehN0NFM2 6QUILL9w6CqoJoVrPPCchW3VQ1JfIoWjrVXOxxljYfpfj2Dnr+5/lOwg3Vt4EXJhcvk+ NEgYPNR4yaEju+7ilRGkIZsAkwqYOifLNqoZ2CE0PSDbsGzjz2Coz+t9wlRs5MBjBlxE 8iVcNlL42Q/lCbQmkRrfY00pCldoNtNW25VrtesP0lUaZsr8g+L2nv8bfzRfYU2uUdkb hUt5WR2kw99cjL2Wg68274gdbve59z88Q/TMQT7SUY6YeYkudLCKozkoGp+ebROqFMEU 398w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dk26si176817edb.60.2020.09.29.20.18.47; Tue, 29 Sep 2020 20:18:47 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729954AbgI3DSq (ORCPT + 6 others); Tue, 29 Sep 2020 23:18:46 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14734 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726327AbgI3DSk (ORCPT ); Tue, 29 Sep 2020 23:18:40 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 68C58BF68D4427185DE4; Wed, 30 Sep 2020 11:18:37 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:29 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 02/17] dt-bindings: arm: hisilicon: delete the descriptions of HiP05/HiP06 controllers Date: Wed, 30 Sep 2020 11:16:57 +0800 Message-ID: <20200930031712.2365-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The compatible strings of Hi6220 SRAM controller, HiP05/HiP06 PCIe-SAS subsystem controller, HiP05/HiP06 PERI subsystem controller and HiP05/HiP06 DSA subsystem controller is in syscon.yaml now. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/hisilicon.txt | 68 ---------------------- 1 file changed, 68 deletions(-) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index a97f643e7d1c760..54f423d87a80a6a 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -186,24 +186,6 @@ Example: #clock-cells = <1>; }; - -Hisilicon Hi6220 SRAM controller - -Required properties: -- compatible : "hisilicon,hi6220-sramctrl", "syscon" -- reg : Register address and size - -Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several -SRAM banks for power management, modem, security, etc. Further, use "syscon" -managing the common sram which can be shared by multiple modules. - -Example: - /*for Hi6220*/ - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; - ----------------------------------------------------------------------- Hisilicon HiP01 system controller @@ -226,56 +208,6 @@ Example: }; ----------------------------------------------------------------------- -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller - -Required properties: -- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; -- reg : Register address and size - -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 PCIe-SAS sub system */ - pcie_sas: system_controller@b0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0xb0000000 0x10000>; - }; - -Hisilicon HiP05/HiP06 PERI sub system controller - -Required properties: -- compatible : "hisilicon,peri-subctrl", "syscon"; -- reg : Register address and size - -The PERI sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. The peripheral -controllers include mdio, ddr, iic, uart, timer and so on. - -Example: - /* for HiP05 sub peri system */ - peri_c_subctrl: syscon@80000000 { - compatible = "hisilicon,peri-subctrl", "syscon"; - reg = <0x0 0x80000000 0x0 0x10000>; - }; - -Hisilicon HiP05/HiP06 DSA sub system controller - -Required properties: -- compatible : "hisilicon,dsa-subctrl", "syscon"; -- reg : Register address and size - -The DSA sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 dsa sub system */ - pcie_sas: system_controller@a0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0xa0000000 0x10000>; - }; - ------------------------------------------------------------------------ Hisilicon CPU controller Required properties: From patchwork Wed Sep 30 03:16:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313834 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679933ilg; Tue, 29 Sep 2020 20:19:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw4PhP5A9U3uzHNWWhcJeqzIMhe2HZci50Py94aozgfQATPCvPmFsDgSgk445AjDpKwLs6o X-Received: by 2002:a50:eb92:: with SMTP id y18mr524606edr.373.1601435983557; Tue, 29 Sep 2020 20:19:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435983; cv=none; d=google.com; s=arc-20160816; b=wRM/+MC+t5CUjYcWGqOQQGOvkHC15EMuWkObY/zBCfL8y/8FWppBlX2pwoRwSPqaVh /3dAxdb1mBWU0jwkVVmq3DiCwmNQQTeLd9FlbfATgTUn3bSxjLjQe2SF2u8xcV18Ieq9 syVWEj91qfqdQ1l8XOkC1XLZlZfguVgYKhzUc4q3ZzX1S40Vt8IZ57q5EumeWFvjrvh4 SEkw6Ndc5LOaX+4H3uqyTy9/HTOcnPZl48wRCVWeWhQLnUdHwwiDbXMVCR40j4K5W+Ry zCS26tGgaqaLtv1WLrMdQ/3SRzS0b3nYEhHQAxgDSDRDLbJaWyIB5mr7m38YiBXqBKsM a5aQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=uaCbgqEUw9Ip5oWiqPmgxUSh5UNkbXGu17Rkigfnl1k=; b=aT+PFchSn+LqJJjgtJr6kpF8GyaheQUQATmZmeK4qlHS/lxGpBWa5/1Rdg61hnMLcg vVF2NEX6r/SmpIgPmp9asCoaKd7JSvBIlzRcb8Dd10FSpPHCr9mexSsETZBv3iKDErZB 6Br7ieAN7HA28NFLt1gUNraJvBRDbk2uYv7uWZQytN8EXUycvKjGuYOcn0TNVkkb5bmV aCUJykvww4JaM74NXTh9+0T3/A3c0rDC+WW4FkLjHW0Nr3zzYWOToHoxXca4ZtWGTzPD 9VNZ1cBGMzR33Ml8fjLksA888HTP6E18hoPpvJLwAQ/IIxiEj9eeokaskEBJ3kWYYVoo NwPg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v25si290031eja.693.2020.09.29.20.19.43; Tue, 29 Sep 2020 20:19:43 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730175AbgI3DTd (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:33 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14736 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729820AbgI3DSl (ORCPT ); Tue, 29 Sep 2020 23:18:41 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 777C860047683712F8EF; Wed, 30 Sep 2020 11:18:37 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:29 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 03/17] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file Date: Wed, 30 Sep 2020 11:16:58 +0800 Message-ID: <20200930031712.2365-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Split the devicetree bindings of each Hisilicon controller from hisilicon.txt into a separate file, the file name is the compatible name attach the .txt file name extension. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 + .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 +++ .../controller/hisilicon,hi6220-aoctrl.txt | 18 ++ .../controller/hisilicon,hi6220-mediactrl.txt | 18 ++ .../controller/hisilicon,hi6220-pmctrl.txt | 18 ++ .../controller/hisilicon,hi6220-sysctrl.txt | 19 ++ .../controller/hisilicon,hip01-sysctrl.txt | 19 ++ .../controller/hisilicon,hip04-bootwrapper.txt | 9 + .../controller/hisilicon,hip04-fabric.txt | 5 + .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 ++ .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 +++ .../bindings/arm/hisilicon/hisilicon.txt | 194 --------------------- 12 files changed, 173 insertions(+), 194 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt new file mode 100644 index 000000000000000..ceffac537671668 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt @@ -0,0 +1,8 @@ +Hisilicon CPU controller + +Required properties: +- compatible : "hisilicon,cpuctrl" +- reg : Register address and size + +The clock registers and power registers of secondary cores are defined +in CPU controller, especially in HIX5HD2 SoC. diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt new file mode 100644 index 000000000000000..0d5282f4670658d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt @@ -0,0 +1,21 @@ +Hisilicon Hi3798CV200 Peripheral Controller + +The Hi3798CV200 Peripheral Controller controls peripherals, queries +their status, and configures some functions of peripherals. + +Required properties: +- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" + and "simple-mfd". +- reg: Register address and size of Peripheral Controller. +- #address-cells: Should be 1. +- #size-cells: Should be 1. + +Examples: + + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt new file mode 100644 index 000000000000000..5a723c1d45f4a17 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Power Always ON domain controller + +Required properties: +- compatible : "hisilicon,hi6220-aoctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power always +on domain for mobile platform. + +Example: + /*for Hi6220*/ + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0x0 0xf7800000 0x0 0x2000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt new file mode 100644 index 000000000000000..dcfdcbcb6455771 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Media domain controller + +Required properties: +- compatible : "hisilicon,hi6220-mediactrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the multimedia +domain(e.g. codec, G3D ...) for mobile platform. + +Example: + /*for Hi6220*/ + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0x0 0xf4410000 0x0 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt new file mode 100644 index 000000000000000..972842f07b5a2ce --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Power Management domain controller + +Required properties: +- compatible : "hisilicon,hi6220-pmctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, some clock registers are define + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power management +domain for mobile platform. + +Example: + /*for Hi6220*/ + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0x0 0xf7032000 0x0 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt new file mode 100644 index 000000000000000..07e318eda254f52 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt @@ -0,0 +1,19 @@ +Hisilicon Hi6220 system controller + +Required properties: +- compatible : "hisilicon,hi6220-sysctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this controller as one of the system controllers, +its main functions are the same as Hisilicon system controller, but +the register offset of some core modules are different. + +Example: + /*for Hi6220*/ + sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt new file mode 100644 index 000000000000000..db2dfdce799db91 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt @@ -0,0 +1,19 @@ +Hisilicon HiP01 system controller + +Required properties: +- compatible : "hisilicon,hip01-sysctrl" +- reg : Register address and size + +The HiP01 system controller is mostly compatible with hisilicon +system controller,but it has some specific control registers for +HIP01 SoC family, such as slave core boot, and also some same +registers located at different offset. + +Example: + + /* for hip01-ca9x2 */ + sysctrl: system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt new file mode 100644 index 000000000000000..b0d53333f4fdae1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt @@ -0,0 +1,9 @@ +Bootwrapper boot method (software protocol on SMP): + +Required Properties: +- compatible: "hisilicon,hip04-bootwrapper"; +- boot-method: Address and size of boot method. + [0]: bootwrapper physical address + [1]: bootwrapper size + [2]: relocation physical address + [3]: relocation size diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt new file mode 100644 index 000000000000000..40453d02f2024bd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt @@ -0,0 +1,5 @@ +Fabric: + +Required Properties: +- compatible: "hisilicon,hip04-fabric"; +- reg: Address and size of Fabric diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt new file mode 100644 index 000000000000000..deec777bc3a850a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt @@ -0,0 +1,13 @@ +PCTRL: Peripheral misc control register + +Required Properties: +- compatible: "hisilicon,pctrl" +- reg: Address and size of pctrl. + +Example: + + /* for Hi3620 */ + pctrl: pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt new file mode 100644 index 000000000000000..963f7f1ca7a2f0c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt @@ -0,0 +1,25 @@ +Hisilicon system controller + +Required properties: +- compatible : "hisilicon,sysctrl" +- reg : Register address and size + +Optional properties: +- smp-offset : offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go +- resume-offset : offset in sysctrl for notifying cpu0 when resume +- reboot-offset : offset in sysctrl for system reboot + +Example: + + /* for Hi3620 */ + sysctrl: system-controller@fc802000 { + compatible = "hisilicon,sysctrl"; + reg = <0xfc802000 0x1000>; + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 54f423d87a80a6a..ffe760a636b5e7f 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -55,197 +55,3 @@ Required root node properties: HiP07 D05 Board Required root node properties: - compatible = "hisilicon,hip07-d05"; - -Hisilicon system controller - -Required properties: -- compatible : "hisilicon,sysctrl" -- reg : Register address and size - -Optional properties: -- smp-offset : offset in sysctrl for notifying slave cpu booting - cpu 1, reg; - cpu 2, reg + 0x4; - cpu 3, reg + 0x8; - If reg value is not zero, cpun exit wfi and go -- resume-offset : offset in sysctrl for notifying cpu0 when resume -- reboot-offset : offset in sysctrl for system reboot - -Example: - - /* for Hi3620 */ - sysctrl: system-controller@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi3798CV200 Peripheral Controller - -The Hi3798CV200 Peripheral Controller controls peripherals, queries -their status, and configures some functions of peripherals. - -Required properties: -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" - and "simple-mfd". -- reg: Register address and size of Peripheral Controller. -- #address-cells: Should be 1. -- #size-cells: Should be 1. - -Examples: - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi6220 system controller - -Required properties: -- compatible : "hisilicon,hi6220-sysctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this controller as one of the system controllers, -its main functions are the same as Hisilicon system controller, but -the register offset of some core modules are different. - -Example: - /*for Hi6220*/ - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Always ON domain controller - -Required properties: -- compatible : "hisilicon,hi6220-aoctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power always -on domain for mobile platform. - -Example: - /*for Hi6220*/ - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Media domain controller - -Required properties: -- compatible : "hisilicon,hi6220-mediactrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the multimedia -domain(e.g. codec, G3D ...) for mobile platform. - -Example: - /*for Hi6220*/ - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Management domain controller - -Required properties: -- compatible : "hisilicon,hi6220-pmctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, some clock registers are define - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power management -domain for mobile platform. - -Example: - /*for Hi6220*/ - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; - ------------------------------------------------------------------------ -Hisilicon HiP01 system controller - -Required properties: -- compatible : "hisilicon,hip01-sysctrl" -- reg : Register address and size - -The HiP01 system controller is mostly compatible with hisilicon -system controller,but it has some specific control registers for -HIP01 SoC family, such as slave core boot, and also some same -registers located at different offset. - -Example: - - /* for hip01-ca9x2 */ - sysctrl: system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. - ------------------------------------------------------------------------ -PCTRL: Peripheral misc control register - -Required Properties: -- compatible: "hisilicon,pctrl" -- reg: Address and size of pctrl. - -Example: - - /* for Hi3620 */ - pctrl: pctrl@fca09000 { - compatible = "hisilicon,pctrl"; - reg = <0xfca09000 0x1000>; - }; - ------------------------------------------------------------------------ -Fabric: - -Required Properties: -- compatible: "hisilicon,hip04-fabric"; -- reg: Address and size of Fabric - ------------------------------------------------------------------------ -Bootwrapper boot method (software protocol on SMP): - -Required Properties: -- compatible: "hisilicon,hip04-bootwrapper"; -- boot-method: Address and size of boot method. - [0]: bootwrapper physical address - [1]: bootwrapper size - [2]: relocation physical address - [3]: relocation size From patchwork Wed Sep 30 03:16:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313821 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679552ilg; Tue, 29 Sep 2020 20:18:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyvWwqOFHbfuEIwaDs37BAHfipdTd/PiutS3kor5jb3kwqhIws7KA8BjKyFNzulbel4+5Vg X-Received: by 2002:a50:fc08:: with SMTP id i8mr556208edr.257.1601435926922; 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[23.128.96.18]) by mx.google.com with ESMTP id dk26si176817edb.60.2020.09.29.20.18.46; Tue, 29 Sep 2020 20:18:46 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729950AbgI3DSp (ORCPT + 6 others); Tue, 29 Sep 2020 23:18:45 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14737 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729708AbgI3DSk (ORCPT ); Tue, 29 Sep 2020 23:18:40 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 80D54233FE635A0C73DA; Wed, 30 Sep 2020 11:18:37 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:30 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 04/17] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema Date: Wed, 30 Sep 2020 11:16:59 +0800 Message-ID: <20200930031712.2365-5-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Hisilicon SoC bindings to DT schema format using json-schema. Signed-off-by: Zhen Lei Reviewed-by: Rob Herring --- .../bindings/arm/hisilicon/hisilicon.txt | 57 -------------------- .../bindings/arm/hisilicon/hisilicon.yaml | 62 ++++++++++++++++++++++ 2 files changed, 62 insertions(+), 57 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt deleted file mode 100644 index ffe760a636b5e7f..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ /dev/null @@ -1,57 +0,0 @@ -Hisilicon Platforms Device Tree Bindings ----------------------------------------------------- -Hi3660 SoC -Required root node properties: - - compatible = "hisilicon,hi3660"; - -HiKey960 Board -Required root node properties: - - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; - -Hi3670 SoC -Required root node properties: - - compatible = "hisilicon,hi3670"; - -HiKey970 Board -Required root node properties: - - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; - -Hi3798cv200 SoC -Required root node properties: - - compatible = "hisilicon,hi3798cv200"; - -Hi3798cv200 Poplar Board -Required root node properties: - - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; - -Hi4511 Board -Required root node properties: - - compatible = "hisilicon,hi3620-hi4511"; - -Hi6220 SoC -Required root node properties: - - compatible = "hisilicon,hi6220"; - -HiKey Board -Required root node properties: - - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; - -HiP01 ca9x2 Board -Required root node properties: - - compatible = "hisilicon,hip01-ca9x2"; - -HiP04 D01 Board -Required root node properties: - - compatible = "hisilicon,hip04-d01"; - -HiP05 D02 Board -Required root node properties: - - compatible = "hisilicon,hip05-d02"; - -HiP06 D03 Board -Required root node properties: - - compatible = "hisilicon,hip06-d03"; - -HiP07 D05 Board -Required root node properties: - - compatible = "hisilicon,hip07-d05"; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml new file mode 100644 index 000000000000000..6d17309c7c84308 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Platforms Device Tree Bindings + +maintainers: + - Wei Xu + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Hi3660 based boards. + items: + - const: hisilicon,hi3660-hikey960 + - const: hisilicon,hi3660 + + - description: Hi3670 based boards. + items: + - const: hisilicon,hi3670-hikey970 + - const: hisilicon,hi3670 + + - description: Hi3798cv200 based boards. + items: + - const: hisilicon,hi3798cv200-poplar + - const: hisilicon,hi3798cv200 + + - description: Hi4511 Board + items: + - const: hisilicon,hi3620-hi4511 + + - description: Hi6220 based boards. + items: + - const: hisilicon,hi6220-hikey + - const: hisilicon,hi6220 + + - description: HiP01 based boards. + items: + - const: hisilicon,hip01-ca9x2 + - const: hisilicon,hip01 + + - description: HiP04 D01 Board + items: + - const: hisilicon,hip04-d01 + + - description: HiP05 D02 Board + items: + - const: hisilicon,hip05-d02 + + - description: HiP06 D03 Board + items: + - const: hisilicon,hip06-d03 + + - description: HiP07 D05 Board + items: + - const: hisilicon,hip07-d05 +... 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[23.128.96.18]) by mx.google.com with ESMTP id t15si177602edw.359.2020.09.29.20.19.17; Tue, 29 Sep 2020 20:19:18 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730104AbgI3DTR (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:17 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14739 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729784AbgI3DSo (ORCPT ); Tue, 29 Sep 2020 23:18:44 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8939C68E6F7F032983E9; Wed, 30 Sep 2020 11:18:37 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:31 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 05/17] dt-bindings: arm: hisilicon: add binding for SD5203 SoC Date: Wed, 30 Sep 2020 11:17:00 +0800 Message-ID: <20200930031712.2365-6-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree binding for Hisilicon SD5203 SoC. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml | 5 +++++ 1 file changed, 5 insertions(+) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml index 6d17309c7c84308..43b8ce2227aaae9 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml @@ -59,4 +59,9 @@ properties: - description: HiP07 D05 Board items: - const: hisilicon,hip07-d05 + + - description: SD5203 based boards + items: + - const: H836ASDJ + - const: hisilicon,sd5203 ... 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[23.128.96.18]) by mx.google.com with ESMTP id v25si290031eja.693.2020.09.29.20.19.43; Tue, 29 Sep 2020 20:19:43 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730168AbgI3DTd (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:33 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14738 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729912AbgI3DSm (ORCPT ); Tue, 29 Sep 2020 23:18:42 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 906BA77D7C058181D1F9; Wed, 30 Sep 2020 11:18:37 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:31 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 06/17] ARM: hisi: add support for SD5203 SoC Date: Wed, 30 Sep 2020 11:17:01 +0800 Message-ID: <20200930031712.2365-7-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Enable support for the Hisilicon SD5203 SoC. The core is ARM926EJ-S. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/mach-hisi/Kconfig | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 1.8.3 diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 3b010fe7c0e9b48..2e980f834a6aa1b 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only config ARCH_HISI bool "Hisilicon SoC Support" - depends on ARCH_MULTI_V7 + depends on ARCH_MULTI_V7 || ARCH_MULTI_V5 select ARM_AMBA - select ARM_GIC + select ARM_GIC if ARCH_MULTI_V7 select ARM_TIMER_SP804 select POWER_RESET select POWER_RESET_HISI @@ -15,6 +15,7 @@ menu "Hisilicon platform type" config ARCH_HI3xxx bool "Hisilicon Hi36xx family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -25,6 +26,7 @@ config ARCH_HI3xxx config ARCH_HIP01 bool "Hisilicon HIP01 family" + depends on ARCH_MULTI_V7 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ARM_GLOBAL_TIMER @@ -33,6 +35,7 @@ config ARCH_HIP01 config ARCH_HIP04 bool "Hisilicon HiP04 Cortex A15 family" + depends on ARCH_MULTI_V7 select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select MCPM if SMP @@ -43,6 +46,7 @@ config ARCH_HIP04 config ARCH_HIX5HD2 bool "Hisilicon X5HD2 family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -50,6 +54,14 @@ config ARCH_HIX5HD2 select PINCTRL_SINGLE help Support for Hisilicon HIX5HD2 SoC family + +config ARCH_SD5203 + bool "Hisilicon SD5203 family" + depends on ARCH_MULTI_V5 + select DW_APB_ICTL + help + Support for Hisilicon SD5203 SoC family + endmenu endif From patchwork Wed Sep 30 03:17:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313825 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679592ilg; Tue, 29 Sep 2020 20:18:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwKY2PugFTzXjv5K+LL1yyGLNvzx100/QtZaiVw82GJev38lBt+J13hiNNtJTU3CAICn+XS X-Received: by 2002:a17:906:edd6:: with SMTP id sb22mr689750ejb.499.1601435935145; Tue, 29 Sep 2020 20:18:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435935; cv=none; d=google.com; s=arc-20160816; b=AsVLsfY18aofZRqFeYbBXfLy7h8zWkvC7o2t73O7Rf5sQ150IxQOKq1ctVSjdI/QRZ CGWUWodc8KZCY5nNejgsm8eM1bsfzLY/bkbDGYftW5n3QMknm+TtdQWvHUgAh00uQTcB DVx3RcckHFkVZfBA1mWWXhZt2SAGPXZYJf/88lqqLhCkOL42ZPJdDvTKVc/jJuCTW1hZ unm/PEzdadW0ris/mE5S6gKqvp8uSwN1S1y6i8f0e1455b4R5zwBa5e64l2gB3XYbcss 3Pl6QGuiQZaPDFlpJqpo2cwuq1XuuwBo0Drum6rD7s2FKOLVKUE4BZgXX912LcaXJt1a XPNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=vBY6HV1Qej/RJ01qRTL+9wLFWIqsKm76YvTE5EBi5y0=; b=hZ/nsO1d3QkjTCLBwD+J+ZMZfRo0uS+YHPWzFNzSvOhk2elADM1thijFThkof1od0t H8lT6uzGlL8oByLos7rQTK6SP46WgIjtv4EAjGNgnKYasIlcdNPJ2lHPZKMGI+CI3gg5 oXqoyImZDbYOn2iqNFGZ+TdMoWgDPHfbHU9Jp3WmQS5/CBvEgQXF1VXCMaJ+0L14YZF9 3ZoLWmwAENfaYZ1t/ZbxzbcO512Iypy515CWErH5eYgCI/pbr+52lXUg+6vlwcBtuL8i kJftD/KAYB939nSMTfGeWUqaa5Mkvx6ZNwtJM7ssDpMclkyoJe0EGZNfeFCb5F+8m1wy 6n+g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v10si305218ejf.80.2020.09.29.20.18.55; Tue, 29 Sep 2020 20:18:55 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729999AbgI3DSy (ORCPT + 6 others); Tue, 29 Sep 2020 23:18:54 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:35834 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729940AbgI3DSo (ORCPT ); Tue, 29 Sep 2020 23:18:44 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 7538C3D32178250CF0D8; Wed, 30 Sep 2020 11:18:42 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:32 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 07/17] ARM: debug: add UART early console support for SD5203 Date: Wed, 30 Sep 2020 11:17:02 +0800 Message-ID: <20200930031712.2365-8-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Add support of early console for SD5203. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/Kconfig.debug | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) -- 1.8.3 diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 80000a66a4e3549..d27a7764c3bfb46 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1086,6 +1086,14 @@ choice on SA-11x0 UART ports. The kernel will check for the first enabled UART in a sequence 3-1-2. + config DEBUG_SD5203_UART + bool "Hisilicon SD5203 Debug UART" + depends on ARCH_SD5203 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on SD5203 UART. + config DEBUG_SOCFPGA_UART0 depends on ARCH_SOCFPGA bool "Use SOCFPGA UART0 for low-level debug" @@ -1639,6 +1647,7 @@ config DEBUG_UART_PHYS default 0x11006000 if DEBUG_MT6589_UART0 default 0x11009000 if DEBUG_MT8135_UART3 default 0x16000000 if DEBUG_INTEGRATOR + default 0x1600d000 if DEBUG_SD5203_UART default 0x18000300 if DEBUG_BCM_5301X default 0x18000400 if DEBUG_BCM_HR2 default 0x18010000 if DEBUG_SIRFATLAS7_UART0 @@ -1841,7 +1850,7 @@ config DEBUG_UART_VIRT default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1 default 0xfec90000 if DEBUG_RK32_UART2 default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 - default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 + default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART default 0xfed60000 if DEBUG_RK29_UART0 default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 From patchwork Wed Sep 30 03:17:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313824 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679586ilg; Tue, 29 Sep 2020 20:18:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzgLthWo6WdcG6ZWtNTQ0+VU4mjpwy+7Q+pG7kYVQvRtQg3ysoUui1cGD+OiEDrzPTimzIU X-Received: by 2002:a17:906:6855:: with SMTP id a21mr193858ejs.289.1601435934743; Tue, 29 Sep 2020 20:18:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435934; cv=none; d=google.com; s=arc-20160816; b=dY7HlgQkuCXPzmrxWBpbO0nr3Upi+VB9NYPrsT6nKyHpOJMuwz9G10CtLA7sw2I68i 391PwjUPUkSnKpN/oDIqvyDBV5GwDRKYhkHLb2ZVoq0mmxLX34txfvhBwxZOR3HDmL+I k+S00PgYddK+sQEq8+Q0QK2LARJpw/ZLMNgSeBFORtfQc6tdksu0QJ7pIxc5eT7FeEeK VwT4roeS1zLtJrSXk0IeG35iNfM3YSmSlZmnYYtV2hIoTwjFnbQc7/2UWFumgm4FL+r8 C8nm9YtTg+BfkrVR/DyIhuf8HtyJC24Ju+9b/dOqOLIZXTGoApbusee28JGf0YcJq1on B4Qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=qaTY6Bs1ej95bN4jlVHPRiwBRGFpx3xoNkvxROLgOlw=; b=VzVzNE96gkitgmVg2LvN/PDBiqBfb6JDCxzSwmPN/DgQbL8945oGfrMeOjwtE7vov7 GLa81EKs0ZbBd2iNsGJaR7G4LOXva0CgtUmjh9vk8B7pEwEY8Ap4i7REvZgI5uKTYIWk 4NMZD6UGAtDlwlAE14pWXrzWTFR6Dm8JCss9gc1bM4BOE9Oh5nbCQaB5G3usFLWNpGTK jGnG+dFtGuv2W63CQsxHcGxWVXWt0cjUppRQDv1swQ6XpE78wgB1GxrWDKYF5EaXzBWO Y73GgKR91QuzvcpWl9OM22PxSuJylr9vDZCdVGDDYKTnH/Xj5jWeL3s63NcFfqLXJFoX Buww== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v10si305218ejf.80.2020.09.29.20.18.54; Tue, 29 Sep 2020 20:18:54 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729995AbgI3DSx (ORCPT + 6 others); Tue, 29 Sep 2020 23:18:53 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:35812 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729941AbgI3DSo (ORCPT ); Tue, 29 Sep 2020 23:18:44 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 6F600B744AEFEB29BC7D; Wed, 30 Sep 2020 11:18:42 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:33 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 08/17] ARM: dts: add SD5203 dts Date: Wed, 30 Sep 2020 11:17:03 +0800 Message-ID: <20200930031712.2365-9-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Add sd5203.dts for Hisilicon SD5203 SoC platform. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sd5203.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 arch/arm/boot/dts/sd5203.dts -- 1.8.3 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae302..1d1262df5c55907 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \ mps2-an399.dtb dtb-$(CONFIG_ARCH_MOXART) += \ moxart-uc7112lx.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb dtb-$(CONFIG_SOC_IMX1) += \ imx1-ads.dtb \ imx1-apf9328.dtb diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts new file mode 100644 index 000000000000000..3cc9a23910be62e --- /dev/null +++ b/arch/arm/boot/dts/sd5203.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 Hisilicon Limited. + * + * DTS file for Hisilicon SD5203 Board + */ + +/dts-v1/; + +/ { + model = "Hisilicon SD5203"; + compatible = "H836ASDJ", "hisilicon,sd5203"; + interrupt-parent = <&vic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + }; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + refclk125mhz: refclk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + timer0: timer@16002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16002000 0x1000>; + interrupts = <4>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + timer1: timer@16003000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16003000 0x1000>; + interrupts = <5>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + uart0: serial@1600d000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600d000 0x1000>; + bus_id = "uart0"; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <17>; + }; + + uart1: serial@1600c000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600c000 0x1000>; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <16>; + status = "disabled"; + }; + }; +}; From patchwork Wed Sep 30 03:17:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313836 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679950ilg; Tue, 29 Sep 2020 20:19:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzTq21l37MLa13jxACjVl3d4KlO05VfaXtuq8OAa+YpcOzKTgIKdVyhHC+2zaV8xs/Vt3NR X-Received: by 2002:aa7:da0f:: with SMTP id r15mr525736eds.321.1601435985356; Tue, 29 Sep 2020 20:19:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435985; cv=none; d=google.com; s=arc-20160816; b=GAgaEblQw3Su6oP62pxWZO2CMeW9BPbeY6XTpkHdjazN2MCcoaXir9V2nUhVwetiU0 QqjD0R+/PrZkZmX1GBieOgwBmLRbgS6hSEJBfPpZcX9PUt9excdUQh09MxcntkxuxL3h v2HafNPdxe/l4mK/sMiuCzTpo18EAGsJJp5CDTVcvCFh4loMyPVGxW6SFjU/Q1VdAuqV ErDgQkinyfnpd5a8JKeI9rV8QrJ65Tc/rbQ8NUnYWNDOhEgmLJdz4ufQpfEorpl2GE3F 01Z0IUsnq3i9PanlO31QQ8GVXec4+F3U+m0OTjp/yCHXjFCm+l4jbV373mEj/tElhLTI nCDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=5sZsuZ0eEN7C+b/Jr7fHPBnNkpaPIktSR6AnyqkRnIM=; b=Hj5JZUfKlaJt4zxqQleRF3AbwsJtX5iupl5li6jHEn2nxdJqnu7D32m9DIVxbd6XP0 cmXDyaiVnxNJo+jNxQqgglaMguTDmVVDG+wkpyHM63tVF6WOMwpbk9pCg8wB5p0SRLSs pSK4JxjrcSMHHC8BpgUedgkE33F2D5wPV01G2+kCMfxMh4/XE5bYJ7cOQbqFQ8sgl03s +Cdn9TillgUdFKCavd+Qnob9jMgcv9TabLnL4bxH9S6/AWB9S1V0GLbFTlW6JXQBbrFW TlQmQ+vmFcVb7/0Di7HgHdpPuzu1vDscT361FbaWHLG59H5Q80E845JLjNDscRrDEJdF tswA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v25si290031eja.693.2020.09.29.20.19.45; Tue, 29 Sep 2020 20:19:45 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729784AbgI3DTd (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:33 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:53790 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729943AbgI3DSo (ORCPT ); Tue, 29 Sep 2020 23:18:44 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 9C863DB33977C52F6BA2; Wed, 30 Sep 2020 11:18:42 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:33 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 09/17] ARM: dts: hisilicon: fix ststem controller compatible node Date: Wed, 30 Sep 2020 11:17:04 +0800 Message-ID: <20200930031712.2365-10-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The DT binding for Hisilicon system controllers requires to have a "syscon" compatible string. Signed-off-by: Zhen Lei --- arch/arm/boot/dts/hi3620.dtsi | 2 +- arch/arm/boot/dts/hip04.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 1.8.3 diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 355175b25fd6220..f683440ee5694b4 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -89,7 +89,7 @@ }; sysctrl: system-controller@802000 { - compatible = "hisilicon,sysctrl"; + compatible = "hisilicon,sysctrl", "syscon"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x802000 0x1000>; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index f5871b1d1ec452c..555bc6b6720fc94 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -213,7 +213,7 @@ }; sysctrl: sysctrl { - compatible = "hisilicon,sysctrl"; + compatible = "hisilicon,sysctrl", "syscon"; reg = <0x3e00000 0x00100000>; }; From patchwork Wed Sep 30 03:17:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313833 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679869ilg; Tue, 29 Sep 2020 20:19:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxychyIH011c08bGMehUxaSkK+MDSWdfbchr+bYqrJfvzl1GCp6K21AI3rvm6CbKb7P3aKS X-Received: by 2002:a05:6402:164d:: with SMTP id s13mr576109edx.222.1601435972835; Tue, 29 Sep 2020 20:19:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435972; cv=none; d=google.com; s=arc-20160816; b=Ao9nGSuze67WqDAxJT21KZLtJIAKhVb9MsphCgt69LRDABmpnLmRJl6KFK2779QHBb n7/wZTVHkDaJgAgvdx4s+TAl7PX3Ak63O4002/0Yz7gPJ7znPh2Y+YNvl2IBs9eHWNIp LSHrUIzjV03HGEd+vsrYbdubIFQ5UXIVG9sbXVxtgj7Pf61XQwSbHu2HMbKdP6y3emQw GSgApZYB0A/TCzAN5//Xz3lnDAxN6272qmVMjHHYsZRm6v+0zJ5XEAUq98JjsJuFR3cG wuhuZVp1XSAAkHmMm7h6h35JVmGDhWxiAgP5us10shJhNH6L0Bgi8ol3MyholFYXUnTc t3WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=mIxCYQ/A/Mzd4b1DNt9K1j4tCby8c8nGq4hcB8AET5o=; b=aPqfYxR1fAxJJI47x9ReKzMwQDMnoDoS3x0OHaG4D/U6mnEGLLIav/ng5G2ZmciIdo +RQq2SOv85kRBQ0URfgOvhNnr3ppervgTi0wc53jledGZW0lK9RUgx5v2alOzzeaSMw6 gsRNoSE1yPYdNitSGrvkamfT6UfDnfLsgHlCzh9Y6RpN4i3OdcxsiZz4TIN0pJA2HCCK A0HSaClopvVI+DYU8jbU3+w8iicf6+M6RezTzm3eEM1Hve9TGS8uctNSjMHV9LoJUCqX YRsg6KqdiknoQZ97+vH4bl+4NR7MYiyvFYb+XLE2Mw+Q637IzvA1RTTc8XDQWW09Fg3Q dlhQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bu5si298653ejb.750.2020.09.29.20.19.32; Tue, 29 Sep 2020 20:19:32 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730099AbgI3DTQ (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:16 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:35840 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729936AbgI3DSo (ORCPT ); Tue, 29 Sep 2020 23:18:44 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 7A3A73E71788B651D89D; Wed, 30 Sep 2020 11:18:42 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:34 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 10/17] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema Date: Wed, 30 Sep 2020 11:17:05 +0800 Message-ID: <20200930031712.2365-11-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon system controller and its variants binding to DT schema format using json-schema. All of them are grouped into one yaml file, to help users understand differences and avoid repeated descriptions. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-sysctrl.txt | 19 ---- .../controller/hisilicon,hip01-sysctrl.txt | 19 ---- .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 ----- .../bindings/arm/hisilicon/controller/sysctrl.yaml | 110 +++++++++++++++++++++ .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 --- 5 files changed, 110 insertions(+), 77 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt deleted file mode 100644 index 07e318eda254f52..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt +++ /dev/null @@ -1,19 +0,0 @@ -Hisilicon Hi6220 system controller - -Required properties: -- compatible : "hisilicon,hi6220-sysctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this controller as one of the system controllers, -its main functions are the same as Hisilicon system controller, but -the register offset of some core modules are different. - -Example: - /*for Hi6220*/ - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt deleted file mode 100644 index db2dfdce799db91..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt +++ /dev/null @@ -1,19 +0,0 @@ -Hisilicon HiP01 system controller - -Required properties: -- compatible : "hisilicon,hip01-sysctrl" -- reg : Register address and size - -The HiP01 system controller is mostly compatible with hisilicon -system controller,but it has some specific control registers for -HIP01 SoC family, such as slave core boot, and also some same -registers located at different offset. - -Example: - - /* for hip01-ca9x2 */ - sysctrl: system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt deleted file mode 100644 index 963f7f1ca7a2f0c..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt +++ /dev/null @@ -1,25 +0,0 @@ -Hisilicon system controller - -Required properties: -- compatible : "hisilicon,sysctrl" -- reg : Register address and size - -Optional properties: -- smp-offset : offset in sysctrl for notifying slave cpu booting - cpu 1, reg; - cpu 2, reg + 0x4; - cpu 3, reg + 0x8; - If reg value is not zero, cpun exit wfi and go -- resume-offset : offset in sysctrl for notifying cpu0 when resume -- reboot-offset : offset in sysctrl for system reboot - -Example: - - /* for Hi3620 */ - sysctrl: system-controller@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml new file mode 100644 index 000000000000000..449140f89ddbc3b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon system controller + +maintainers: + - Wei Xu + +description: | + The Hisilicon system controller is used on many Hisilicon boards, it can be + used to assist the slave core startup, reboot the system, etc. + + There are some variants of the Hisilicon system controller, such as HiP01, + Hi3519, Hi6220 system controller, each of them is mostly compatible with the + Hisilicon system controller, but some same registers located at different + offset. In addition, the HiP01 system controller has some specific control + registers for HIP01 SoC family, such as slave core boot. + + The compatible names of each system controller are as follows: + Hisilicon system controller --> hisilicon,sysctrl + HiP01 system controller --> hisilicon,hip01-sysctrl + Hi6220 system controller --> hisilicon,hi6220-sysctrl + Hi3519 system controller --> hisilicon,hi3519-sysctrl + +allOf: + - if: + properties: + compatible: + contains: + const: hisilicon,hi6220-sysctrl + then: + required: + - '#clock-cells' + +properties: + compatible: + oneOf: + - items: + - enum: + - hisilicon,sysctrl + - hisilicon,hi6220-sysctrl + - hisilicon,hi3519-sysctrl + - const: syscon + - items: + - const: hisilicon,hip01-sysctrl + - const: hisilicon,sysctrl + + reg: + maxItems: 1 + + smp-offset: + description: | + offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go + $ref: /schemas/types.yaml#/definitions/uint32 + + resume-offset: + description: offset in sysctrl for notifying cpu0 when resume + $ref: /schemas/types.yaml#/definitions/uint32 + + reboot-offset: + description: offset in sysctrl for system reboot + $ref: /schemas/types.yaml#/definitions/uint32 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + /* Hisilicon system controller */ + system-controller@fc802000 { + compatible = "hisilicon,sysctrl", "syscon"; + reg = <0xfc802000 0x1000>; + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + }; + + /* HiP01 system controller */ + system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; + + /* Hi6220 system controller */ + system-controller@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0xf7030000 0x2000>; + #clock-cells = <1>; + }; + + /* Hi3519 system controller */ + system-controller@12010000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12010000 0x1000>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt deleted file mode 100644 index 8defacc44dd5b9e..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt +++ /dev/null @@ -1,14 +0,0 @@ -* Hisilicon Hi3519 System Controller Block - -This bindings use the following binding: -Documentation/devicetree/bindings/mfd/syscon.yaml - -Required properties: -- compatible: "hisilicon,hi3519-sysctrl". -- reg: the register region of this block - -Examples: -sysctrl: system-controller@12010000 { - compatible = "hisilicon,hi3519-sysctrl", "syscon"; - reg = <0x12010000 0x1000>; -}; From patchwork Wed Sep 30 03:17:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313823 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679581ilg; Tue, 29 Sep 2020 20:18:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMiKf2CrvBnF3JNkhPpdAP+wb1ximnj6Eup6hLw8sU24rytOw1y/exEdlkQwNFt76wXo29 X-Received: by 2002:a05:6402:17b1:: with SMTP id j17mr540369edy.253.1601435934363; Tue, 29 Sep 2020 20:18:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435934; cv=none; d=google.com; s=arc-20160816; b=Ypr8W2iyMMKYvMGbZiGpFCbj6LM4iA35HFKqG9NzyC08NQgAiqVviX8hKTazdAkc4y qmrnRbjxP2mt8hwNDeY8C5dGaiMuUtJBlqRR89RnEf5qmWk3atfKPSFscY66t+MtDPFJ sFfUbK4E79wdScTtLh5CxGYUuqS1hPFCZUYkatYXFYtsXpgTZthL7jVDl9IophgYxMpq O8Ph+W3Glt0OpmNBYe973A/NB+eX0kmrtd0iXE8RYRyaoUVuWxCTAeVirv7OgXOjET/S SOdGBcebHSW54bdnR9V4n9RK7IREv1SpieBAJ+b0aFcu0K55G2a7KqWpid2zdQNRIwfp ae7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=/cv5Td9YxBdozN2S0gO++Jvx9Jpl+/Nk9vHDJR9ZQk8=; b=P8v/hT16mh//fJPXl1fwzC18FU8bEr7cVJlj+x74DRs4SDfvypqwb/L5B5gPk9Z8Zb qk45bhEPUTzS93lBrv6d9i75ygAUfrKaRw3mJQCQKl6zUNfFgvmjruHzz4FJpXUC42jx QfJemuE80n1esmglKVRkISU5cDEv3aXQulF8nNvuOEWxnf7pHC84GCAOvWQA4vWtGjxJ nyHOkBwMSLNjRg03vXBdeaElamaWpYATtu2HdNlhEJTAM1E7W8oHtUtSzJ07ruxWLKMu GLar8uGcCkj11l3tdG5ncZJletE/lF3Bv13vHvrIgP4MkRUVExjQIqpdr7tP2fc53D/s WrDA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v10si305218ejf.80.2020.09.29.20.18.54; Tue, 29 Sep 2020 20:18:54 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729992AbgI3DSx (ORCPT + 6 others); Tue, 29 Sep 2020 23:18:53 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:53798 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729945AbgI3DSo (ORCPT ); Tue, 29 Sep 2020 23:18:44 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A0F9A8FB9F7044AB98F9; Wed, 30 Sep 2020 11:18:42 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:35 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 11/17] dt-bindings: arm: hisilicon: convert hisilicon, cpuctrl bindings to json-schema Date: Wed, 30 Sep 2020 11:17:06 +0800 Message-ID: <20200930031712.2365-12-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon CPU controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/controller/cpuctrl.yaml | 29 ++++++++++++++++++++++ .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 ------ 2 files changed, 29 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml new file mode 100644 index 000000000000000..f6a314db3a59416 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon CPU controller + +maintainers: + - Wei Xu + +description: | + The clock registers and power registers of secondary cores are defined + in CPU controller, especially in HIX5HD2 SoC. + +properties: + compatible: + items: + - const: hisilicon,cpuctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt deleted file mode 100644 index ceffac537671668..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt +++ /dev/null @@ -1,8 +0,0 @@ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. From patchwork Wed Sep 30 03:17:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313830 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679759ilg; Tue, 29 Sep 2020 20:19:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyyMuhdgos+pnOZLGTvq2+hK5IajaVMt1GMG7BCNjiGdwkH0CFuP3kyA/ZeDuJTDONnJ8bk X-Received: by 2002:a05:6402:1451:: with SMTP id d17mr596853edx.48.1601435956872; Tue, 29 Sep 2020 20:19:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435956; cv=none; d=google.com; s=arc-20160816; b=jK7OMK1AMtvisLbA6qXq9Dx0sVqMQ3ddpYZc16fbIL+AtmJ3cQuWFHJDrLYBE7XerN Hm+60AqR3PdL0ErUN98eHmz15ZqsOHKUBMxbXZB1QLxdpqPqFOWstUS3k+vWlFRycgcn iqCq5AhEqfmmIK5Hyqh5ZYrmPWzlr8FdHcBt3aOyj/EP8tWCl3mbTS4rmSsVjjS0CCVw GtDif5jbVheFPiMGZRxAflNqUyYNiuy3A+PPt4o7ibSm9tRbTW/PW4M2yq3dGq3sc1Y8 eT47D8fQewvgqn2sKTwu+72AGrTWFyzoHnNyfwFRmnLULsqEU0spjYakyfQl++aKD6uP nk2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=5+dwH/msMvhogBWDQzoJzNBmasxnGtduDjDoYNaHa3A=; b=VmIateCpJAGJXodWxvXvAiaCL4OthpbxFFbPG4mYO/hopRSzPRlFocWpV4LxoKBNQ1 I9QVAEKrzXhbVqZly0pLZX+jJCmGWqTychPkHzVRTYgFMy08kr9HPw5jf5m85WodOyJG qRH/XR9ChwzUNNX3ZDA0mud9PUgaNBeAV/jGa9spdnul7E4TRRgEqoIMnMekc5MJcnv1 xSuqHPjNbzv/7vFUkQ/C/kPGRVg0tQU45IDcZtLAdWeXuC6y65FV/FDrHjdRCxnYvpBz V5/UBC9eZfYypDqmMWZs4x1uL1eSUOT369IPnlSZvqdG5W0dfh7TVfcvMXZJpbIPoHJh ukoQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t15si177602edw.359.2020.09.29.20.19.16; Tue, 29 Sep 2020 20:19:16 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730089AbgI3DTP (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:15 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:35792 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729937AbgI3DSo (ORCPT ); Tue, 29 Sep 2020 23:18:44 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 65BCD5E9BF5BD5CF3954; Wed, 30 Sep 2020 11:18:42 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:35 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 12/17] dt-bindings: arm: hisilicon: convert hisilicon, pctrl bindings to json-schema Date: Wed, 30 Sep 2020 11:17:07 +0800 Message-ID: <20200930031712.2365-13-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon peripheral misc control register binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 --------- .../bindings/arm/hisilicon/controller/pctrl.yaml | 34 ++++++++++++++++++++++ 2 files changed, 34 insertions(+), 13 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt deleted file mode 100644 index deec777bc3a850a..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt +++ /dev/null @@ -1,13 +0,0 @@ -PCTRL: Peripheral misc control register - -Required Properties: -- compatible: "hisilicon,pctrl" -- reg: Address and size of pctrl. - -Example: - - /* for Hi3620 */ - pctrl: pctrl@fca09000 { - compatible = "hisilicon,pctrl"; - reg = <0xfca09000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml new file mode 100644 index 000000000000000..6d50658728092cf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/pctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral misc control register + +maintainers: + - Wei Xu + +description: Peripheral misc control register + +properties: + compatible: + items: + - const: hisilicon,pctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id t15si177602edw.359.2020.09.29.20.19.17; Tue, 29 Sep 2020 20:19:17 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730095AbgI3DTQ (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:16 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:53766 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729949AbgI3DSo (ORCPT ); Tue, 29 Sep 2020 23:18:44 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 97687ADA38F6F5B3BA6F; Wed, 30 Sep 2020 11:18:42 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:36 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 13/17] dt-bindings: arm: hisilicon: convert hisilicon, hip04-fabric bindings to json-schema Date: Wed, 30 Sep 2020 11:17:08 +0800 Message-ID: <20200930031712.2365-14-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Fabric controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hip04-fabric.yaml | 27 ++++++++++++++++++++++ .../controller/hisilicon,hip04-fabric.txt | 5 ---- 2 files changed, 27 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml new file mode 100644 index 000000000000000..60c516a04ad58b3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hip04-fabric.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Fabric controller + +maintainers: + - Wei Xu + +description: Hisilicon Fabric controller + +properties: + compatible: + items: + - const: hisilicon,hip04-fabric + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt deleted file mode 100644 index 40453d02f2024bd..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt +++ /dev/null @@ -1,5 +0,0 @@ -Fabric: - -Required Properties: -- compatible: "hisilicon,hip04-fabric"; -- reg: Address and size of Fabric From patchwork Wed Sep 30 03:17:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313827 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679738ilg; Tue, 29 Sep 2020 20:19:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwduyo49M5OVyzYlJHpuztEvYUNx7L+3w/dtC7C9pDDqUg5agjtXQN27n6L1XmLSi7KYPqN X-Received: by 2002:aa7:d353:: with SMTP id m19mr524002edr.275.1601435954849; Tue, 29 Sep 2020 20:19:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435954; cv=none; d=google.com; s=arc-20160816; b=XouxvBNZp055rDSxkbjlE1msSwp5E64T9pfHAQr6eHSyx76R5pD5YURGDO073fP7pT ZzEcZwjXC4RUzj5TB+2EBiEa4PqKx9mCDXjLwgA0CuobE4gotewEN5MqB5+szDQH4Cmi 8HDWhjQr/tD+YzmXYzIkhI/v8e+roqqZJ7aA8b8UN8Xl+I2nVA3IzEw/DQvZvyEOklLP azAC3K6tZDmYAezc7BhWKqlBcGP2bgRxF61JzHSsylUZaTVdIRCSip+sEU4ZvBugIedK 1l3U7o40Z8NDY5CTlSUQTKv5vPqNdPtIiqTVwOGnCx5EfENaLIXSsdFvGv32FqDkztPj OSeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=lJ3bXXqfe3I1hiw0+bHQDdIw/7V+0wrc7YA1Fllkcuk=; b=h9ebKZnqyOp7J4ZnEUXElvSZxdO8n5/B7Yysv3lHUJDNqNywm1nKh2ecfyqWha/LPu eXF0/kzYDLGgDw09rFCq8v5gVfv1zAEKD3gBtAZk+H3HFBr75bg2sytu9VbaleWcFKDP 92COYaWKBv/j8w32YlbEhhSvXH47LPoCh1pYKfOGeum820lWkgqC5HqwZc7/EVmLh8v+ rD3CDiQrEtsqtLd6CTw4mNrWmYOljfEFCHVomMqU8oA9JThKMUCvbbxvcbEQfswZF3FI GfENOf6MzrvgWnQTkXY+wN7CgAa00SJnn1etYLxKxqpOcx4/apX8l+1UQWY9idtXHWfy QePA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t15si177602edw.359.2020.09.29.20.19.14; Tue, 29 Sep 2020 20:19:14 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730041AbgI3DTE (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:04 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14785 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729975AbgI3DSu (ORCPT ); Tue, 29 Sep 2020 23:18:50 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 81EC8FBDFAFE854B2EA5; Wed, 30 Sep 2020 11:18:47 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:36 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 14/17] dt-bindings: arm: hisilicon: convert hisilicon, hip04-bootwrapper bindings to json-schema Date: Wed, 30 Sep 2020 11:17:09 +0800 Message-ID: <20200930031712.2365-15-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Bootwrapper boot method binding to DT schema format using json-schema. The property boot-method contains two groups of physical address range information: bootwrapper and relocation. The "uint32-array" type is not suitable for it, because the field "address" and "size" may occupy one or two cells respectively. Use "minItems: 1" and "maxItems: 2" to allow it can be written in "" or ", " format. Signed-off-by: Zhen Lei --- .../hisilicon/controller/hip04-bootwrapper.yaml | 34 ++++++++++++++++++++++ .../controller/hisilicon,hip04-bootwrapper.txt | 9 ------ 2 files changed, 34 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml new file mode 100644 index 000000000000000..7378159e61df998 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hip04-bootwrapper.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bootwrapper boot method + +maintainers: + - Wei Xu + +description: Bootwrapper boot method (software protocol on SMP) + +properties: + compatible: + items: + - const: hisilicon,hip04-bootwrapper + + boot-method: + description: | + Address and size of boot method. + [0]: bootwrapper physical address + [1]: bootwrapper size + [2]: relocation physical address + [3]: relocation size + minItems: 1 + maxItems: 2 + +required: + - compatible + - boot-method + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt deleted file mode 100644 index b0d53333f4fdae1..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt +++ /dev/null @@ -1,9 +0,0 @@ -Bootwrapper boot method (software protocol on SMP): - -Required Properties: -- compatible: "hisilicon,hip04-bootwrapper"; -- boot-method: Address and size of boot method. - [0]: bootwrapper physical address - [1]: bootwrapper size - [2]: relocation physical address - [3]: relocation size From patchwork Wed Sep 30 03:17:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313828 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679748ilg; Tue, 29 Sep 2020 20:19:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzzXfn7NDfKYdXYWkDi8HSqgEfC9tIYVz7p6GUAH7qJdMn6x5XNQMxw4KMYBYsMCOi4Xata X-Received: by 2002:a17:906:4f8d:: with SMTP id o13mr755960eju.20.1601435955624; Tue, 29 Sep 2020 20:19:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435955; cv=none; d=google.com; s=arc-20160816; b=AWt73Nh1JHxyYvMNPUbE1J4St2uIbmRWRGpfUVIoJm1DtahOws5fL+ERwyCyecH5GE hvaqAUaxeJoohGx9f5hxoD3ltJnhQtbinvPdaUMCmo/D0B0ETtnmEHrEyJjvZGMFv4Im U6fVHYvLY9yKLJBbtRq1m4e6QboHFitUqm8Md5e+XmYIo/rGqP2pCimKGUpA5Q/crXi0 92fdcZpbx4afdT/ogd6gklZzoDSTGXt7aRba7Hh2KXGHZpeJiPV1evo1HTEelM03p0H9 qVLPPYQi+Tz+SvwjETXWD2MLPLFMM/BYbLlLQJ8iD46RzpX3o63gg34/b2rEqCw5zZGW JEjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=rxYasr1RL+3ttnb/cRVA5+VKEMgvTR9hagKzO5zwUdM=; b=BX+80cM102tTINAhj2BUKXKDC/IdGyL/9MxkdRNviFNY/eT2x95FnuPgdSDHZG3JCq TetjTgf3gGjHNivxs7XRma/h0g7QEf9sbqf8opDr1BiDnEYXhLh3GEjCmqXdVzXIkp9I Lnugugs3UmlOe128DEwfOnWITN6fx7uG1A+mVRJYuCp3qnBXbZWRjVAr+ibMVy0cOn1h +fhBIWHPREXnRTRYAVJHK5IegB3u2mefWlGH7VTcr8fSRttJnm2c7ei8mD5yuFr2NA4Q KK2B7arDjVbKKl5Wzxu8TVEGXIFkQttp2aOM8pl+TWWlIA6UxZiWoDyn++eFf2dN8hIZ elkg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t15si177602edw.359.2020.09.29.20.19.15; Tue, 29 Sep 2020 20:19:15 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729940AbgI3DTE (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:04 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14786 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729976AbgI3DSu (ORCPT ); Tue, 29 Sep 2020 23:18:50 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 87147261CA98E68529DC; Wed, 30 Sep 2020 11:18:47 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:37 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 15/17] dt-bindings: arm: hisilicon: convert Hi6220 domain controller bindings to json-schema Date: Wed, 30 Sep 2020 11:17:10 +0800 Message-ID: <20200930031712.2365-16-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 domain controllers binding to DT schema format using json-schema. All of them are grouped into one yaml file, to help users understand differences and avoid repeated descriptions. Signed-off-by: Zhen Lei --- .../hisilicon/controller/hi6220-domain-ctrl.yaml | 68 ++++++++++++++++++++++ .../controller/hisilicon,hi6220-aoctrl.txt | 18 ------ .../controller/hisilicon,hi6220-mediactrl.txt | 18 ------ .../controller/hisilicon,hi6220-pmctrl.txt | 18 ------ 4 files changed, 68 insertions(+), 54 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml new file mode 100644 index 000000000000000..6ea6d7ee7a14f0a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi6220-domain-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 domain controller + +maintainers: + - Wei Xu + +description: | + Hisilicon designs some special domain controllers for mobile platform, + such as: the power Always On domain controller, the Media domain + controller(e.g. codec, G3D ...) and the Power Management domain + controller. + + The compatible names of each domain controller are as follows: + Power Always ON domain controller --> hisilicon,hi6220-aoctrl + Media domain controller --> hisilicon,hi6220-mediactrl + Power Management domain controller --> hisilicon,hi6220-pmctrl + +properties: + compatible: + items: + - enum: + - hisilicon,hi6220-aoctrl + - hisilicon,hi6220-mediactrl + - hisilicon,hi6220-pmctrl + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0xf7800000 0x2000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0xf4410000 0x1000>; + #clock-cells = <1>; + }; + + pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0xf7032000 0x1000>; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt deleted file mode 100644 index 5a723c1d45f4a17..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Power Always ON domain controller - -Required properties: -- compatible : "hisilicon,hi6220-aoctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power always -on domain for mobile platform. - -Example: - /*for Hi6220*/ - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt deleted file mode 100644 index dcfdcbcb6455771..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Media domain controller - -Required properties: -- compatible : "hisilicon,hi6220-mediactrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the multimedia -domain(e.g. codec, G3D ...) for mobile platform. - -Example: - /*for Hi6220*/ - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt deleted file mode 100644 index 972842f07b5a2ce..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Power Management domain controller - -Required properties: -- compatible : "hisilicon,hi6220-pmctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, some clock registers are define - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power management -domain for mobile platform. - -Example: - /*for Hi6220*/ - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; From patchwork Wed Sep 30 03:17:11 2020 Content-Type: text/plain; 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[23.128.96.18]) by mx.google.com with ESMTP id t15si177602edw.359.2020.09.29.20.19.16; Tue, 29 Sep 2020 20:19:16 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729973AbgI3DTP (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:15 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14787 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729974AbgI3DSt (ORCPT ); Tue, 29 Sep 2020 23:18:49 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8C6A97FC2FD147F1BE3E; Wed, 30 Sep 2020 11:18:47 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:38 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 16/17] dt-bindings: arm: hisilicon: convert hisilicon, hi3798cv200-perictrl bindings to json-schema Date: Wed, 30 Sep 2020 11:17:11 +0800 Message-ID: <20200930031712.2365-17-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../hisilicon/controller/hi3798cv200-perictrl.yaml | 64 ++++++++++++++++++++++ .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ------- 2 files changed, 64 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml new file mode 100644 index 000000000000000..cba1937aad9a8d3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3798cv200-perictrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi3798CV200 Peripheral Controller + +maintainers: + - Wei Xu + +description: | + The Hi3798CV200 Peripheral Controller controls peripherals, queries + their status, and configures some functions of peripherals. + +properties: + compatible: + items: + - const: hisilicon,hi3798cv200-perictrl + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: + type: object + +examples: + - | + peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + phy@850 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x850 0x8>; + #phy-cells = <1>; + clocks = <&crg 42>; + resets = <&crg 0x188 4>; + assigned-clocks = <&crg 42>; + assigned-clock-rates = <100000000>; + hisilicon,fixed-mode = <4>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt deleted file mode 100644 index 0d5282f4670658d..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt +++ /dev/null @@ -1,21 +0,0 @@ -Hisilicon Hi3798CV200 Peripheral Controller - -The Hi3798CV200 Peripheral Controller controls peripherals, queries -their status, and configures some functions of peripherals. - -Required properties: -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" - and "simple-mfd". -- reg: Register address and size of Peripheral Controller. -- #address-cells: Should be 1. -- #size-cells: Should be 1. - -Examples: - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; From patchwork Wed Sep 30 03:17:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313826 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4679662ilg; Tue, 29 Sep 2020 20:19:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz199h3Uh6Ouk6YsctNmBVXEW1NjyZ2mjiz5Lu6BXlL0i7XRwmxsWGV9uQA1PJ44edHwv3o X-Received: by 2002:a17:906:b2ce:: with SMTP id cf14mr742049ejb.352.1601435946121; Tue, 29 Sep 2020 20:19:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601435946; cv=none; d=google.com; s=arc-20160816; b=wXQFiavq6WKc0r/dsmMOScj7BsekptcJA+4sqNCecr+umzy/oXEPBuEggLaEPBSuXr +129d8saoyqmZ6a9dNvdgMMckDXVaXtDuUkirPXJa3vVOyXgFdvh8XiUabZT6vLrVX18 QpPS+Q7oT4WFbnImDhG6goxoOox95jcD5tAtkcr8BG8IUm92LIDdgjUUcfdPYeGaSXFc EnTIqEKwOmAW7wHa0AwEMq/7ozgSK7BmHlA8zkeRZfh8kVq5a19pUs9yXnCCS3zf/Zmp WPpmHXWZDffUoAHmuBpbusn2ZIAqk1rOYiLdtXByH4UH4W7dgGKOb7hiH3u8tpzJ1wr+ kBxA== ARC-Message-Signature: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id y7si182423edw.23.2020.09.29.20.19.05; Tue, 29 Sep 2020 20:19:06 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730044AbgI3DTF (ORCPT + 6 others); Tue, 29 Sep 2020 23:19:05 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14740 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729973AbgI3DSt (ORCPT ); Tue, 29 Sep 2020 23:18:49 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B36B3205B953FF83444C; Wed, 30 Sep 2020 11:18:47 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 11:18:38 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v6 17/17] dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema Date: Wed, 30 Sep 2020 11:17:12 +0800 Message-ID: <20200930031712.2365-18-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------ .../bindings/arm/hisilicon/low-pin-count.yaml | 61 ++++++++++++++++++++++ 2 files changed, 61 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt deleted file mode 100644 index 10bd35f9207f2ee..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hip06 Low Pin Count device - Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which - provides I/O access to some legacy ISA devices. - Hip06 is based on arm64 architecture where there is no I/O space. So, the - I/O ports here are not CPU addresses, and there is no 'ranges' property in - LPC device node. - -Required properties: -- compatible: value should be as follows: - (a) "hisilicon,hip06-lpc" - (b) "hisilicon,hip07-lpc" -- #address-cells: must be 2 which stick to the ISA/EISA binding doc. -- #size-cells: must be 1 which stick to the ISA/EISA binding doc. -- reg: base memory range where the LPC register set is mapped. - -Note: - The node name before '@' must be "isa" to represent the binding stick to the - ISA/EISA binding specification. - -Example: - -isa@a01b0000 { - compatible = "hisilicon,hip06-lpc"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml new file mode 100644 index 000000000000000..3b36e683bb1511d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP06 Low Pin Count device + +maintainers: + - Wei Xu + +description: | + Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which + provides I/O access to some legacy ISA devices. + HiP06 is based on arm64 architecture where there is no I/O space. So, the + I/O ports here are not CPU addresses, and there is no 'ranges' property in + LPC device node. + +properties: + $nodename: + pattern: '^isa@[0-9a-f]+$' + description: | + The node name before '@' must be "isa" to represent the binding stick + to the ISA/EISA binding specification. + + compatible: + enum: + - hisilicon,hip06-lpc + - hisilicon,hip07-lpc + + reg: + maxItems: 1 + + '#address-cells': + const: 2 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + isa@a01b0000 { + compatible = "hisilicon,hip06-lpc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xa01b0000 0x1000>; + + ipmi0: bt@e4 { + compatible = "ipmi-bt"; + device_type = "ipmi"; + reg = <0x01 0xe4 0x04>; + }; + }; +...