From patchwork Tue Sep 29 14:14:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313769 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206873ilg; Tue, 29 Sep 2020 07:16:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzedmM9Aw0AK8+AtkmQHjfFM7O471XSp34ztnSeyLUV3NF/W08RoLSgsbj2WsE5NUqUCnFD X-Received: by 2002:a5d:688b:: with SMTP id h11mr4536838wru.319.1601388982550; Tue, 29 Sep 2020 07:16:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388982; cv=none; d=google.com; s=arc-20160816; b=sGkBrAAiZjRN6andg1ieitLyz51F+6FuKEj5gVZAg0+RQmnxDQkfQQYuvOco9NjSRj YTNayPwniLmhD3pHYuyC0esHWrFKmMoh1c4bmX0KjJplpaLVyKlo/tm+kDvCG8B+3f6b VPa/y6mFNF8mWe5/Q9ZwjwtV0vIkLztv039Vpp8XW/s4Q4K3jNmA5OttfCYz42CTmu6D QBuSCMkBV9qBEHFs/yEP2xQu6XIUx4FwWkZo4G21h7bjbel0HAWBgdvOD5kSha1H5SNA GmIH6oTAdOKOA/+XQ8STTFEdsbIYTFQpfSj+SowamrAS8Ltw1ARSO4CmAII9XeWkXHqZ E4pA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=lGxpHeEn/39zIIUb3FIE3CjugydFdSOb+TztoLeaWWs=; b=xXrhtHUMHtRLUDnoSOBtH2ch1wAdovCGqfKXpKJ+juZZr7qKQzLeoCUD4LZQSsd93N Azh6xz4GY4yBPZWbyxNS38aitV2crmqb4/v/gBo1OSyO4Zf7C5f3fZ9GWRc46X/lZ2nl dkuqmjO1/jJ+aLJEL2MbpgTC9njVvEo/EoF9paic2FYCFYeisl18TMrYqKGclvPk21WW fcNcv2ilzI1sej04izPUSqC1XF8WhbqBw/BWyopmjhJLBBPDNi4gIEpUA4j7MkDp5LsI zz8Y9XI2CU9lrrBvl3PiWUQKmkbD7c7IJ6wyvqxpE9seYFgf+NmuT3WbuSlMNodJRxEi 8mTg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e9si2746312ejt.529.2020.09.29.07.16.22; Tue, 29 Sep 2020 07:16:22 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731373AbgI2OQK (ORCPT + 6 others); Tue, 29 Sep 2020 10:16:10 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14778 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728599AbgI2OPb (ORCPT ); Tue, 29 Sep 2020 10:15:31 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 694F2DF4E77E81DA352A; Tue, 29 Sep 2020 22:15:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:11 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 01/17] dt-bindings: mfd: syscon: add some compatible strings for Hisilicon Date: Tue, 29 Sep 2020 22:14:38 +0800 Message-ID: <20200929141454.2312-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add some compatible strings for Hisilicon controllers: hisilicon,hi6220-sramctrl --> Hi6220 SRAM controller hisilicon,pcie-sas-subctrl --> HiP05/HiP06 PCIe-SAS subsystem controller hisilicon,peri-subctrl --> HiP05/HiP06 PERI subsystem controller hisilicon,dsa-subctrl --> HiP05/HiP06 DSA subsystem controller Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/mfd/syscon.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 049ec2ffc7f97e4..fc2e85004d363bf 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -40,7 +40,10 @@ properties: - allwinner,sun50i-a64-system-controller - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep - + - hisilicon,hi6220-sramctrl + - hisilicon,pcie-sas-subctrl + - hisilicon,peri-subctrl + - hisilicon,dsa-subctrl - const: syscon - contains: From patchwork Tue Sep 29 14:14:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313766 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206626ilg; Tue, 29 Sep 2020 07:16:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxxokmEysPPuchd6G6UZ7mqdK3Wj8hdAHJx5j8wY5A4xsMGNc7Rqvk+RhqytYoQxgZH/Fc3 X-Received: by 2002:a05:6402:64b:: with SMTP id u11mr3300478edx.147.1601388964295; Tue, 29 Sep 2020 07:16:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388964; cv=none; d=google.com; s=arc-20160816; b=wYiZvXchPgoqTA7eWMFk9JsnsPb/iS9ZBmKPTthov93u8DWE478Y47EekMURGM0qWH sRlckKK68R8YLUBj1N2830UQQn5BMFeIgtV9lwKPhFVh2a90UZX/winCkfLDxxwQjV6d /3q3bofoe6rSYPeUsJ1iA9F+eh752tGOxIuh7X0FKwz9PX8Mx1aa39smQexs4BDeP8wv zTxMwDBJFgZl8F5aVPrQFmHT2IwXP//V3FEFlM0j/I3GZnybmTi5ub0gdIVLj/56iwic 17DdSsy3W7JYG/BpJUb05MB4g1a0Uymbuu+7pQ5zZDX/2XUr7gLVP1e6mINH145fSnNv rLUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=eC6vBFcx0B8FKp7TtWRxVLZF5tfza8kVadEMd87eRTQ=; b=h2ubXhc8ul4GUBrPbJ8mWcpbd564rnP0uTsNmAdPxNojV5Ub362KWlEako4Cg4AZul AT4/omXfyF82+WciGci46AW0u9DOyXIetW8mpk9v2v2szjck1Q6mYSIVFVp8ruKr1w1e 4Yv1FO50onYoxExBYjOTu7OKVU5V2cpZ+btNR9pgbuNSdoyz6EV5loBokBYCvHsNrC+L xYN88OGC2uXBWwEcONoj2jekZaewiKFFyJpsMgqpoj0bDSlMLzKiOoEoxyqlACulXxx6 0uIGC6WWOKgARYEM1tR4VDhFbKZ0g3pK5okraUrN28SLTyu21szYA5aT4RGgo9CtfJSo JhNw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p26si2775529ejf.86.2020.09.29.07.16.04; Tue, 29 Sep 2020 07:16:04 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731311AbgI2OQC (ORCPT + 6 others); Tue, 29 Sep 2020 10:16:02 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14777 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728514AbgI2OPd (ORCPT ); Tue, 29 Sep 2020 10:15:33 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 6E1C72BDB9FDB8E4435E; Tue, 29 Sep 2020 22:15:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:12 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 02/17] dt-bindings: arm: hisilicon: delete the descriptions of HiP05/HiP06 controllers Date: Tue, 29 Sep 2020 22:14:39 +0800 Message-ID: <20200929141454.2312-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The compatible strings of Hi6220 SRAM controller, HiP05/HiP06 PCIe-SAS subsystem controller, HiP05/HiP06 PERI subsystem controller and HiP05/HiP06 DSA subsystem controller is in syscon.yaml now. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/hisilicon.txt | 68 ---------------------- 1 file changed, 68 deletions(-) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index a97f643e7d1c760..54f423d87a80a6a 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -186,24 +186,6 @@ Example: #clock-cells = <1>; }; - -Hisilicon Hi6220 SRAM controller - -Required properties: -- compatible : "hisilicon,hi6220-sramctrl", "syscon" -- reg : Register address and size - -Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several -SRAM banks for power management, modem, security, etc. Further, use "syscon" -managing the common sram which can be shared by multiple modules. - -Example: - /*for Hi6220*/ - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; - ----------------------------------------------------------------------- Hisilicon HiP01 system controller @@ -226,56 +208,6 @@ Example: }; ----------------------------------------------------------------------- -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller - -Required properties: -- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; -- reg : Register address and size - -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 PCIe-SAS sub system */ - pcie_sas: system_controller@b0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0xb0000000 0x10000>; - }; - -Hisilicon HiP05/HiP06 PERI sub system controller - -Required properties: -- compatible : "hisilicon,peri-subctrl", "syscon"; -- reg : Register address and size - -The PERI sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. The peripheral -controllers include mdio, ddr, iic, uart, timer and so on. - -Example: - /* for HiP05 sub peri system */ - peri_c_subctrl: syscon@80000000 { - compatible = "hisilicon,peri-subctrl", "syscon"; - reg = <0x0 0x80000000 0x0 0x10000>; - }; - -Hisilicon HiP05/HiP06 DSA sub system controller - -Required properties: -- compatible : "hisilicon,dsa-subctrl", "syscon"; -- reg : Register address and size - -The DSA sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 dsa sub system */ - pcie_sas: system_controller@a0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0xa0000000 0x10000>; - }; - ------------------------------------------------------------------------ Hisilicon CPU controller Required properties: From patchwork Tue Sep 29 14:14:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313759 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206168ilg; Tue, 29 Sep 2020 07:15:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyBeEgaiBVGRXCC8vuWu5SpYqqFa0OWXdvXDEN07fme/alSR8Lk85HhBGQv2brTBmdSjPjf X-Received: by 2002:a17:906:3c47:: with SMTP id i7mr4005208ejg.554.1601388934014; Tue, 29 Sep 2020 07:15:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388934; cv=none; d=google.com; s=arc-20160816; b=ghKgLSRNL9tZyPtyI1WjgWmmYnDg3Sh9wycVr75jyhftO+svoOZQz4Vj3JaTgFEnDO NsxdLBmghSUEOt2b1wi2b6So5vXI3Pn82aGH6jHnLvonD2h0ip4lPoYrQut+xWTUft39 NhHu+niqt5GRSLRRaAJ+/eHuzV1+vfGVTXXoO+VGAUix0EqT9q2xvo0c8VnS2+0a9grl M2FB1eBG5JuMv8T3RMOK3bDVXjpYnNZ3g913+Caiq/+BxQfpBNm1M82FbcOAB/XrQbRV 8te+9ZjUMw6XaXYRAL/vbjSKLpKrOY+uxcF0BqW+be1xQwHj1xKppQBUsQhwbyBrJSKp oYLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=uaCbgqEUw9Ip5oWiqPmgxUSh5UNkbXGu17Rkigfnl1k=; b=vg1Ho+Z/pLzxUVLJ5pKgdvlkoehvA5R49WjtW+INyeLrEYFgDBrc83nI/o3/C4U5M+ S7b5ea3zw6oH6Sgjad1aK4ehINczRAuWqcXX76KicvDPyIpNJHXCS7btJxGYQWFY/YAK 73DYZAwmkMUOa7WJzqb+3YOi8w5FJjte3/NtnJOypDDFq+hFrjURY+h7AplDt3HuZr3g ofXl5W8r7V6evnnU3mznofCwc9PfCMWAOcr1Ci4YUMwsk+9qVBAhFrFBW96hbTe0MwPp 4OvJ5R56+6kEUXUemLt78eaA+ePwfLT3cilqPEqmJ+JW/ECbMj1f6l2IeXKHKspwhldC ry2A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bt13si2973506ejb.259.2020.09.29.07.15.33; Tue, 29 Sep 2020 07:15:34 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731007AbgI2OPc (ORCPT + 6 others); Tue, 29 Sep 2020 10:15:32 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14779 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728705AbgI2OPa (ORCPT ); Tue, 29 Sep 2020 10:15:30 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 72CB6495249992A87A26; Tue, 29 Sep 2020 22:15:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:12 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 03/17] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file Date: Tue, 29 Sep 2020 22:14:40 +0800 Message-ID: <20200929141454.2312-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Split the devicetree bindings of each Hisilicon controller from hisilicon.txt into a separate file, the file name is the compatible name attach the .txt file name extension. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 + .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 +++ .../controller/hisilicon,hi6220-aoctrl.txt | 18 ++ .../controller/hisilicon,hi6220-mediactrl.txt | 18 ++ .../controller/hisilicon,hi6220-pmctrl.txt | 18 ++ .../controller/hisilicon,hi6220-sysctrl.txt | 19 ++ .../controller/hisilicon,hip01-sysctrl.txt | 19 ++ .../controller/hisilicon,hip04-bootwrapper.txt | 9 + .../controller/hisilicon,hip04-fabric.txt | 5 + .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 ++ .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 +++ .../bindings/arm/hisilicon/hisilicon.txt | 194 --------------------- 12 files changed, 173 insertions(+), 194 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt new file mode 100644 index 000000000000000..ceffac537671668 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt @@ -0,0 +1,8 @@ +Hisilicon CPU controller + +Required properties: +- compatible : "hisilicon,cpuctrl" +- reg : Register address and size + +The clock registers and power registers of secondary cores are defined +in CPU controller, especially in HIX5HD2 SoC. diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt new file mode 100644 index 000000000000000..0d5282f4670658d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt @@ -0,0 +1,21 @@ +Hisilicon Hi3798CV200 Peripheral Controller + +The Hi3798CV200 Peripheral Controller controls peripherals, queries +their status, and configures some functions of peripherals. + +Required properties: +- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" + and "simple-mfd". +- reg: Register address and size of Peripheral Controller. +- #address-cells: Should be 1. +- #size-cells: Should be 1. + +Examples: + + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt new file mode 100644 index 000000000000000..5a723c1d45f4a17 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Power Always ON domain controller + +Required properties: +- compatible : "hisilicon,hi6220-aoctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power always +on domain for mobile platform. + +Example: + /*for Hi6220*/ + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0x0 0xf7800000 0x0 0x2000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt new file mode 100644 index 000000000000000..dcfdcbcb6455771 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Media domain controller + +Required properties: +- compatible : "hisilicon,hi6220-mediactrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the multimedia +domain(e.g. codec, G3D ...) for mobile platform. + +Example: + /*for Hi6220*/ + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0x0 0xf4410000 0x0 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt new file mode 100644 index 000000000000000..972842f07b5a2ce --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Power Management domain controller + +Required properties: +- compatible : "hisilicon,hi6220-pmctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, some clock registers are define + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power management +domain for mobile platform. + +Example: + /*for Hi6220*/ + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0x0 0xf7032000 0x0 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt new file mode 100644 index 000000000000000..07e318eda254f52 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt @@ -0,0 +1,19 @@ +Hisilicon Hi6220 system controller + +Required properties: +- compatible : "hisilicon,hi6220-sysctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this controller as one of the system controllers, +its main functions are the same as Hisilicon system controller, but +the register offset of some core modules are different. + +Example: + /*for Hi6220*/ + sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt new file mode 100644 index 000000000000000..db2dfdce799db91 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt @@ -0,0 +1,19 @@ +Hisilicon HiP01 system controller + +Required properties: +- compatible : "hisilicon,hip01-sysctrl" +- reg : Register address and size + +The HiP01 system controller is mostly compatible with hisilicon +system controller,but it has some specific control registers for +HIP01 SoC family, such as slave core boot, and also some same +registers located at different offset. + +Example: + + /* for hip01-ca9x2 */ + sysctrl: system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt new file mode 100644 index 000000000000000..b0d53333f4fdae1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt @@ -0,0 +1,9 @@ +Bootwrapper boot method (software protocol on SMP): + +Required Properties: +- compatible: "hisilicon,hip04-bootwrapper"; +- boot-method: Address and size of boot method. + [0]: bootwrapper physical address + [1]: bootwrapper size + [2]: relocation physical address + [3]: relocation size diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt new file mode 100644 index 000000000000000..40453d02f2024bd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt @@ -0,0 +1,5 @@ +Fabric: + +Required Properties: +- compatible: "hisilicon,hip04-fabric"; +- reg: Address and size of Fabric diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt new file mode 100644 index 000000000000000..deec777bc3a850a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt @@ -0,0 +1,13 @@ +PCTRL: Peripheral misc control register + +Required Properties: +- compatible: "hisilicon,pctrl" +- reg: Address and size of pctrl. + +Example: + + /* for Hi3620 */ + pctrl: pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt new file mode 100644 index 000000000000000..963f7f1ca7a2f0c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt @@ -0,0 +1,25 @@ +Hisilicon system controller + +Required properties: +- compatible : "hisilicon,sysctrl" +- reg : Register address and size + +Optional properties: +- smp-offset : offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go +- resume-offset : offset in sysctrl for notifying cpu0 when resume +- reboot-offset : offset in sysctrl for system reboot + +Example: + + /* for Hi3620 */ + sysctrl: system-controller@fc802000 { + compatible = "hisilicon,sysctrl"; + reg = <0xfc802000 0x1000>; + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 54f423d87a80a6a..ffe760a636b5e7f 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -55,197 +55,3 @@ Required root node properties: HiP07 D05 Board Required root node properties: - compatible = "hisilicon,hip07-d05"; - -Hisilicon system controller - -Required properties: -- compatible : "hisilicon,sysctrl" -- reg : Register address and size - -Optional properties: -- smp-offset : offset in sysctrl for notifying slave cpu booting - cpu 1, reg; - cpu 2, reg + 0x4; - cpu 3, reg + 0x8; - If reg value is not zero, cpun exit wfi and go -- resume-offset : offset in sysctrl for notifying cpu0 when resume -- reboot-offset : offset in sysctrl for system reboot - -Example: - - /* for Hi3620 */ - sysctrl: system-controller@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi3798CV200 Peripheral Controller - -The Hi3798CV200 Peripheral Controller controls peripherals, queries -their status, and configures some functions of peripherals. - -Required properties: -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" - and "simple-mfd". -- reg: Register address and size of Peripheral Controller. -- #address-cells: Should be 1. -- #size-cells: Should be 1. - -Examples: - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi6220 system controller - -Required properties: -- compatible : "hisilicon,hi6220-sysctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this controller as one of the system controllers, -its main functions are the same as Hisilicon system controller, but -the register offset of some core modules are different. - -Example: - /*for Hi6220*/ - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Always ON domain controller - -Required properties: -- compatible : "hisilicon,hi6220-aoctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power always -on domain for mobile platform. - -Example: - /*for Hi6220*/ - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Media domain controller - -Required properties: -- compatible : "hisilicon,hi6220-mediactrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the multimedia -domain(e.g. codec, G3D ...) for mobile platform. - -Example: - /*for Hi6220*/ - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Management domain controller - -Required properties: -- compatible : "hisilicon,hi6220-pmctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, some clock registers are define - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power management -domain for mobile platform. - -Example: - /*for Hi6220*/ - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; - ------------------------------------------------------------------------ -Hisilicon HiP01 system controller - -Required properties: -- compatible : "hisilicon,hip01-sysctrl" -- reg : Register address and size - -The HiP01 system controller is mostly compatible with hisilicon -system controller,but it has some specific control registers for -HIP01 SoC family, such as slave core boot, and also some same -registers located at different offset. - -Example: - - /* for hip01-ca9x2 */ - sysctrl: system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. - ------------------------------------------------------------------------ -PCTRL: Peripheral misc control register - -Required Properties: -- compatible: "hisilicon,pctrl" -- reg: Address and size of pctrl. - -Example: - - /* for Hi3620 */ - pctrl: pctrl@fca09000 { - compatible = "hisilicon,pctrl"; - reg = <0xfca09000 0x1000>; - }; - ------------------------------------------------------------------------ -Fabric: - -Required Properties: -- compatible: "hisilicon,hip04-fabric"; -- reg: Address and size of Fabric - ------------------------------------------------------------------------ -Bootwrapper boot method (software protocol on SMP): - -Required Properties: -- compatible: "hisilicon,hip04-bootwrapper"; -- boot-method: Address and size of boot method. - [0]: bootwrapper physical address - [1]: bootwrapper size - [2]: relocation physical address - [3]: relocation size From patchwork Tue Sep 29 14:14:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313756 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206008ilg; Tue, 29 Sep 2020 07:15:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxdms7AhmS99FKuCHmM1PwKztjSBYIg3zRouTWge/AFbkNpswY1ADgwSFJUvCsxn1yTP3Pq X-Received: by 2002:a17:906:7248:: with SMTP id n8mr4095147ejk.160.1601388922705; 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[23.128.96.18]) by mx.google.com with ESMTP id u2si3094814edy.251.2020.09.29.07.15.22; Tue, 29 Sep 2020 07:15:22 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729098AbgI2OPV (ORCPT + 6 others); Tue, 29 Sep 2020 10:15:21 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14780 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728599AbgI2OPV (ORCPT ); Tue, 29 Sep 2020 10:15:21 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 78E8BC5ADCCD71D945CE; Tue, 29 Sep 2020 22:15:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:13 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 04/17] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema Date: Tue, 29 Sep 2020 22:14:41 +0800 Message-ID: <20200929141454.2312-5-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Hisilicon SoC bindings to DT schema format using json-schema. Signed-off-by: Zhen Lei Reviewed-by: Rob Herring --- .../bindings/arm/hisilicon/hisilicon.txt | 57 -------------------- .../bindings/arm/hisilicon/hisilicon.yaml | 62 ++++++++++++++++++++++ 2 files changed, 62 insertions(+), 57 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt deleted file mode 100644 index ffe760a636b5e7f..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ /dev/null @@ -1,57 +0,0 @@ -Hisilicon Platforms Device Tree Bindings ----------------------------------------------------- -Hi3660 SoC -Required root node properties: - - compatible = "hisilicon,hi3660"; - -HiKey960 Board -Required root node properties: - - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; - -Hi3670 SoC -Required root node properties: - - compatible = "hisilicon,hi3670"; - -HiKey970 Board -Required root node properties: - - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; - -Hi3798cv200 SoC -Required root node properties: - - compatible = "hisilicon,hi3798cv200"; - -Hi3798cv200 Poplar Board -Required root node properties: - - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; - -Hi4511 Board -Required root node properties: - - compatible = "hisilicon,hi3620-hi4511"; - -Hi6220 SoC -Required root node properties: - - compatible = "hisilicon,hi6220"; - -HiKey Board -Required root node properties: - - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; - -HiP01 ca9x2 Board -Required root node properties: - - compatible = "hisilicon,hip01-ca9x2"; - -HiP04 D01 Board -Required root node properties: - - compatible = "hisilicon,hip04-d01"; - -HiP05 D02 Board -Required root node properties: - - compatible = "hisilicon,hip05-d02"; - -HiP06 D03 Board -Required root node properties: - - compatible = "hisilicon,hip06-d03"; - -HiP07 D05 Board -Required root node properties: - - compatible = "hisilicon,hip07-d05"; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml new file mode 100644 index 000000000000000..6d17309c7c84308 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Platforms Device Tree Bindings + +maintainers: + - Wei Xu + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Hi3660 based boards. + items: + - const: hisilicon,hi3660-hikey960 + - const: hisilicon,hi3660 + + - description: Hi3670 based boards. + items: + - const: hisilicon,hi3670-hikey970 + - const: hisilicon,hi3670 + + - description: Hi3798cv200 based boards. + items: + - const: hisilicon,hi3798cv200-poplar + - const: hisilicon,hi3798cv200 + + - description: Hi4511 Board + items: + - const: hisilicon,hi3620-hi4511 + + - description: Hi6220 based boards. + items: + - const: hisilicon,hi6220-hikey + - const: hisilicon,hi6220 + + - description: HiP01 based boards. + items: + - const: hisilicon,hip01-ca9x2 + - const: hisilicon,hip01 + + - description: HiP04 D01 Board + items: + - const: hisilicon,hip04-d01 + + - description: HiP05 D02 Board + items: + - const: hisilicon,hip05-d02 + + - description: HiP06 D03 Board + items: + - const: hisilicon,hip06-d03 + + - description: HiP07 D05 Board + items: + - const: hisilicon,hip07-d05 +... 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[23.128.96.18]) by mx.google.com with ESMTP id bt13si2973506ejb.259.2020.09.29.07.15.30; Tue, 29 Sep 2020 07:15:30 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730601AbgI2OP0 (ORCPT + 6 others); Tue, 29 Sep 2020 10:15:26 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14720 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730448AbgI2OP0 (ORCPT ); Tue, 29 Sep 2020 10:15:26 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 90851EB1130CB4B38CC7; Tue, 29 Sep 2020 22:15:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:13 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 05/17] dt-bindings: arm: hisilicon: add binding for SD5203 SoC Date: Tue, 29 Sep 2020 22:14:42 +0800 Message-ID: <20200929141454.2312-6-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree binding for Hisilicon SD5203 SoC. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml | 5 +++++ 1 file changed, 5 insertions(+) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml index 6d17309c7c84308..43b8ce2227aaae9 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml @@ -59,4 +59,9 @@ properties: - description: HiP07 D05 Board items: - const: hisilicon,hip07-d05 + + - description: SD5203 based boards + items: + - const: H836ASDJ + - const: hisilicon,sd5203 ... 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[23.128.96.18]) by mx.google.com with ESMTP id p26si2775529ejf.86.2020.09.29.07.16.02; Tue, 29 Sep 2020 07:16:03 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731002AbgI2OP5 (ORCPT + 6 others); Tue, 29 Sep 2020 10:15:57 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14719 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730810AbgI2OPm (ORCPT ); Tue, 29 Sep 2020 10:15:42 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 8B818BA33B7AD039D4F4; Tue, 29 Sep 2020 22:15:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:14 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 06/17] ARM: hisi: add support for SD5203 SoC Date: Tue, 29 Sep 2020 22:14:43 +0800 Message-ID: <20200929141454.2312-7-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Enable support for the Hisilicon SD5203 SoC. The core is ARM926EJ-S. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/mach-hisi/Kconfig | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 1.8.3 diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 3b010fe7c0e9b48..2e980f834a6aa1b 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only config ARCH_HISI bool "Hisilicon SoC Support" - depends on ARCH_MULTI_V7 + depends on ARCH_MULTI_V7 || ARCH_MULTI_V5 select ARM_AMBA - select ARM_GIC + select ARM_GIC if ARCH_MULTI_V7 select ARM_TIMER_SP804 select POWER_RESET select POWER_RESET_HISI @@ -15,6 +15,7 @@ menu "Hisilicon platform type" config ARCH_HI3xxx bool "Hisilicon Hi36xx family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -25,6 +26,7 @@ config ARCH_HI3xxx config ARCH_HIP01 bool "Hisilicon HIP01 family" + depends on ARCH_MULTI_V7 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ARM_GLOBAL_TIMER @@ -33,6 +35,7 @@ config ARCH_HIP01 config ARCH_HIP04 bool "Hisilicon HiP04 Cortex A15 family" + depends on ARCH_MULTI_V7 select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select MCPM if SMP @@ -43,6 +46,7 @@ config ARCH_HIP04 config ARCH_HIX5HD2 bool "Hisilicon X5HD2 family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -50,6 +54,14 @@ config ARCH_HIX5HD2 select PINCTRL_SINGLE help Support for Hisilicon HIX5HD2 SoC family + +config ARCH_SD5203 + bool "Hisilicon SD5203 family" + depends on ARCH_MULTI_V5 + select DW_APB_ICTL + help + Support for Hisilicon SD5203 SoC family + endmenu endif From patchwork Tue Sep 29 14:14:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313773 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4207017ilg; Tue, 29 Sep 2020 07:16:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzykK3cpc/fajHemmMONgZc7ypKu3FRQr+nSXIm++Jkqh2cCe7hr5kBU6tZ6PwDJE33VHWu X-Received: by 2002:a17:906:c55:: with SMTP id t21mr4303497ejf.276.1601388993398; Tue, 29 Sep 2020 07:16:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388993; cv=none; d=google.com; s=arc-20160816; b=e//vX476dODVzIG+pewoGODunKquB6kWUTSCyniqngmATUcRYiSliSRAowbIbai4SU a4Xnu8N7SkN64u7bwkjwkWwu/oYJoaZOEkDw9eEMB9k+T75WSc9Yc+PfUWD45Po+iLV+ RR40izEE8zIJ4TX5vC83Tk/B11dVUYlVT5pLnxOQgr1AWmXUVdobzjYbj8iv8ND8s37P pyVnvPd2rhwnnWg3Js7+g0oHt4Y36YS0YBPwuA/ryXpr3M/0EsuB184l8YPCzhtb1rwZ dJ3BEpA28XTJvMZe6zZB3tE5S1HWV/ad7dCrwNyZewI9bwaVAbiARmOJc9XgnCqsFftf OSdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=vBY6HV1Qej/RJ01qRTL+9wLFWIqsKm76YvTE5EBi5y0=; b=bJQCAdQGp8KlWTAa0YtzGiAciS/aMQsPg/XQtJU627g3jGA9qaNDkTRTe9lIJjUVx/ sv+Fcl0a9LazrMi4Wb5eHHDeuDzLOI537QTMX1nIF0G2K9c8Ndnc4Uvajp/LSLyQc7EK bv37svNQIsvtLXPo9yKEzgEGh/uS1Np2k0PNDq4y7lAgQoNWlvJuzblCD9S0olw7Hpe0 9gk6nhRAeIN2PKL90+JzUHb3WQYCdAzxF6mMWbEL9kWaBDqijKDtZiaSrmmdhOTd79H3 puY0PoU+aiP02Tr1aCr8TgokTgqsRJR1w33NtJ+rmZ1LGl1+R1f5ZkPoofEw1uWgsgq3 Mruw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e9si2746312ejt.529.2020.09.29.07.16.33; Tue, 29 Sep 2020 07:16:33 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730772AbgI2OQc (ORCPT + 6 others); Tue, 29 Sep 2020 10:16:32 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14718 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730452AbgI2OP2 (ORCPT ); Tue, 29 Sep 2020 10:15:28 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 868946862B18E65487C6; Tue, 29 Sep 2020 22:15:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:14 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 07/17] ARM: debug: add UART early console support for SD5203 Date: Tue, 29 Sep 2020 22:14:44 +0800 Message-ID: <20200929141454.2312-8-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Add support of early console for SD5203. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/Kconfig.debug | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) -- 1.8.3 diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 80000a66a4e3549..d27a7764c3bfb46 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1086,6 +1086,14 @@ choice on SA-11x0 UART ports. The kernel will check for the first enabled UART in a sequence 3-1-2. + config DEBUG_SD5203_UART + bool "Hisilicon SD5203 Debug UART" + depends on ARCH_SD5203 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on SD5203 UART. + config DEBUG_SOCFPGA_UART0 depends on ARCH_SOCFPGA bool "Use SOCFPGA UART0 for low-level debug" @@ -1639,6 +1647,7 @@ config DEBUG_UART_PHYS default 0x11006000 if DEBUG_MT6589_UART0 default 0x11009000 if DEBUG_MT8135_UART3 default 0x16000000 if DEBUG_INTEGRATOR + default 0x1600d000 if DEBUG_SD5203_UART default 0x18000300 if DEBUG_BCM_5301X default 0x18000400 if DEBUG_BCM_HR2 default 0x18010000 if DEBUG_SIRFATLAS7_UART0 @@ -1841,7 +1850,7 @@ config DEBUG_UART_VIRT default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1 default 0xfec90000 if DEBUG_RK32_UART2 default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 - default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 + default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART default 0xfed60000 if DEBUG_RK29_UART0 default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 From patchwork Tue Sep 29 14:14:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313768 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206863ilg; Tue, 29 Sep 2020 07:16:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyc0FPUPqJYs4uLl88vj6Vm5dM4UQlmbGipLM4zQqYufVhjI/o51kg4W1CUjEvbHIcyg3T1 X-Received: by 2002:a50:9b19:: with SMTP id o25mr3360094edi.340.1601388982175; Tue, 29 Sep 2020 07:16:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388982; cv=none; d=google.com; s=arc-20160816; b=cZ6nVYfgGwJfF8zV1t+KTKsUWmBm8J4xzkvFIDfp8FjOlQjZ1zKcua1OQa/fleVcua J9Ph8x6/w63ZuYy0M7aNg2QmuIPhk7++QVWBYh52GiqIPpIPnlJPmcV0+THlVOiCpdVD zYPCBTrje4x+hatRdOTNtrqbLuAjzVS6mMuRDG8Lk4WCIc/NbOhByZnUjv7GaJuK5+zu 42KqWEwdN3vwe+8SRzTmoCahrY6YAjxUI7ciQ6gZr+qDLRgjI2j2JGFFmU/ZdORIE2oQ ofJIhvIfJ3fcBZnL2CFIwW7nWhCBW448FvIDzSa1WRhcwg1j4kjnbfhSO7ylXKjDhhZo I4Dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=qaTY6Bs1ej95bN4jlVHPRiwBRGFpx3xoNkvxROLgOlw=; b=VZaNYuxVGRpRr/dHX38idrTD8k20NZrRk2hTrrOb9Zc12lLNetIvO2gi+NwOQKbop1 PVP0hdL9SsYZyTosYNr01e+POudJYOiCXzNqi/JbbSNYVyVNuVzWWl5LXaGgR9i1LifY SGyyYWAjS1Um+fPaxXKO91QEFY6xF+BLUCpC7tE1tn7o0vb0w5KftxAraxTwxEAATEWg fC5zQxfj0S1MZ5Q6beL4Xf1RDp31Kos6vahloDQCvJ9AH71TejnNdVu4qaXcjXAHzGqZ oStpDv/qGGBfgopGaj58Mkv/f8in8kbn/g43D6cooVLH78KKwE/2TWxRnfFtCBHPboh4 rUSA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e9si2746312ejt.529.2020.09.29.07.16.22; Tue, 29 Sep 2020 07:16:22 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730216AbgI2OQK (ORCPT + 6 others); Tue, 29 Sep 2020 10:16:10 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14724 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730778AbgI2OPa (ORCPT ); Tue, 29 Sep 2020 10:15:30 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 9F1E8884EF6EDEE079B7; Tue, 29 Sep 2020 22:15:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:15 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 08/17] ARM: dts: add SD5203 dts Date: Tue, 29 Sep 2020 22:14:45 +0800 Message-ID: <20200929141454.2312-9-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Add sd5203.dts for Hisilicon SD5203 SoC platform. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sd5203.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 arch/arm/boot/dts/sd5203.dts -- 1.8.3 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae302..1d1262df5c55907 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \ mps2-an399.dtb dtb-$(CONFIG_ARCH_MOXART) += \ moxart-uc7112lx.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb dtb-$(CONFIG_SOC_IMX1) += \ imx1-ads.dtb \ imx1-apf9328.dtb diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts new file mode 100644 index 000000000000000..3cc9a23910be62e --- /dev/null +++ b/arch/arm/boot/dts/sd5203.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 Hisilicon Limited. + * + * DTS file for Hisilicon SD5203 Board + */ + +/dts-v1/; + +/ { + model = "Hisilicon SD5203"; + compatible = "H836ASDJ", "hisilicon,sd5203"; + interrupt-parent = <&vic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + }; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + refclk125mhz: refclk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + timer0: timer@16002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16002000 0x1000>; + interrupts = <4>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + timer1: timer@16003000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16003000 0x1000>; + interrupts = <5>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + uart0: serial@1600d000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600d000 0x1000>; + bus_id = "uart0"; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <17>; + }; + + uart1: serial@1600c000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600c000 0x1000>; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <16>; + status = "disabled"; + }; + }; +}; From patchwork Tue Sep 29 14:14:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313758 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206113ilg; Tue, 29 Sep 2020 07:15:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJysPX6h3KsR9Ta3+KZ5ssKXn3hY/K+/HTTelm6E6/VtG801iH8CslTRbmiVDvu9HsL1se1a X-Received: by 2002:a17:906:3bca:: with SMTP id v10mr4021645ejf.57.1601388930723; Tue, 29 Sep 2020 07:15:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388930; cv=none; d=google.com; s=arc-20160816; b=lPM9t6W43tn9MvQmXJPzKSQ8+WdjCGEFrw3T94fd1VnEGYNTk0gLZmxR0tIbVoEqR9 NVLZeYtXR9oFkZod5PKQ3cGDyqPq9zsIUYGLWWm1b2LQqRIj7AfzcF1RIhRVvZrlP4ku PsrHiVVpIjWxBfHckdPXJ9tpVV3IxgYrupvGX+MNnz5m9WgbyLS8QDIvpRr1wnAo9fzX 55hWWnR58UJyAmi6ES7ZvqkHVqx5wXlV64nfOSkt4Qua3uMeJFil7Q9dt9eAjR5e4Uq7 cKvwaXEjg1BPEqPwrccW7X6UWVP8d/sdFjOTiWwN7EJJvoeX6QHYCX1HzA7jOxiDumTk VUqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=5sZsuZ0eEN7C+b/Jr7fHPBnNkpaPIktSR6AnyqkRnIM=; b=sPBo00c4cVzKG4vzJDeIBylUAqpubGwRNCxROTOH89SWPa7001OpgfyrQVTfMm9ghV M8rnZJ8u0lwNndOO90hT5/SSS+SqM/SHyz42dHjNEQOsoyqjgssnxFDqi1hSNcnXtE5X X2NKWmW13lBmrQw0bRNwtXzNCNT6kq77u8FtW2+aEeP2Cx+pPo/ycoPS1WpVtSk35bc9 FZDYwXebZNK9O5FDOn6aXIzVYnrh3JBs+6f8gxMxS3iAIbMZ1oZFxky880d19VD31OB9 FZOKLr/uM1IkErRmUFmP4Vg31OZUlbhuVAjwRlt8tI+VPQJUwM2i8twkKjtZdyuO0aYL YTzg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bt13si2973506ejb.259.2020.09.29.07.15.30; Tue, 29 Sep 2020 07:15:30 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730627AbgI2OP0 (ORCPT + 6 others); Tue, 29 Sep 2020 10:15:26 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14722 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730430AbgI2OP0 (ORCPT ); Tue, 29 Sep 2020 10:15:26 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 9A486AF1AD5D9518AA74; Tue, 29 Sep 2020 22:15:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:16 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 09/17] ARM: dts: hisilicon: fix ststem controller compatible node Date: Tue, 29 Sep 2020 22:14:46 +0800 Message-ID: <20200929141454.2312-10-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The DT binding for Hisilicon system controllers requires to have a "syscon" compatible string. Signed-off-by: Zhen Lei --- arch/arm/boot/dts/hi3620.dtsi | 2 +- arch/arm/boot/dts/hip04.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 1.8.3 diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 355175b25fd6220..f683440ee5694b4 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -89,7 +89,7 @@ }; sysctrl: system-controller@802000 { - compatible = "hisilicon,sysctrl"; + compatible = "hisilicon,sysctrl", "syscon"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x802000 0x1000>; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index f5871b1d1ec452c..555bc6b6720fc94 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -213,7 +213,7 @@ }; sysctrl: sysctrl { - compatible = "hisilicon,sysctrl"; + compatible = "hisilicon,sysctrl", "syscon"; reg = <0x3e00000 0x00100000>; }; From patchwork Tue Sep 29 14:14:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313770 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206878ilg; Tue, 29 Sep 2020 07:16:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyZoBfSb1V+zbHmvxHDUcMpU3vn62t48g5rXmZSpvOs84PzgwkxQSQ2cUWuI1gmBaZGRPHs X-Received: by 2002:a17:906:c1c3:: with SMTP id bw3mr4048950ejb.516.1601388983194; Tue, 29 Sep 2020 07:16:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388983; cv=none; d=google.com; s=arc-20160816; b=d3pIEh21so/Ns8+MWsb4xCrKUI/fYF/YBJ31LGf3cy4BMzy0X0YUbv8AQieYpEGuoV eJW12CVLWFR6gmpuTdTSS+HKjrNosIUykU74HHfU7AOHBcPlcAfQdK3TcK05fXy0axAe 4auu1YQW33+h3rzhBf8KnK7nbbsWw5mgkkkOpIjXu8astYv8pXRt+3eSBOMwigqJgSKv +J6cVdHhwlx/XfNmA+RJNpRygLRgZciQOebkdSbtM6thw6KxuevcQRxdIFzGcSsAAuYq R89+7wMvrAGsmqTgvFozhVtsECKOAluj9bY3ibOLbtv5sMcjP/0NMvZO0VbOXbZzb9wQ 9Z3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=mIxCYQ/A/Mzd4b1DNt9K1j4tCby8c8nGq4hcB8AET5o=; b=XkMD+8bY82y09AueQg7rwxA+0RHK5va2yGG516fcW6HtuWak9h8WZB1gpDB7A1Qaow ZRs7a3j0IWleML4qducH04hIUbFgHWbNymKJaOv/0UjOFjH8HbWPZlhDABt0skbH8m2N jfFkbjnmqWr1iQm02KHfxf0YEfltwFoi3IngPHP2YcCsWcrf4Aaiq/s9BJec8hljbvv0 LXc5N1EXzyp5GYkh2rxcRvII67g0Y6sPxyD2+apM2jH3OTnLP4C9hwKgCDgZk/L8Msg+ WYtCAHId2lb0FGer4SGHwdVSqjH25uwhcn516HpkWEUl1kyatg+Ug+ZmUYwrriDxOQ5V aqxg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e9si2746312ejt.529.2020.09.29.07.16.22; Tue, 29 Sep 2020 07:16:23 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728514AbgI2OQK (ORCPT + 6 others); Tue, 29 Sep 2020 10:16:10 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14725 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730854AbgI2OPb (ORCPT ); Tue, 29 Sep 2020 10:15:31 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id B019BB53DEB46DDB8FF7; Tue, 29 Sep 2020 22:15:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:16 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 10/17] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema Date: Tue, 29 Sep 2020 22:14:47 +0800 Message-ID: <20200929141454.2312-11-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon system controller and its variants binding to DT schema format using json-schema. All of them are grouped into one yaml file, to help users understand differences and avoid repeated descriptions. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-sysctrl.txt | 19 ---- .../controller/hisilicon,hip01-sysctrl.txt | 19 ---- .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 ----- .../bindings/arm/hisilicon/controller/sysctrl.yaml | 110 +++++++++++++++++++++ .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 --- 5 files changed, 110 insertions(+), 77 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt deleted file mode 100644 index 07e318eda254f52..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt +++ /dev/null @@ -1,19 +0,0 @@ -Hisilicon Hi6220 system controller - -Required properties: -- compatible : "hisilicon,hi6220-sysctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this controller as one of the system controllers, -its main functions are the same as Hisilicon system controller, but -the register offset of some core modules are different. - -Example: - /*for Hi6220*/ - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt deleted file mode 100644 index db2dfdce799db91..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt +++ /dev/null @@ -1,19 +0,0 @@ -Hisilicon HiP01 system controller - -Required properties: -- compatible : "hisilicon,hip01-sysctrl" -- reg : Register address and size - -The HiP01 system controller is mostly compatible with hisilicon -system controller,but it has some specific control registers for -HIP01 SoC family, such as slave core boot, and also some same -registers located at different offset. - -Example: - - /* for hip01-ca9x2 */ - sysctrl: system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt deleted file mode 100644 index 963f7f1ca7a2f0c..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt +++ /dev/null @@ -1,25 +0,0 @@ -Hisilicon system controller - -Required properties: -- compatible : "hisilicon,sysctrl" -- reg : Register address and size - -Optional properties: -- smp-offset : offset in sysctrl for notifying slave cpu booting - cpu 1, reg; - cpu 2, reg + 0x4; - cpu 3, reg + 0x8; - If reg value is not zero, cpun exit wfi and go -- resume-offset : offset in sysctrl for notifying cpu0 when resume -- reboot-offset : offset in sysctrl for system reboot - -Example: - - /* for Hi3620 */ - sysctrl: system-controller@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml new file mode 100644 index 000000000000000..449140f89ddbc3b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon system controller + +maintainers: + - Wei Xu + +description: | + The Hisilicon system controller is used on many Hisilicon boards, it can be + used to assist the slave core startup, reboot the system, etc. + + There are some variants of the Hisilicon system controller, such as HiP01, + Hi3519, Hi6220 system controller, each of them is mostly compatible with the + Hisilicon system controller, but some same registers located at different + offset. In addition, the HiP01 system controller has some specific control + registers for HIP01 SoC family, such as slave core boot. + + The compatible names of each system controller are as follows: + Hisilicon system controller --> hisilicon,sysctrl + HiP01 system controller --> hisilicon,hip01-sysctrl + Hi6220 system controller --> hisilicon,hi6220-sysctrl + Hi3519 system controller --> hisilicon,hi3519-sysctrl + +allOf: + - if: + properties: + compatible: + contains: + const: hisilicon,hi6220-sysctrl + then: + required: + - '#clock-cells' + +properties: + compatible: + oneOf: + - items: + - enum: + - hisilicon,sysctrl + - hisilicon,hi6220-sysctrl + - hisilicon,hi3519-sysctrl + - const: syscon + - items: + - const: hisilicon,hip01-sysctrl + - const: hisilicon,sysctrl + + reg: + maxItems: 1 + + smp-offset: + description: | + offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go + $ref: /schemas/types.yaml#/definitions/uint32 + + resume-offset: + description: offset in sysctrl for notifying cpu0 when resume + $ref: /schemas/types.yaml#/definitions/uint32 + + reboot-offset: + description: offset in sysctrl for system reboot + $ref: /schemas/types.yaml#/definitions/uint32 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + /* Hisilicon system controller */ + system-controller@fc802000 { + compatible = "hisilicon,sysctrl", "syscon"; + reg = <0xfc802000 0x1000>; + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + }; + + /* HiP01 system controller */ + system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; + + /* Hi6220 system controller */ + system-controller@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0xf7030000 0x2000>; + #clock-cells = <1>; + }; + + /* Hi3519 system controller */ + system-controller@12010000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12010000 0x1000>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt deleted file mode 100644 index 8defacc44dd5b9e..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt +++ /dev/null @@ -1,14 +0,0 @@ -* Hisilicon Hi3519 System Controller Block - -This bindings use the following binding: -Documentation/devicetree/bindings/mfd/syscon.yaml - -Required properties: -- compatible: "hisilicon,hi3519-sysctrl". -- reg: the register region of this block - -Examples: -sysctrl: system-controller@12010000 { - compatible = "hisilicon,hi3519-sysctrl", "syscon"; - reg = <0x12010000 0x1000>; -}; From patchwork Tue Sep 29 14:14:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313772 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4207007ilg; Tue, 29 Sep 2020 07:16:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJznqDI8hx4xyRL91rDU+hMwNHpRCgilKdmtlzgEoTh0JVHHcdAnt/LEm9liG1k2K3+Vgxsl X-Received: by 2002:a17:906:f157:: with SMTP id gw23mr4009843ejb.325.1601388992140; Tue, 29 Sep 2020 07:16:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388992; cv=none; d=google.com; s=arc-20160816; b=xHq686FZkzmJ+TF1poMA5qHboCVDJny0eChxUVhWVHbAGPmy+0eW/jTcHA/SeGxT+7 fthm+Co1/fLelH9xXXHntXukNyMQXsk2eFQR8dQYtpjceJAGzVgTDhvqKHAFNVXuy+D3 Fo7U9x1EOyBOrSrFa8Z4rgkFoWgPj/mF+xHKMpiub6tT6DdSYLyaroGTn5yLuJTnx9fG Kftg5t5ypHPq8Jrf+4HN6x7FFHdlk1uoDQMDQPdA2L0PzQ3bpQfvtVCGc6XBJulhVIMt mzp85J7sUZJDz1P9psTZnj5JYMctoHpCqUnlLkPMfGvlgNLw1DSWOfo89DBBrljdzb2a 5OGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=/cv5Td9YxBdozN2S0gO++Jvx9Jpl+/Nk9vHDJR9ZQk8=; b=Rg2NRUfOmaOOVrqFrJJSKsIeSrzS6afMSjmpj2OkSeDt6SrzsKsX7gxxSaXm8b8wOz PmK3q9vX2KKnQ3KSo/Y7I/tzhNCD/1CeLP3DDeu583ewV0XO5cY27cf5j5d0V0uWbyDd CbubqCAUK9M2TIl0UbSo5+PTYWNu1UKUxZiwhaRqKZSm9Lfs/SheF6WHCVT6+onPHrlH XVxZ1Yt5+mPnGM7QyjIMGt/ZlRp0xpr8bIP/C8rCFLbyGJZ8AbiIaTrpYjb15+zYDrQK gUa/Zpkh9lbnCYb2C46LR3erno0o3yqDHfB+oS7WktWBGYF3vYM4hQilkr1iQRrwUkaU Ktqg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e9si2746312ejt.529.2020.09.29.07.16.31; Tue, 29 Sep 2020 07:16:32 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730778AbgI2OQZ (ORCPT + 6 others); Tue, 29 Sep 2020 10:16:25 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14723 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730772AbgI2OP2 (ORCPT ); Tue, 29 Sep 2020 10:15:28 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id AB84C16B1EE2ADFAB6D7; Tue, 29 Sep 2020 22:15:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:17 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 11/17] dt-bindings: arm: hisilicon: convert hisilicon, cpuctrl bindings to json-schema Date: Tue, 29 Sep 2020 22:14:48 +0800 Message-ID: <20200929141454.2312-12-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon CPU controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/controller/cpuctrl.yaml | 29 ++++++++++++++++++++++ .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 ------ 2 files changed, 29 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml new file mode 100644 index 000000000000000..f6a314db3a59416 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon CPU controller + +maintainers: + - Wei Xu + +description: | + The clock registers and power registers of secondary cores are defined + in CPU controller, especially in HIX5HD2 SoC. + +properties: + compatible: + items: + - const: hisilicon,cpuctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt deleted file mode 100644 index ceffac537671668..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt +++ /dev/null @@ -1,8 +0,0 @@ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. 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[23.128.96.18]) by mx.google.com with ESMTP id e9si2746312ejt.529.2020.09.29.07.16.25; Tue, 29 Sep 2020 07:16:25 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730843AbgI2OP2 (ORCPT + 6 others); Tue, 29 Sep 2020 10:15:28 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14721 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730369AbgI2OP2 (ORCPT ); Tue, 29 Sep 2020 10:15:28 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 9546A665D24B12652272; Tue, 29 Sep 2020 22:15:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:18 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 12/17] dt-bindings: arm: hisilicon: convert hisilicon, pctrl bindings to json-schema Date: Tue, 29 Sep 2020 22:14:49 +0800 Message-ID: <20200929141454.2312-13-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon peripheral misc control register binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 --------- .../bindings/arm/hisilicon/controller/pctrl.yaml | 34 ++++++++++++++++++++++ 2 files changed, 34 insertions(+), 13 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt deleted file mode 100644 index deec777bc3a850a..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt +++ /dev/null @@ -1,13 +0,0 @@ -PCTRL: Peripheral misc control register - -Required Properties: -- compatible: "hisilicon,pctrl" -- reg: Address and size of pctrl. - -Example: - - /* for Hi3620 */ - pctrl: pctrl@fca09000 { - compatible = "hisilicon,pctrl"; - reg = <0xfca09000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml new file mode 100644 index 000000000000000..6d50658728092cf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/pctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral misc control register + +maintainers: + - Wei Xu + +description: Peripheral misc control register + +properties: + compatible: + items: + - const: hisilicon,pctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id bt13si2973506ejb.259.2020.09.29.07.15.52; Tue, 29 Sep 2020 07:15:52 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729978AbgI2OPh (ORCPT + 6 others); Tue, 29 Sep 2020 10:15:37 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:39016 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731022AbgI2OPf (ORCPT ); Tue, 29 Sep 2020 10:15:35 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 91C0BEC47C805F1A6900; Tue, 29 Sep 2020 22:15:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:18 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 13/17] dt-bindings: arm: hisilicon: convert hisilicon, hip04-fabric bindings to json-schema Date: Tue, 29 Sep 2020 22:14:50 +0800 Message-ID: <20200929141454.2312-14-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Fabric controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hip04-fabric.yaml | 27 ++++++++++++++++++++++ .../controller/hisilicon,hip04-fabric.txt | 5 ---- 2 files changed, 27 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml new file mode 100644 index 000000000000000..60c516a04ad58b3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hip04-fabric.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Fabric controller + +maintainers: + - Wei Xu + +description: Hisilicon Fabric controller + +properties: + compatible: + items: + - const: hisilicon,hip04-fabric + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt deleted file mode 100644 index 40453d02f2024bd..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt +++ /dev/null @@ -1,5 +0,0 @@ -Fabric: - -Required Properties: -- compatible: "hisilicon,hip04-fabric"; -- reg: Address and size of Fabric From patchwork Tue Sep 29 14:14:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313767 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206726ilg; Tue, 29 Sep 2020 07:16:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwP1OeoVoRk1DhJT+4r+lGzd8yJsq/5+Fq++FBwrM3kgc9/UnmHGC0xUQ03SKGjo6yQQtdT X-Received: by 2002:aa7:dd01:: with SMTP id i1mr3555115edv.121.1601388972042; Tue, 29 Sep 2020 07:16:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388972; cv=none; d=google.com; s=arc-20160816; b=bZvebiqZo9z/7+75udqDDBEprSEr0Yzuctip/uhVSYntmnqM0/Y/WmrWz2IGW07DSm fyJNlIIUCKkWphipmCrTKkt9KyL9Wl82MHPhr43t4WeKdlbgirtiIbZZfbGpIdDrwDBk vEW7ZylvCHWHSO45SAAheNW1Hz8EqZLkFu0241ksUqqyPo1tY8bUq4MGtLsEXX/bZWR/ jvP33VAIx4NgoPelm2geeKzTaM3h7bpXvL33jmu5Kg58DwYSGyVSbwQVJcG4zQsKem2s an2s4K8kgQ2jwhcwmIrIl3nVScyz9XHITUpLMsqhDpEQAMQMaHjimyXVHp8u7gEMCJFC Z/UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=lJ3bXXqfe3I1hiw0+bHQDdIw/7V+0wrc7YA1Fllkcuk=; b=cZfLZYYcFtdA/5Z8Wc8eRWSQLOPITPXz9CN0e1ON7lGOsRQf4gAI1Nhm/DIm1DLj+d UXiizjz7RNhdZVmBTnipvq5Q1mq2N6E0pZYhBMOd+TOzayuCNMWYr5ZRQ54lP54gEpHS LxOSPBPIQxJ2Q6RlzQP0ABRhK33M3gOdR2Y1E2LtHfMzR7BenuKKRJlW7CgQhh2YKwEA 47xygkKJiBN1a0RODe2dqYYd+r5NukCGnlhv9xnCUbLp03aaIGzwwR2hx2bgROqT57gy NwGZNcSuwsOjwJJtUQXxoszoo+wW3+lzD0YIVARuA2OPl/Hcsm743MNSqJqxLPLCTE+n ERWA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q11si3240505edh.208.2020.09.29.07.16.11; Tue, 29 Sep 2020 07:16:12 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730810AbgI2OQC (ORCPT + 6 others); Tue, 29 Sep 2020 10:16:02 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:39000 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731020AbgI2OPd (ORCPT ); Tue, 29 Sep 2020 10:15:33 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 88243A8464C949D311E9; Tue, 29 Sep 2020 22:15:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:19 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 14/17] dt-bindings: arm: hisilicon: convert hisilicon, hip04-bootwrapper bindings to json-schema Date: Tue, 29 Sep 2020 22:14:51 +0800 Message-ID: <20200929141454.2312-15-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Bootwrapper boot method binding to DT schema format using json-schema. The property boot-method contains two groups of physical address range information: bootwrapper and relocation. The "uint32-array" type is not suitable for it, because the field "address" and "size" may occupy one or two cells respectively. Use "minItems: 1" and "maxItems: 2" to allow it can be written in "" or ", " format. Signed-off-by: Zhen Lei --- .../hisilicon/controller/hip04-bootwrapper.yaml | 34 ++++++++++++++++++++++ .../controller/hisilicon,hip04-bootwrapper.txt | 9 ------ 2 files changed, 34 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml new file mode 100644 index 000000000000000..7378159e61df998 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hip04-bootwrapper.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bootwrapper boot method + +maintainers: + - Wei Xu + +description: Bootwrapper boot method (software protocol on SMP) + +properties: + compatible: + items: + - const: hisilicon,hip04-bootwrapper + + boot-method: + description: | + Address and size of boot method. + [0]: bootwrapper physical address + [1]: bootwrapper size + [2]: relocation physical address + [3]: relocation size + minItems: 1 + maxItems: 2 + +required: + - compatible + - boot-method + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt deleted file mode 100644 index b0d53333f4fdae1..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt +++ /dev/null @@ -1,9 +0,0 @@ -Bootwrapper boot method (software protocol on SMP): - -Required Properties: -- compatible: "hisilicon,hip04-bootwrapper"; -- boot-method: Address and size of boot method. - [0]: bootwrapper physical address - [1]: bootwrapper size - [2]: relocation physical address - [3]: relocation size From patchwork Tue Sep 29 14:14:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313764 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206466ilg; Tue, 29 Sep 2020 07:15:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz3DlzLaK3k9NRTvcRa+VRLa7esfvpxJYQYcUk9/Gseg9t/5VxyhOf25KW82y6DG7n3ohdP X-Received: by 2002:a50:ee10:: with SMTP id g16mr3709132eds.258.1601388953183; Tue, 29 Sep 2020 07:15:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388953; cv=none; d=google.com; s=arc-20160816; b=cJyvbpi5RS44SdmUqzvj8yj/5PRw4Q7rZ0ww77okRoCcsh79tOIiiNl9vKgjf7cmFe 0ZP96Ivu/GjB/gYUeuLoVJ9/x/90ptXffwM2bwP0KnAirIusjuE0Lzc/eOilRew02VHA 2RGN4AaoBI5euKHHdEJoB2KvAWQsc3zIFtGNQml+lhciEst43COwbLfHW3E+n5zd06K7 AibXYI6gRHfWwhnCzWkCyWEHOmokeu7sb0FdDU6gd1paZCPImffNhXt97oefsbH2486X QrZvJ75KSYPugGMYU2PWVd6JlQ9kqLnCmgXQ4L/3nHQ8WvwrR0HXWTq0Ed1BDScqyvuB Qz9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=rIpqHJT7NLpbdYbP+B2xmqc/wUinpYxn7l/hspWDoU0=; b=JK5eGblesRlmXoRj+9Aq2FHDrpAXT1zmgy4TT2Mv35u06OyRlH3Mr5U21jm+Hynpff MeXSJ6USmd37cct+HvG5vjj/tk26XwI+QK2UZmlxXaaxrzP48zQ7vRZYKNbzYNV+/jq3 lr5rpXmFUV+3vJzYnQ8rKmnk0RFhWTI14VOwws020j6tXYFquJB/vttUwRfqZaJjvHYp 3QcfyUiqQZh+zemuRFHRJ6MQcLSz8pKCLkCW21gApU0KV6XnLNNUCQR6GsNnwm9L7zKg /pgVsdpQ1HELmTnFGnHs+3B1BZjawj1hgyYHkjA7cnU6E+IgIqSPzni5VZOT9DWVfQVg CHzw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bt13si2973506ejb.259.2020.09.29.07.15.53; Tue, 29 Sep 2020 07:15:53 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731120AbgI2OPv (ORCPT + 6 others); Tue, 29 Sep 2020 10:15:51 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:46140 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731002AbgI2OPh (ORCPT ); Tue, 29 Sep 2020 10:15:37 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id BDEB67C8A951A906F604; Tue, 29 Sep 2020 22:15:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:19 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 15/17] dt-bindings: arm: hisilicon: convert Hi6220 domain controller bindings to json-schema Date: Tue, 29 Sep 2020 22:14:52 +0800 Message-ID: <20200929141454.2312-16-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 domain controllers binding to DT schema format using json-schema. All of them are grouped into one yaml file, to help users understand differences and avoid repeated descriptions. Signed-off-by: Zhen Lei --- .../hisilicon/controller/hi6220-domain-ctrl.yaml | 64 ++++++++++++++++++++++ .../controller/hisilicon,hi6220-aoctrl.txt | 18 ------ .../controller/hisilicon,hi6220-mediactrl.txt | 18 ------ .../controller/hisilicon,hi6220-pmctrl.txt | 18 ------ 4 files changed, 64 insertions(+), 54 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml new file mode 100644 index 000000000000000..32c562720d877c9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi6220-domain-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 domain controller + +maintainers: + - Wei Xu + +description: | + Hisilicon designs some special domain controllers for mobile platform, + such as: the power Always On domain controller, the Media domain + controller(e.g. codec, G3D ...) and the Power Management domain + controller. + + The compatible names of each domain controller are as follows: + Power Always ON domain controller --> hisilicon,hi6220-aoctrl + Media domain controller --> hisilicon,hi6220-mediactrl + Power Management domain controller --> hisilicon,hi6220-pmctrl + +properties: + compatible: + items: + - enum: + - hisilicon,hi6220-aoctrl + - hisilicon,hi6220-mediactrl + - hisilicon,hi6220-pmctrl + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0xf7800000 0x2000>; + #clock-cells = <1>; + }; + + media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0xf4410000 0x1000>; + #clock-cells = <1>; + }; + + pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0xf7032000 0x1000>; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt deleted file mode 100644 index 5a723c1d45f4a17..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Power Always ON domain controller - -Required properties: -- compatible : "hisilicon,hi6220-aoctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power always -on domain for mobile platform. - -Example: - /*for Hi6220*/ - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt deleted file mode 100644 index dcfdcbcb6455771..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Media domain controller - -Required properties: -- compatible : "hisilicon,hi6220-mediactrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the multimedia -domain(e.g. codec, G3D ...) for mobile platform. - -Example: - /*for Hi6220*/ - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt deleted file mode 100644 index 972842f07b5a2ce..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Power Management domain controller - -Required properties: -- compatible : "hisilicon,hi6220-pmctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, some clock registers are define - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power management -domain for mobile platform. - -Example: - /*for Hi6220*/ - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; From patchwork Tue Sep 29 14:14:53 2020 Content-Type: text/plain; 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[23.128.96.18]) by mx.google.com with ESMTP id bt13si2973506ejb.259.2020.09.29.07.15.51; Tue, 29 Sep 2020 07:15:51 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731213AbgI2OPr (ORCPT + 6 others); Tue, 29 Sep 2020 10:15:47 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:46122 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731120AbgI2OPj (ORCPT ); Tue, 29 Sep 2020 10:15:39 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id B8B255224D7ED0D69A2A; Tue, 29 Sep 2020 22:15:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:20 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 16/17] dt-bindings: arm: hisilicon: convert hisilicon, hi3798cv200-perictrl bindings to json-schema Date: Tue, 29 Sep 2020 22:14:53 +0800 Message-ID: <20200929141454.2312-17-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../hisilicon/controller/hi3798cv200-perictrl.yaml | 64 ++++++++++++++++++++++ .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ------- 2 files changed, 64 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml new file mode 100644 index 000000000000000..cba1937aad9a8d3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3798cv200-perictrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi3798CV200 Peripheral Controller + +maintainers: + - Wei Xu + +description: | + The Hi3798CV200 Peripheral Controller controls peripherals, queries + their status, and configures some functions of peripherals. + +properties: + compatible: + items: + - const: hisilicon,hi3798cv200-perictrl + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: + type: object + +examples: + - | + peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + phy@850 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x850 0x8>; + #phy-cells = <1>; + clocks = <&crg 42>; + resets = <&crg 0x188 4>; + assigned-clocks = <&crg 42>; + assigned-clock-rates = <100000000>; + hisilicon,fixed-mode = <4>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt deleted file mode 100644 index 0d5282f4670658d..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt +++ /dev/null @@ -1,21 +0,0 @@ -Hisilicon Hi3798CV200 Peripheral Controller - -The Hi3798CV200 Peripheral Controller controls peripherals, queries -their status, and configures some functions of peripherals. - -Required properties: -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" - and "simple-mfd". -- reg: Register address and size of Peripheral Controller. -- #address-cells: Should be 1. -- #size-cells: Should be 1. - -Examples: - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; From patchwork Tue Sep 29 14:14:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313762 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4206449ilg; Tue, 29 Sep 2020 07:15:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxRQcKJZ2r2RqGMEw7Qqd/uEVNFAYgt31IZgioJzQTk7RstCYrX5qfFUYPq2lFZhQY29Ob4 X-Received: by 2002:a17:906:4cc2:: with SMTP id q2mr4293912ejt.422.1601388952354; Tue, 29 Sep 2020 07:15:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601388952; cv=none; d=google.com; s=arc-20160816; b=znyExwAlMTvYZAL6EvsZKfl9Vcsri105tDZ5bwV4jt8M6OkAqyh+3deGSrwopIS8la wkWBNNgBuw7NnAT3Qbh7ReqLj+87I5for7AaXRORVQivd2ZqDnhSyobFHNHGWWhzeHtW QP3129+fi4+ERLiy87KeoEL6KIB+InFs+F77lXJwCNJ3wLR0Lc4V32JvpITxV+PKq9lS AdZkfdJTzhCibMhlr6ZYVw7y5q5lSvHjYE/fCWo7IPU+vyideu7I7A6dEIFwrKRVpktH kUoX/mwDP7xn7eUrnks12tkicB2IyC4rgyRtC3CnaoKau4AOYMJnlanqdIAFU2eL2sqs pK5A== ARC-Message-Signature: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id bt13si2973506ejb.259.2020.09.29.07.15.52; Tue, 29 Sep 2020 07:15:52 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731115AbgI2OPh (ORCPT + 6 others); Tue, 29 Sep 2020 10:15:37 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:39006 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731045AbgI2OPf (ORCPT ); Tue, 29 Sep 2020 10:15:35 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 8CE88B5C14036196774B; Tue, 29 Sep 2020 22:15:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Tue, 29 Sep 2020 22:15:20 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v5 17/17] dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema Date: Tue, 29 Sep 2020 22:14:54 +0800 Message-ID: <20200929141454.2312-18-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200929141454.2312-1-thunder.leizhen@huawei.com> References: <20200929141454.2312-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------ .../bindings/arm/hisilicon/low-pin-count.yaml | 61 ++++++++++++++++++++++ 2 files changed, 61 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt deleted file mode 100644 index 10bd35f9207f2ee..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hip06 Low Pin Count device - Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which - provides I/O access to some legacy ISA devices. - Hip06 is based on arm64 architecture where there is no I/O space. So, the - I/O ports here are not CPU addresses, and there is no 'ranges' property in - LPC device node. - -Required properties: -- compatible: value should be as follows: - (a) "hisilicon,hip06-lpc" - (b) "hisilicon,hip07-lpc" -- #address-cells: must be 2 which stick to the ISA/EISA binding doc. -- #size-cells: must be 1 which stick to the ISA/EISA binding doc. -- reg: base memory range where the LPC register set is mapped. - -Note: - The node name before '@' must be "isa" to represent the binding stick to the - ISA/EISA binding specification. - -Example: - -isa@a01b0000 { - compatible = "hisilicon,hip06-lpc"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml new file mode 100644 index 000000000000000..3b36e683bb1511d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP06 Low Pin Count device + +maintainers: + - Wei Xu + +description: | + Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which + provides I/O access to some legacy ISA devices. + HiP06 is based on arm64 architecture where there is no I/O space. So, the + I/O ports here are not CPU addresses, and there is no 'ranges' property in + LPC device node. + +properties: + $nodename: + pattern: '^isa@[0-9a-f]+$' + description: | + The node name before '@' must be "isa" to represent the binding stick + to the ISA/EISA binding specification. + + compatible: + enum: + - hisilicon,hip06-lpc + - hisilicon,hip07-lpc + + reg: + maxItems: 1 + + '#address-cells': + const: 2 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + isa@a01b0000 { + compatible = "hisilicon,hip06-lpc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xa01b0000 0x1000>; + + ipmi0: bt@e4 { + compatible = "ipmi-bt"; + device_type = "ipmi"; + reg = <0x01 0xe4 0x04>; + }; + }; +...