From patchwork Mon Sep 28 06:39:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 313634 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3047042ilg; Sun, 27 Sep 2020 23:39:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyK6jvI6UDjvy1wxMd0pgzlo9x/PDiWlwqisiOIJeQeQVtMVF3D4vF1nGDsQygHpjCuaSQF X-Received: by 2002:a50:cc9a:: with SMTP id q26mr158221edi.64.1601275190949; Sun, 27 Sep 2020 23:39:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601275190; cv=none; d=google.com; s=arc-20160816; b=d035Q1Ovn+qigfk4616zVBdYg9jBG09gHOmZ905d18GJI0NUep3WfBairJ8O/r8e0T PYUd8R0Lnye0unfVFjS0L8afYw7Me6248eHvMyACU4LBL0o1GZ1PK0Qm/oiqkeO5YLQb kwnxhCLJNMCik9KSi8mF5KryuxIBwksMzKd18hGqRjC37VY+V3qBEvA+UdjCs522z9xa aU6959gidKwEyWtxBOMpnauD1c7WRWQO+lnUzPwAyUdE4T1RHNXFHta5YbfkNGfWFwqm EcBO2IA5sG5vpFIPzTK6ZzzQIoYo09G9QZfLtwO3kJtFuyRwGrLpBnnybD45kXc5yqEA cvjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=85unnZJhyI+scHoIxruVD24vC/qQPy3VUMvy4L1fLlQ=; b=SoDFGgtu22njvj2g5fUWlaSeJ+pGRq64R+3PJdZUxl19WiVJihl/Scu5yHVSB6HTgM THMfIek6UNzCkJW2kwvOOGPb33T60xc6thDcCXliW9f1uSUBaDjGYNFpswmE2zPzdlS6 yqJSDcCEaPzxTQorIQxsDD1SfAzMrExHjO4IDOEQJZ2yFBaCeCqXC5F5HWHimyAQEDZH /9VrOuxQuPMwfBYZReEodkcG83Biq/S3Yhd79cukO5TrG9O3EVH4S3XaHdBmZkp6ebCw iWaxpPhl03E0E2nEDqagfk/MCH14j+lqL1Qh2RRYIRUgFU0jkYXh7FqK8cfWpjptw3uQ fCtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ik+yoNMz; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p25si7086041edw.585.2020.09.27.23.39.50; Sun, 27 Sep 2020 23:39:50 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ik+yoNMz; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726655AbgI1Gjt (ORCPT + 6 others); Mon, 28 Sep 2020 02:39:49 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:43972 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726651AbgI1Gjs (ORCPT ); Mon, 28 Sep 2020 02:39:48 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08S6dMg2126278; Mon, 28 Sep 2020 01:39:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1601275162; bh=85unnZJhyI+scHoIxruVD24vC/qQPy3VUMvy4L1fLlQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ik+yoNMzwDTQNENweQtvlHkvPwnIOJkCxMFA/5wSE5Wefd29wNumgGTch569B2M8j gWTp8exdcXkPIpI3v8LOQPm1Zc3NQ/adAN79eM/QfkwAKdDan85Ks2MZCP/+nF64+L hflyhpCNJsZbMTWgVIYBohF7NA6MUy31iX5vdo/I= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08S6dMCH021948 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 28 Sep 2020 01:39:22 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 28 Sep 2020 01:39:22 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 28 Sep 2020 01:39:21 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08S6dG3e111672; Mon, 28 Sep 2020 01:39:19 -0500 From: Peter Ujfalusi To: , , , , , , , CC: , , Subject: [PATCH 1/2] dt-bindings: irqchip: ti, sci-inta: Update for unmapped event handling Date: Mon, 28 Sep 2020 09:39:29 +0300 Message-ID: <20200928063930.12012-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200928063930.12012-1-peter.ujfalusi@ti.com> References: <20200928063930.12012-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The new DMA architecture introduced with AM64 introduced new event types: unampped events. These events are mapped within INTA in contrast to other K3 devices where the events with similar function was originating from the UDMAP or ringacc. The ti,unmapped-event-sources should contain phandle array to the devices in the system (typically DMA controllers) from where the unmapped events originate. Signed-off-by: Peter Ujfalusi --- .../bindings/interrupt-controller/ti,sci-inta.yaml | 5 +++++ 1 file changed, 5 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml index c7cd05656a3e..2837b90bbb56 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml @@ -70,6 +70,11 @@ properties: - description: | "limit" specifies the limit for translation + ti,unmapped-event-sources: + $ref: /schemas/types.yaml#definitions/phandle-array + description: + Array of phandles to DMA controllers where the unmapped events originate. + required: - compatible - reg From patchwork Mon Sep 28 06:39:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 313633 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3047017ilg; Sun, 27 Sep 2020 23:39:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxYxDykQ5NCwUbaSBFr7STLr1fJG1RxWRsE9irSjGmWjvhCEaIVyO+H3OOg9RSU0D4WRd05 X-Received: by 2002:a17:906:2c14:: with SMTP id e20mr236137ejh.205.1601275188053; Sun, 27 Sep 2020 23:39:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601275188; cv=none; d=google.com; s=arc-20160816; b=gHhKCs0j5DfO9m40xYVUT+P/kCCOyFc/IKHoWymuhK1ETMvRu2wPLlyvt5URHMcPdV cQvFpwac/JC9bX9ktQWhkbey74VWOEYxgLwCba4PGL3L6MYjCCRqrMnL6xGLQRAE9/HM oyChNRf/jYctDfN4weUwqYgruOX7c2JSOteKdZSg1nwWeaIBp0vBfzyI2S/bZfEYrz28 VjdWkD43syrHtbX+krA6Ir0j4LV+b9K6b4o0w5JSLTxYwriM/XTsZVTB9llXr18honSX I2TwD7EL8IrF5htN/ikZa4bWn1+hVYTRFHyHZffqk+OEmM8JNV0zKonKyDJOKrhcMOuy GZMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bG303yFR4uOJmtzhuoEEplC+W0gyVvQTPQNVb5c+C7k=; b=VBJ6wdHLNVn52KNGGJtucrxk2KgBaR8u9um79sdanw5YGs/ZgjHWr/PVklQPu8f9NK XAd5dw0dp/lsgFdq1ke4boxsC9kTCh6OM7X/EqUyMRwDDucQXHYM6sh2fx8irColivdp o53FA9jeX3MG6lBlFm2hQ+X6ENI1fEYojccghMhwdCEbdImVKkGlGxzHcCEp/UjmqPMG C1qr8Do50gMfhGSkG53sFTKcXOkFUXuCmbqpQxDya6PZLSqPgG4BA7MzYnUH7IPla9Q7 kYNsEwEeeqcT3kdRUErWSsXHQTc6Da+Oyci96VOQDG0VtVoO4DjUpuk2ZHC0Gz2YR+fa SZUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MfxwcITO; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j17si59139ejc.26.2020.09.27.23.39.47; Sun, 27 Sep 2020 23:39:48 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MfxwcITO; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726522AbgI1Gjr (ORCPT + 6 others); Mon, 28 Sep 2020 02:39:47 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:43948 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725290AbgI1Gjr (ORCPT ); Mon, 28 Sep 2020 02:39:47 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08S6dPxF126293; Mon, 28 Sep 2020 01:39:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1601275165; bh=bG303yFR4uOJmtzhuoEEplC+W0gyVvQTPQNVb5c+C7k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MfxwcITOMTdeNwqoPVBFK4jMNFlDmQOejEijdESHrKmECXrftrtFFglC+Fyh3JuNy Z2xtbr5g9eO8GylfnL8E8QJ7LmTxNliiWmPSGZErUWhKxFgnEZkUIqxhbuckmfByYU LZSbQ12dEpzD5m5xHqdXskuwi7p1eOSJXJh7TLmE= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08S6dP0k021978 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 28 Sep 2020 01:39:25 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 28 Sep 2020 01:39:24 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 28 Sep 2020 01:39:24 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08S6dG3f111672; Mon, 28 Sep 2020 01:39:22 -0500 From: Peter Ujfalusi To: , , , , , , , CC: , , Subject: [PATCH 2/2] irqchip/ti-sci-inta: Add support for unmapped event handling Date: Mon, 28 Sep 2020 09:39:30 +0300 Message-ID: <20200928063930.12012-3-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200928063930.12012-1-peter.ujfalusi@ti.com> References: <20200928063930.12012-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The DMA (BCDMA/PKTDMA and their rings/flows) events are under the INTA's supervision as unmapped events in AM64. In order to keep the current SW stack working, the INTA driver must replace the dev_id with it's own when a request comes for BCDMA or PKTDMA resources. Implement parsing of the optional "ti,unmapped-event-sources" phandle array to get the sci-dev-ids of the devices where the unmapped events originate. Signed-off-by: Peter Ujfalusi --- drivers/irqchip/irq-ti-sci-inta.c | 72 +++++++++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 4 deletions(-) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/irqchip/irq-ti-sci-inta.c b/drivers/irqchip/irq-ti-sci-inta.c index bc863ef7998d..02914d29140b 100644 --- a/drivers/irqchip/irq-ti-sci-inta.c +++ b/drivers/irqchip/irq-ti-sci-inta.c @@ -85,6 +85,8 @@ struct ti_sci_inta_vint_desc { * @base: Base address of the memory mapped IO registers * @pdev: Pointer to platform device. * @ti_sci_id: TI-SCI device identifier + * @difu_cnt: Number of TI-SCI device identifiers for unmapped events + * @dev_ids_for_unmapped: Pointer to an array of TI-SCI device identifiers */ struct ti_sci_inta_irq_domain { const struct ti_sci_handle *sci; @@ -96,11 +98,33 @@ struct ti_sci_inta_irq_domain { void __iomem *base; struct platform_device *pdev; u32 ti_sci_id; + + int difu_cnt; + u32 *dev_ids_for_unmapped; }; #define to_vint_desc(e, i) container_of(e, struct ti_sci_inta_vint_desc, \ events[i]) +static u16 ti_sci_inta_get_dev_id(struct ti_sci_inta_irq_domain *inta, + u32 hwirq) +{ + u16 dev_id = HWIRQ_TO_DEVID(hwirq); + int i; + + if (inta->difu_cnt == 0) + return dev_id; + + for (i = 0; i < inta->difu_cnt; i++) { + if (dev_id == inta->dev_ids_for_unmapped[i]) { + dev_id = inta->ti_sci_id; + break; + } + } + + return dev_id; +} + /** * ti_sci_inta_irq_handler() - Chained IRQ handler for the vint irqs * @desc: Pointer to irq_desc corresponding to the irq @@ -251,7 +275,7 @@ static struct ti_sci_inta_event_desc *ti_sci_inta_alloc_event(struct ti_sci_inta u16 dev_id, dev_index; int err; - dev_id = HWIRQ_TO_DEVID(hwirq); + dev_id = ti_sci_inta_get_dev_id(inta, hwirq); dev_index = HWIRQ_TO_IRQID(hwirq); event_desc = &vint_desc->events[free_bit]; @@ -352,14 +376,15 @@ static void ti_sci_inta_free_irq(struct ti_sci_inta_event_desc *event_desc, { struct ti_sci_inta_vint_desc *vint_desc; struct ti_sci_inta_irq_domain *inta; + u16 dev_id; vint_desc = to_vint_desc(event_desc, event_desc->vint_bit); inta = vint_desc->domain->host_data; + dev_id = ti_sci_inta_get_dev_id(inta, hwirq); /* free event irq */ mutex_lock(&inta->vint_mutex); inta->sci->ops.rm_irq_ops.free_event_map(inta->sci, - HWIRQ_TO_DEVID(hwirq), - HWIRQ_TO_IRQID(hwirq), + dev_id, HWIRQ_TO_IRQID(hwirq), inta->ti_sci_id, vint_desc->vint_id, event_desc->global_event, @@ -562,7 +587,6 @@ static void ti_sci_inta_msi_set_desc(msi_alloc_info_t *arg, arg->desc = desc; arg->hwirq = TO_HWIRQ(pdev->id, desc->inta.dev_index); } - static struct msi_domain_ops ti_sci_inta_msi_ops = { .set_desc = ti_sci_inta_msi_set_desc, }; @@ -574,6 +598,42 @@ static struct msi_domain_info ti_sci_inta_msi_domain_info = { .chip = &ti_sci_inta_msi_irq_chip, }; +static int ti_sci_inta_get_unmapped_sources(struct ti_sci_inta_irq_domain *inta) +{ + struct device *dev = &inta->pdev->dev; + struct device_node *node = dev_of_node(dev); + struct of_phandle_iterator it; + int count, err, ret, i; + + count = of_count_phandle_with_args(node, "ti,unmapped-event-sources", + NULL); + if (count <= 0) + return count; + + inta->dev_ids_for_unmapped = devm_kcalloc(dev, count, + sizeof(*inta->dev_ids_for_unmapped), + GFP_KERNEL); + if (!inta->dev_ids_for_unmapped) + return -ENOMEM; + + i = 0; + of_for_each_phandle(&it, err, node, "ti,unmapped-event-sources", + NULL, 0) { + ret = of_property_read_u32(it.node, "ti,sci-dev-id", + &inta->dev_ids_for_unmapped[i++]); + if (ret) { + dev_err(dev, "ti,sci-dev-id read failure for %s\n", + of_node_full_name(it.node)); + of_node_put(it.node); + return ret; + } + } + + inta->difu_cnt = count; + + return 0; +} + static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev) { struct irq_domain *parent_domain, *domain, *msi_domain; @@ -629,6 +689,10 @@ static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev) if (IS_ERR(inta->base)) return PTR_ERR(inta->base); + ret = ti_sci_inta_get_unmapped_sources(inta); + if (ret) + return ret; + domain = irq_domain_add_linear(dev_of_node(dev), ti_sci_get_num_resources(inta->vint), &ti_sci_inta_irq_domain_ops, inta);