From patchwork Sun Sep 27 06:21:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313579 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2397862ilg; Sat, 26 Sep 2020 23:27:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyGn5BsR2bPH1kJq+33oGkTsUo3O912ScMtxNMpzL1Jfv1vFcnsQkvps8ykqN1jRwC/MLlO X-Received: by 2002:a17:906:178d:: with SMTP id t13mr10538200eje.410.1601188023142; Sat, 26 Sep 2020 23:27:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188023; cv=none; d=google.com; s=arc-20160816; b=U80iJ3FpMrDg+XFtHdhreLH2fAsyoCWLAWekIi4BHGtjTV/FZ7Zpr1P6GGF9SN+mXf l1ADltMA5uOiCDEj8J5MrAo6vIvuL+hCjjEBon73MLvqhQNi9vS1dCEVD1yQC8mQQupp vUQ/TgwR8xQaJRf27P6nllXXxCGLlFymtN3NUCxowqmSIBmtj+IHZNTPgUd4PEzEIkMe GOQjMllVZNG17TWNOEG/cOm9RTR58hcq8vylRK7237uk7jdvW/S/H/xYsxhYSjBZ+Ihc D+3JPc8MAyQ124BVFrfEjuJ+VADUE0CfApU0CjFYUWLHHUrkMPGlnA6uSqtVSidlYLgd RpIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Ry5EA63CCDQ2v+szzk3KRHtXsegcL8HDbeYvZF90KwM=; b=Z7FGNk2Y4B4X1umUb7N8+I5HK+Rm5Cq+XyUxYFl4oYgsofBeNwUFxY3SlxbWE4Mr7W zJ0/HC9DMJsinErZSW8rojThk6NCeHVwkU6079JZbEEDeCb8adbHZEqarE2a27NV7nKj NfLR7Br9H6J1HG/Y+XN+ahg9+JXhu/teGwd1G7VX824EimNpL7RQ8MEZ5nSIfFrsgvKP LMNDPoNd24j/LijxAh2UVbhXhfJ0Sltnw3Qp5T25SuLqqdzxpXOen40tV8o1rewFsRwb t0GUc3wwd4L/koG+NLws+acNSz0SyqUR6jzjQBGWAIJ5BxpSA4+PCUEZJwwanLKphxdm bGYQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q6si5583044edw.446.2020.09.26.23.27.03; Sat, 26 Sep 2020 23:27:03 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730375AbgI0G04 (ORCPT + 6 others); Sun, 27 Sep 2020 02:26:56 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14288 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729740AbgI0G0y (ORCPT ); Sun, 27 Sep 2020 02:26:54 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id AA2E3BD38244D8610FE3; Sun, 27 Sep 2020 14:26:52 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:41 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 01/21] ARM: dts: remove a unused compatible name in hip01-ca9x2.dts Date: Sun, 27 Sep 2020 14:21:09 +0800 Message-ID: <20200927062129.4573-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The compatible name "hisilicon,hip01" does not exist in any C file, and it is not mentioned in the description file "hisilicon.txt". Delete it. Fixes: 56a9c909d88a ("ARM: dts: Add hip01-ca9x2 dts file") Signed-off-by: Zhen Lei --- arch/arm/boot/dts/hip01-ca9x2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.8.3 diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts index f05e74eacfe0bf2..936acb301c55a10 100644 --- a/arch/arm/boot/dts/hip01-ca9x2.dts +++ b/arch/arm/boot/dts/hip01-ca9x2.dts @@ -17,7 +17,7 @@ / { model = "Hisilicon HIP01 Development Board"; - compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01"; + compatible = "hisilicon,hip01-ca9x2"; cpus { #address-cells = <1>; From patchwork Sun Sep 27 06:21:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313596 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398402ilg; Sat, 26 Sep 2020 23:28:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyW3mMI+dn6xVXYt3BUx7CcYEHdnZj2LaZPIEXu4msqXBR9i+EnkQwDQ4iUZ6SYyPl6KyIs X-Received: by 2002:a17:906:556:: with SMTP id k22mr9963950eja.369.1601188103276; Sat, 26 Sep 2020 23:28:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188103; cv=none; d=google.com; s=arc-20160816; b=aY6JDQPgtriplTnzs/IgXuyahf+PHtCIT7GIqEdP93ZPq+d5jPGgdsmZB66Gl+mkDl eVVhRsNTax5xZZrVAENaRvWh+g08zMx+VBZlO80mt+yFIWLr7jQohvuLRbaBKPbTHlJX Ab0+GYJXBFAHZvieTGDyeIITjhCwhwLwtOqSoaXcprwzUjMwDsxwJMr6pzjk1y23fkr+ Herihf+NBzkFKa262F07Z0RiRmqG3DiemBqRSXfjL1zYM2Cq9oR3ai+ByeoKPUZgiIyb 6wO6fnZ/YqfoTbOvSI1FnceSZ/3PxiabBwM7xmdPlNn9iWndua/S/ULhbF147Q6/28mH HXKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=5d25X3bbwVzr93HR+MB1dOfEdyCfa73m8w3xik/dAik=; b=J6NxE8+Pex3/gPocn6VeL0lDVAo0m7ZMd2X3xWKnIK5idOk4u3f1VfztcjhWIXYII7 KrBqOcJJRVGsdCpejqNbRUY2y2K8ouM/Q0JTkw7wyYFaf0WBlJsVZQX3+qDI9yM4oNrC C2cM7ODwigHjaAeDZccwxqVJR6U+rThpvktoCWBYWaEIYHLJesL7TYZB0YpF3wk/pbzf Ii9OzXdguB06f2E91sw5Kjjx3PzW2jsVG9cnPhttrbmm4Yt/J04s3Jq+23tbMBLrL07s 9ZZp8iA2m7FM6q7AQoI4W73pMe+eKKFLjBp3FJlAmNPuhW7CbQf8CYO9bQQ8TC26UQjW 1sZw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qt16si4926110ejb.352.2020.09.26.23.28.22; Sat, 26 Sep 2020 23:28:23 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730564AbgI0G2K (ORCPT + 6 others); Sun, 27 Sep 2020 02:28:10 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14292 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730374AbgI0G1A (ORCPT ); Sun, 27 Sep 2020 02:27:00 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id B2E988747CC027B6DC56; Sun, 27 Sep 2020 14:26:52 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:42 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 02/21] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file Date: Sun, 27 Sep 2020 14:21:10 +0800 Message-ID: <20200927062129.4573-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Split the devicetree bindings of each Hisilicon controller from hisilicon.txt into a separate file, the file name is the compatible name attach the .txt file name extension. All Hi6220 dedicated controllers are grouped into subdirectory "hi3620". All HiPxx dedicated controllers are grouped into subdirectory "hipxx" Signed-off-by: Zhen Lei --- .../controller/hi3620/hisilicon,hi6220-aoctrl.txt | 18 ++ .../hi3620/hisilicon,hi6220-mediactrl.txt | 18 ++ .../controller/hi3620/hisilicon,hi6220-pmctrl.txt | 18 ++ .../hi3620/hisilicon,hi6220-sramctrl.txt | 16 ++ .../controller/hi3620/hisilicon,hi6220-sysctrl.txt | 19 ++ .../controller/hipxx/hisilicon,hip01-sysctrl.txt | 19 ++ .../hipxx/hisilicon,hip04-bootwrapper.txt | 9 + .../controller/hipxx/hisilicon,hip04-fabric.txt | 5 + .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 + .../hisilicon/controller/hisilicon,dsa-subctrl.txt | 15 ++ .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ++ .../controller/hisilicon,pcie-sas-subctrl.txt | 15 ++ .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 + .../controller/hisilicon,peri-subctrl.txt | 16 ++ .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 ++ .../bindings/arm/hisilicon/hisilicon.txt | 264 +-------------------- 16 files changed, 236 insertions(+), 263 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip01-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.txt new file mode 100644 index 000000000000000..8f70ac0ebbdf252 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Power Always ON domain controller + +Required properties: +- compatible : "hisilicon,hi6220-aoctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power always +on domain for mobile platform. + +Example: + /*for Hi6220*/ + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0x0 0xf7800000 0x0 0x2000>; + #clock-cells = <1>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.txt new file mode 100644 index 000000000000000..95bf5f5c7abed7c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Media domain controller + +Required properties: +- compatible : "hisilicon,hi6220-mediactrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the multimedia +domain(e.g. codec, G3D ...) for mobile platform. + +Example: + /*for Hi6220*/ + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0x0 0xf4410000 0x0 0x1000>; + #clock-cells = <1>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.txt new file mode 100644 index 000000000000000..46f5d8c775cea25 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Power Management domain controller + +Required properties: +- compatible : "hisilicon,hi6220-pmctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, some clock registers are define + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power management +domain for mobile platform. + +Example: + /*for Hi6220*/ + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0x0 0xf7032000 0x0 0x1000>; + #clock-cells = <1>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.txt new file mode 100644 index 000000000000000..963a2cb13a249d9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.txt @@ -0,0 +1,16 @@ +Hisilicon Hi6220 SRAM controller + +Required properties: +- compatible : "hisilicon,hi6220-sramctrl", "syscon" +- reg : Register address and size + +Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several +SRAM banks for power management, modem, security, etc. Further, use "syscon" +managing the common sram which can be shared by multiple modules. + +Example: + /*for Hi6220*/ + sram: sram@fff80000 { + compatible = "hisilicon,hi6220-sramctrl", "syscon"; + reg = <0x0 0xfff80000 0x0 0x12000>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sysctrl.txt new file mode 100644 index 000000000000000..2ded19f26e61a7c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sysctrl.txt @@ -0,0 +1,19 @@ +Hisilicon Hi6220 system controller + +Required properties: +- compatible : "hisilicon,hi6220-sysctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this controller as one of the system controllers, +its main functions are the same as Hisilicon system controller, but +the register offset of some core modules are different. + +Example: + /*for Hi6220*/ + sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip01-sysctrl.txt new file mode 100644 index 000000000000000..7cc52596c82e583 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip01-sysctrl.txt @@ -0,0 +1,19 @@ +Hisilicon HiP01 system controller + +Required properties: +- compatible : "hisilicon,hip01-sysctrl" +- reg : Register address and size + +The HiP01 system controller is mostly compatible with hisilicon +system controller,but it has some specific control registers for +HIP01 SoC family, such as slave core boot, and also some same +registers located at different offset. + +Example: + + /* for hip01-ca9x2 */ + sysctrl: system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.txt new file mode 100644 index 000000000000000..baad98ec700e789 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.txt @@ -0,0 +1,9 @@ +Bootwrapper boot method (software protocol on SMP): + +Required Properties: +- compatible: "hisilicon,hip04-bootwrapper"; +- boot-method: Address and size of boot method. + [0]: bootwrapper physical address + [1]: bootwrapper size + [2]: relocation physical address + [3]: relocation size \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.txt new file mode 100644 index 000000000000000..1709ac91d4cd99c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.txt @@ -0,0 +1,5 @@ +Fabric: + +Required Properties: +- compatible: "hisilicon,hip04-fabric"; +- reg: Address and size of Fabric \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt new file mode 100644 index 000000000000000..0188ec93d2df70d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt @@ -0,0 +1,8 @@ +Hisilicon CPU controller + +Required properties: +- compatible : "hisilicon,cpuctrl" +- reg : Register address and size + +The clock registers and power registers of secondary cores are defined +in CPU controller, especially in HIX5HD2 SoC. \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt new file mode 100644 index 000000000000000..88f81760ddc8621 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt @@ -0,0 +1,15 @@ +Hisilicon HiP05/HiP06 DSA sub system controller + +Required properties: +- compatible : "hisilicon,dsa-subctrl", "syscon"; +- reg : Register address and size + +The DSA sub system controller is shared by peripheral controllers in +HiP05 or HiP06 Soc to implement some basic configurations. + +Example: + /* for HiP05 dsa sub system */ + pcie_sas: system_controller@a0000000 { + compatible = "hisilicon,dsa-subctrl", "syscon"; + reg = <0xa0000000 0x10000>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt new file mode 100644 index 000000000000000..beca239e0830e76 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt @@ -0,0 +1,21 @@ +Hisilicon Hi3798CV200 Peripheral Controller + +The Hi3798CV200 Peripheral Controller controls peripherals, queries +their status, and configures some functions of peripherals. + +Required properties: +- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" + and "simple-mfd". +- reg: Register address and size of Peripheral Controller. +- #address-cells: Should be 1. +- #size-cells: Should be 1. + +Examples: + + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt new file mode 100644 index 000000000000000..43efdaf408f6fe1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt @@ -0,0 +1,15 @@ +Hisilicon HiP05/HiP06 PCIe-SAS sub system controller + +Required properties: +- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; +- reg : Register address and size + +The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in +HiP05 or HiP06 Soc to implement some basic configurations. + +Example: + /* for HiP05 PCIe-SAS sub system */ + pcie_sas: system_controller@b0000000 { + compatible = "hisilicon,pcie-sas-subctrl", "syscon"; + reg = <0xb0000000 0x10000>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt new file mode 100644 index 000000000000000..cb89a217c243066 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt @@ -0,0 +1,13 @@ +PCTRL: Peripheral misc control register + +Required Properties: +- compatible: "hisilicon,pctrl" +- reg: Address and size of pctrl. + +Example: + + /* for Hi3620 */ + pctrl: pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt new file mode 100644 index 000000000000000..95e58d43913c0d9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt @@ -0,0 +1,16 @@ +Hisilicon HiP05/HiP06 PERI sub system controller + +Required properties: +- compatible : "hisilicon,peri-subctrl", "syscon"; +- reg : Register address and size + +The PERI sub system controller is shared by peripheral controllers in +HiP05 or HiP06 Soc to implement some basic configurations. The peripheral +controllers include mdio, ddr, iic, uart, timer and so on. + +Example: + /* for HiP05 sub peri system */ + peri_c_subctrl: syscon@80000000 { + compatible = "hisilicon,peri-subctrl", "syscon"; + reg = <0x0 0x80000000 0x0 0x10000>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt new file mode 100644 index 000000000000000..b62c4c5c0dd0bf8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt @@ -0,0 +1,25 @@ +Hisilicon system controller + +Required properties: +- compatible : "hisilicon,sysctrl" +- reg : Register address and size + +Optional properties: +- smp-offset : offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go +- resume-offset : offset in sysctrl for notifying cpu0 when resume +- reboot-offset : offset in sysctrl for system reboot + +Example: + + /* for Hi3620 */ + sysctrl: system-controller@fc802000 { + compatible = "hisilicon,sysctrl"; + reg = <0xfc802000 0x1000>; + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index a97f643e7d1c760..f7e52476f5f2f3c 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -54,266 +54,4 @@ Required root node properties: HiP07 D05 Board Required root node properties: - - compatible = "hisilicon,hip07-d05"; - -Hisilicon system controller - -Required properties: -- compatible : "hisilicon,sysctrl" -- reg : Register address and size - -Optional properties: -- smp-offset : offset in sysctrl for notifying slave cpu booting - cpu 1, reg; - cpu 2, reg + 0x4; - cpu 3, reg + 0x8; - If reg value is not zero, cpun exit wfi and go -- resume-offset : offset in sysctrl for notifying cpu0 when resume -- reboot-offset : offset in sysctrl for system reboot - -Example: - - /* for Hi3620 */ - sysctrl: system-controller@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi3798CV200 Peripheral Controller - -The Hi3798CV200 Peripheral Controller controls peripherals, queries -their status, and configures some functions of peripherals. - -Required properties: -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" - and "simple-mfd". -- reg: Register address and size of Peripheral Controller. -- #address-cells: Should be 1. -- #size-cells: Should be 1. - -Examples: - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi6220 system controller - -Required properties: -- compatible : "hisilicon,hi6220-sysctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this controller as one of the system controllers, -its main functions are the same as Hisilicon system controller, but -the register offset of some core modules are different. - -Example: - /*for Hi6220*/ - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Always ON domain controller - -Required properties: -- compatible : "hisilicon,hi6220-aoctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power always -on domain for mobile platform. - -Example: - /*for Hi6220*/ - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Media domain controller - -Required properties: -- compatible : "hisilicon,hi6220-mediactrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the multimedia -domain(e.g. codec, G3D ...) for mobile platform. - -Example: - /*for Hi6220*/ - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Management domain controller - -Required properties: -- compatible : "hisilicon,hi6220-pmctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, some clock registers are define - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power management -domain for mobile platform. - -Example: - /*for Hi6220*/ - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 SRAM controller - -Required properties: -- compatible : "hisilicon,hi6220-sramctrl", "syscon" -- reg : Register address and size - -Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several -SRAM banks for power management, modem, security, etc. Further, use "syscon" -managing the common sram which can be shared by multiple modules. - -Example: - /*for Hi6220*/ - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; - ------------------------------------------------------------------------ -Hisilicon HiP01 system controller - -Required properties: -- compatible : "hisilicon,hip01-sysctrl" -- reg : Register address and size - -The HiP01 system controller is mostly compatible with hisilicon -system controller,but it has some specific control registers for -HIP01 SoC family, such as slave core boot, and also some same -registers located at different offset. - -Example: - - /* for hip01-ca9x2 */ - sysctrl: system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller - -Required properties: -- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; -- reg : Register address and size - -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 PCIe-SAS sub system */ - pcie_sas: system_controller@b0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0xb0000000 0x10000>; - }; - -Hisilicon HiP05/HiP06 PERI sub system controller - -Required properties: -- compatible : "hisilicon,peri-subctrl", "syscon"; -- reg : Register address and size - -The PERI sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. The peripheral -controllers include mdio, ddr, iic, uart, timer and so on. - -Example: - /* for HiP05 sub peri system */ - peri_c_subctrl: syscon@80000000 { - compatible = "hisilicon,peri-subctrl", "syscon"; - reg = <0x0 0x80000000 0x0 0x10000>; - }; - -Hisilicon HiP05/HiP06 DSA sub system controller - -Required properties: -- compatible : "hisilicon,dsa-subctrl", "syscon"; -- reg : Register address and size - -The DSA sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 dsa sub system */ - pcie_sas: system_controller@a0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0xa0000000 0x10000>; - }; - ------------------------------------------------------------------------ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. - ------------------------------------------------------------------------ -PCTRL: Peripheral misc control register - -Required Properties: -- compatible: "hisilicon,pctrl" -- reg: Address and size of pctrl. - -Example: - - /* for Hi3620 */ - pctrl: pctrl@fca09000 { - compatible = "hisilicon,pctrl"; - reg = <0xfca09000 0x1000>; - }; - ------------------------------------------------------------------------ -Fabric: - -Required Properties: -- compatible: "hisilicon,hip04-fabric"; -- reg: Address and size of Fabric - ------------------------------------------------------------------------ -Bootwrapper boot method (software protocol on SMP): - -Required Properties: -- compatible: "hisilicon,hip04-bootwrapper"; -- boot-method: Address and size of boot method. - [0]: bootwrapper physical address - [1]: bootwrapper size - [2]: relocation physical address - [3]: relocation size + - compatible = "hisilicon,hip07-d05"; \ No newline at end of file From patchwork Sun Sep 27 06:21:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313588 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398168ilg; Sat, 26 Sep 2020 23:27:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzIPreKCLf/3UVrTyWS7cuhzMqnAM80t3yntdcNsyY7t7bLyoDcuPZeO/Ir+DGvHQf3MM9L X-Received: by 2002:a17:906:934f:: with SMTP id p15mr10339239ejw.497.1601188066121; Sat, 26 Sep 2020 23:27:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188066; cv=none; d=google.com; s=arc-20160816; b=yYRzp/ht5A+Syh8Pr3PWbNQNGfFo27zz0CQZkKjo7uWn9s8eWG5dfI2JCAjxVxC500 PukeVf0MDtgbn2AbyEWh/6FHl8+sdqIbQtEW/Pu5HlVpOvfJBivRW5ZiKDze3luwwfgo JkMq3lXAlTg7rHF0ofIssQtG9ec2ND1zeeI9oNBZNVqFsnncTS/q3rZEhcSQWxfibyDi DdZKHspivABZve+XTUuI7KGNYw+HQ3fDBKH+sYksrarlN3ODCDiNnq8lavO05JRRbFBW td3CEuCnvj1YAEjbpsYQXvKgRIUEJGwxJBthMWNYWsSSmulzG67xO6y8TcWJ19FKiCs7 NZVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=vOeokwNhxNhFyFH5tqm2qhjv/YuCUwyCLKd7z+j1TbE=; b=YffMFseM1iAMJ9UuLVT4QnLTOErzOc+6Bv2tppJJE9umfA5Tqfo6mNCIV3LJBhDI1q r3iqFR8cu0iAicoTYWx7r5lCLIR6iG/NBXmoOwVQoEwgMOyWH1WRERiHaqV6mSwdQnb6 Uk4sT45MkmXwhA6KEgsR0NCEuG2XG2P/AMxBCmApvBpkwfC7CX1sBdB+UII/Z1bFa0NM sxGTjSAhWN7GVGiAdTDPpZslmmcBOHEAbIlE/oyI6uVFsmVcEyGIf97qmz6MWmMKbck4 zSFz0LWgEppvX8mpX65S3q/5Jg0cpUCJnN2FR0W/m/u0FGQhOOSqycGotPzuk8Tfm/Ww O6FQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e25si5050492ejb.260.2020.09.26.23.27.45; Sat, 26 Sep 2020 23:27:46 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730506AbgI0G1p (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:45 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14293 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730391AbgI0G1A (ORCPT ); Sun, 27 Sep 2020 02:27:00 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C238D6EC2B1BF2E5D891; Sun, 27 Sep 2020 14:26:52 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:43 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 03/21] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema Date: Sun, 27 Sep 2020 14:21:11 +0800 Message-ID: <20200927062129.4573-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Hisilicon SoC bindings to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/hisilicon.txt | 57 ---------------- .../bindings/arm/hisilicon/hisilicon.yaml | 77 ++++++++++++++++++++++ 2 files changed, 77 insertions(+), 57 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt deleted file mode 100644 index f7e52476f5f2f3c..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ /dev/null @@ -1,57 +0,0 @@ -Hisilicon Platforms Device Tree Bindings ----------------------------------------------------- -Hi3660 SoC -Required root node properties: - - compatible = "hisilicon,hi3660"; - -HiKey960 Board -Required root node properties: - - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; - -Hi3670 SoC -Required root node properties: - - compatible = "hisilicon,hi3670"; - -HiKey970 Board -Required root node properties: - - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; - -Hi3798cv200 SoC -Required root node properties: - - compatible = "hisilicon,hi3798cv200"; - -Hi3798cv200 Poplar Board -Required root node properties: - - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; - -Hi4511 Board -Required root node properties: - - compatible = "hisilicon,hi3620-hi4511"; - -Hi6220 SoC -Required root node properties: - - compatible = "hisilicon,hi6220"; - -HiKey Board -Required root node properties: - - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; - -HiP01 ca9x2 Board -Required root node properties: - - compatible = "hisilicon,hip01-ca9x2"; - -HiP04 D01 Board -Required root node properties: - - compatible = "hisilicon,hip04-d01"; - -HiP05 D02 Board -Required root node properties: - - compatible = "hisilicon,hip05-d02"; - -HiP06 D03 Board -Required root node properties: - - compatible = "hisilicon,hip06-d03"; - -HiP07 D05 Board -Required root node properties: - - compatible = "hisilicon,hip07-d05"; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml new file mode 100644 index 000000000000000..362decf3b85c6fb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Platforms Device Tree Bindings + +maintainers: + - Wei Xu + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Hi3660 SoC + items: + - const: hisilicon,hi3660 + + - description: HiKey960 Board + items: + - const: hisilicon,hi3660-hikey960 + - const: hisilicon,hi3660 + + - description: Hi3670 SoC + items: + - const: hisilicon,hi3670 + + - description: HiKey970 Board + items: + - const: hisilicon,hi3670-hikey970 + - const: hisilicon,hi3670 + + - description: Hi3798cv200 SoC + items: + - const: hisilicon,hi3798cv200 + + - description: Hi3798cv200 Poplar Board + items: + - const: hisilicon,hi3798cv200-poplar + - const: hisilicon,hi3798cv200 + + - description: Hi4511 Board + items: + - const: hisilicon,hi3620-hi4511 + + - description: Hi6220 SoC + items: + - const: hisilicon,hi6220 + + - description: HiKey Board + items: + - const: hisilicon,hi6220-hikey + - const: hisilicon,hi6220 + + - description: HiP01 ca9x2 Board + items: + - const: hisilicon,hip01-ca9x2 + + - description: HiP04 D01 Board + items: + - const: hisilicon,hip04-d01 + + - description: HiP05 D02 Board + items: + - const: hisilicon,hip05-d02 + + - description: HiP06 D03 Board + items: + - const: hisilicon,hip06-d03 + + - description: HiP07 D05 Board + items: + - const: hisilicon,hip07-d05 +... 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[23.128.96.18]) by mx.google.com with ESMTP id q6si5583044edw.446.2020.09.26.23.27.10; Sat, 26 Sep 2020 23:27:10 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730380AbgI0G05 (ORCPT + 6 others); Sun, 27 Sep 2020 02:26:57 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14290 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730358AbgI0G0z (ORCPT ); Sun, 27 Sep 2020 02:26:55 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id B9477E691A92D26497EE; Sun, 27 Sep 2020 14:26:52 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:43 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 04/21] dt-bindings: arm: hisilicon: add binding for SD5203 SoC Date: Sun, 27 Sep 2020 14:21:12 +0800 Message-ID: <20200927062129.4573-5-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree binding for Hisilicon SD5203 SoC. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml | 4 ++++ 1 file changed, 4 insertions(+) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml index 362decf3b85c6fb..bf5a66bb5885d04 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml @@ -74,4 +74,8 @@ properties: - description: HiP07 D05 Board items: - const: hisilicon,hip07-d05 + + - description: SD5203 SoC + items: + - const: hisilicon,sd5203 ... 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[23.128.96.18]) by mx.google.com with ESMTP id a10si4787191ejy.454.2020.09.26.23.28.11; Sat, 26 Sep 2020 23:28:11 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730562AbgI0G2K (ORCPT + 6 others); Sun, 27 Sep 2020 02:28:10 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14294 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730372AbgI0G06 (ORCPT ); Sun, 27 Sep 2020 02:26:58 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id CEC84D0412295B5696DD; Sun, 27 Sep 2020 14:26:52 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:44 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 05/21] ARM: hisi: add support for SD5203 SoC Date: Sun, 27 Sep 2020 14:21:13 +0800 Message-ID: <20200927062129.4573-6-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Enable support for the Hisilicon SD5203 SoC. The core is ARM926EJ-S. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/mach-hisi/Kconfig | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 1.8.3 diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 3b010fe7c0e9b48..2e980f834a6aa1b 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only config ARCH_HISI bool "Hisilicon SoC Support" - depends on ARCH_MULTI_V7 + depends on ARCH_MULTI_V7 || ARCH_MULTI_V5 select ARM_AMBA - select ARM_GIC + select ARM_GIC if ARCH_MULTI_V7 select ARM_TIMER_SP804 select POWER_RESET select POWER_RESET_HISI @@ -15,6 +15,7 @@ menu "Hisilicon platform type" config ARCH_HI3xxx bool "Hisilicon Hi36xx family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -25,6 +26,7 @@ config ARCH_HI3xxx config ARCH_HIP01 bool "Hisilicon HIP01 family" + depends on ARCH_MULTI_V7 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ARM_GLOBAL_TIMER @@ -33,6 +35,7 @@ config ARCH_HIP01 config ARCH_HIP04 bool "Hisilicon HiP04 Cortex A15 family" + depends on ARCH_MULTI_V7 select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select MCPM if SMP @@ -43,6 +46,7 @@ config ARCH_HIP04 config ARCH_HIX5HD2 bool "Hisilicon X5HD2 family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -50,6 +54,14 @@ config ARCH_HIX5HD2 select PINCTRL_SINGLE help Support for Hisilicon HIX5HD2 SoC family + +config ARCH_SD5203 + bool "Hisilicon SD5203 family" + depends on ARCH_MULTI_V5 + select DW_APB_ICTL + help + Support for Hisilicon SD5203 SoC family + endmenu endif From patchwork Sun Sep 27 06:21:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313598 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398421ilg; Sat, 26 Sep 2020 23:28:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyrdhjOxswUJWYa+EM0Nmzftrfp0qgvNm2SAIAKT11F468+gBu+uKrLXa2mGd4iNofIArSg X-Received: by 2002:a05:6402:8:: with SMTP id d8mr9349957edu.15.1601188106497; Sat, 26 Sep 2020 23:28:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188106; cv=none; d=google.com; s=arc-20160816; b=JZ4yL0cDbM+woBJFhj7xWf0OqMk8aVPhrTZV+x0Jt9GChAECkeXjFT4uy+deKVIcu5 6oIZsixHHy0BIkw9VldJELrAfagT39+qmB2EXVWiZqmg0Gza83cAIAd0Wr/4NKdPcMdI 67kqmc/I0LN0ArUNUww6X1BRVfw5uQ2gAAnSQs1rCriVGaCdaDnxRcS7JqkCE4/64HM9 78G91Ycz8APG85vF8aEGd3Wnt7av+dNBA36aljesebA2ZaY8JHPkA60S2RuB28FYgvUn b1E5ZBVKcX5nz8rVDrQwEmzQtU0grwnAYebpP+t7dUJoChNeqk/OG3UZOdc01pq6ttJn X1CQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=vBY6HV1Qej/RJ01qRTL+9wLFWIqsKm76YvTE5EBi5y0=; b=QnCct7mvchLQqo9mztd46Y7Ob2y2NCeKjkh/tl0NjD/YC1cXyZzs+czjdRhsmG8Rp4 n7BrPa2edWfLo8KcOHgLVA3igomob2xKcsvyHt/JNu/hWTzn4adb+WQcnyyD2EaPr1HA 79K+p1vqgbRjp0FjX/GkuVEBlmaGxu2YxC3qq0zDxQN/Glpsb8OxIIh4S7rDKhqXMUxL p89eCddTf7E1IaRe4NR4X0DIgu312OpQFF3DVBswluvNJFWNHtYp3Za7KlS6u+jiE1eT nH/sBVO7h47R2L21OXYRQ4l8exI9fpPxQUSH7lC7Ttzg5LC6Vhl0e9W185hH+t1KeewQ wfzQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qt16si4926110ejb.352.2020.09.26.23.28.26; Sat, 26 Sep 2020 23:28:26 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730369AbgI0G04 (ORCPT + 6 others); Sun, 27 Sep 2020 02:26:56 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14286 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730259AbgI0G0z (ORCPT ); Sun, 27 Sep 2020 02:26:55 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A5B6EC350B4D75A769FF; Sun, 27 Sep 2020 14:26:52 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:44 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 06/21] ARM: debug: add UART early console support for SD5203 Date: Sun, 27 Sep 2020 14:21:14 +0800 Message-ID: <20200927062129.4573-7-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Add support of early console for SD5203. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/Kconfig.debug | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) -- 1.8.3 diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 80000a66a4e3549..d27a7764c3bfb46 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1086,6 +1086,14 @@ choice on SA-11x0 UART ports. The kernel will check for the first enabled UART in a sequence 3-1-2. + config DEBUG_SD5203_UART + bool "Hisilicon SD5203 Debug UART" + depends on ARCH_SD5203 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on SD5203 UART. + config DEBUG_SOCFPGA_UART0 depends on ARCH_SOCFPGA bool "Use SOCFPGA UART0 for low-level debug" @@ -1639,6 +1647,7 @@ config DEBUG_UART_PHYS default 0x11006000 if DEBUG_MT6589_UART0 default 0x11009000 if DEBUG_MT8135_UART3 default 0x16000000 if DEBUG_INTEGRATOR + default 0x1600d000 if DEBUG_SD5203_UART default 0x18000300 if DEBUG_BCM_5301X default 0x18000400 if DEBUG_BCM_HR2 default 0x18010000 if DEBUG_SIRFATLAS7_UART0 @@ -1841,7 +1850,7 @@ config DEBUG_UART_VIRT default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1 default 0xfec90000 if DEBUG_RK32_UART2 default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 - default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 + default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART default 0xfed60000 if DEBUG_RK29_UART0 default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 From patchwork Sun Sep 27 06:21:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313591 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398192ilg; Sat, 26 Sep 2020 23:27:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzxwfvA/hmJkXZCfEvJEcd6Sddi3dSUeOyjcPyAmazPexwr6BQEyfYlcAJSPc8RGqCI10fO X-Received: by 2002:aa7:d043:: with SMTP id n3mr9314167edo.243.1601188068587; Sat, 26 Sep 2020 23:27:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188068; cv=none; d=google.com; s=arc-20160816; b=gbK1XdcXTdd36BRvGCcr5A7El4lFbe6umH6qxU5r0eyRfQChBmCKLU113H/7En483K cgKUrDizwgLDS4+3ffUiBjFAipk5qHO7gNvkBO8PULWotHS+PJqIGLH7fW0DgGNfdS8k BTPu2msr+dhel86GwH44TDF2ceHSu8q4XflPnR6i95eiqGEjmN6yCxuwCxnO3X9CkccQ 3liREVLmTUEvEm+v5X/z+tAQsRD8/7OHuG0ylIJ9nFUKqHX8JyAP+TPqTl3eGQpesLM6 iS9A1QYLL5pjI1UVk3AoUBUbPs3SrPP0/+QU1IAbFcOvo3RTPKx2Lt9ibLG+hprqID22 mTzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=eP9Kk2TWGXf3Fp1/uhi3NrjPJNNPWX/aTD0AhgZAW7o=; b=y7oBKWB6FKMuBolNoAUi0aTyYlVPmkyGBSPAWjjpu8CPPP0bvsMBYIz7zZ3FPMgYUo SwZTb8FbsUIjy/pEgsj2GZ7GECpLtv8rqmSEP9baKSOPalGguecnMTOCRrzaEpt5u0ju DeVj3m7owSwJjplt9c+TYDRHStrvZRBhPpBHAQ4VDIBGZOv2TkmKy426Loj/JdJZUwA3 KIbPjwEugqqd3Wc3sPHKX3me3Kxis7QuLWzJbkz/As7pNth8lYczJUCAfeQUSlpxeg2J gvVreCFDxw1cT9BYvAcrRSghBZv+IMu03a6kCl1DxH2IOT15bjglwTMX279E/vaRCcG/ wNDw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q4si5121274ejd.380.2020.09.26.23.27.48; Sat, 26 Sep 2020 23:27:48 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730513AbgI0G1p (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:45 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14291 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730373AbgI0G1A (ORCPT ); Sun, 27 Sep 2020 02:27:00 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id BD7182C97A4C1F043FD1; Sun, 27 Sep 2020 14:26:52 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:45 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 07/21] ARM: dts: add SD5203 dts Date: Sun, 27 Sep 2020 14:21:15 +0800 Message-ID: <20200927062129.4573-8-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Add sd5203.dts for Hisilicon SD5203 SoC platform. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sd5203.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 arch/arm/boot/dts/sd5203.dts -- 1.8.3 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae302..1d1262df5c55907 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \ mps2-an399.dtb dtb-$(CONFIG_ARCH_MOXART) += \ moxart-uc7112lx.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb dtb-$(CONFIG_SOC_IMX1) += \ imx1-ads.dtb \ imx1-apf9328.dtb diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts new file mode 100644 index 000000000000000..41113a46a71a584 --- /dev/null +++ b/arch/arm/boot/dts/sd5203.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 Hisilicon Limited. + * + * DTS file for Hisilicon SD5203 Board + */ + +/dts-v1/; + +/ { + model = "Hisilicon SD5203"; + compatible = "hisilicon,sd5203"; + interrupt-parent = <&vic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + }; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + refclk125mhz: refclk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + timer0: timer@16002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16002000 0x1000>; + interrupts = <4>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + timer1: timer@16003000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16003000 0x1000>; + interrupts = <5>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + uart0: serial@1600d000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600d000 0x1000>; + bus_id = "uart0"; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <17>; + }; + + uart1: serial@1600c000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600c000 0x1000>; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <16>; + status = "disabled"; + }; + }; +}; From patchwork Sun Sep 27 06:21:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313592 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398285ilg; Sat, 26 Sep 2020 23:28:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzJSyjMcsV6OA1rLLzRCNCH9zxJLHocWGmoxylP16RdWbiG4P8UJOahH3EdDtzS2Uvm7H2s X-Received: by 2002:a17:906:1c03:: with SMTP id k3mr10590025ejg.259.1601188083536; Sat, 26 Sep 2020 23:28:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188083; cv=none; d=google.com; s=arc-20160816; b=Sr785sedjdrYrqtsrJaXnDFx+ZltnIRcBVBonRDU6pLpaYhqJXRpk9moWWVGcD1ezt 5qFQepoO4OtGULTPT7gN/hw9xInq5lTkAc7oM3YDpLRo+IdUo5oooEQ9dB4eRNZJ3KhK OBD9L3mr7eJ+TVKxZUkiI2toyT5nL7o4em/rX09Qma1cVnK2mNvkmqNpOzg8jqJzHLSN WUqKr2q29DFa2Oh5TcP+R+4Futh6wSOphwrNRN25sKuc8GkEDKkijoHKCxp27dO/+beh 3Azzo2a2ko7eP25k92wlffTwBLj84d9zlRBGc0q6mBQ2OM2rcybpxgymXFU2g7jwLZpc 0bSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=deZjefr9F24CYiGm4fQ4ZmsDpI1/z1S7Hsq3zbpkHu4=; b=lLU9p7KGZoelCwtgT+q+8JmnpKHWe9F+md6bbSX5LkPXz7aY9J2vwbJq5JDqQALplQ cGg5TI5I7GciNu7d3tzA3+derUtIh8HG6Vdz725PSVOlX4iaU2A8OD+glYruNazAQmhF bklENVME+sIwV8P1Xsi1VTH4mAWPhXp/XE7pI4TF6zSClPp56pnZ0NfhR8d8kwO5ArrV C8qARZDuOtPaKUHOOFMKGhb4sIk4iiInRDZSBsJr1Ox32Ua4GPH9KhLyyBpFGhed/JDT eZITXmQcG2gMhCMBDdJLqkfNCYjWTLj/63wrDB4bgKsxKJvPfG7NhpOLt9xY+kFYFYA+ d3dg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p21si5481358edq.151.2020.09.26.23.28.03; Sat, 26 Sep 2020 23:28:03 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730544AbgI0G2C (ORCPT + 6 others); Sun, 27 Sep 2020 02:28:02 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14285 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729125AbgI0G1A (ORCPT ); Sun, 27 Sep 2020 02:27:00 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 9A9B1E2D971222C62541; Sun, 27 Sep 2020 14:26:52 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:45 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 08/21] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema Date: Sun, 27 Sep 2020 14:21:16 +0800 Message-ID: <20200927062129.4573-9-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon system controller and its variants binding to DT schema format using json-schema. All of them are grouped into one yaml file, to help users understand differences and avoid repeated descriptions. Signed-off-by: Zhen Lei --- .../controller/hi3620/hisilicon,hi6220-sysctrl.txt | 19 ---- .../controller/hipxx/hisilicon,hip01-sysctrl.txt | 19 ---- .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 ----- .../hisilicon/controller/hisilicon,sysctrl.yaml | 115 +++++++++++++++++++++ .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 --- 5 files changed, 115 insertions(+), 77 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip01-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sysctrl.txt deleted file mode 100644 index 2ded19f26e61a7c..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sysctrl.txt +++ /dev/null @@ -1,19 +0,0 @@ -Hisilicon Hi6220 system controller - -Required properties: -- compatible : "hisilicon,hi6220-sysctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this controller as one of the system controllers, -its main functions are the same as Hisilicon system controller, but -the register offset of some core modules are different. - -Example: - /*for Hi6220*/ - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip01-sysctrl.txt deleted file mode 100644 index 7cc52596c82e583..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip01-sysctrl.txt +++ /dev/null @@ -1,19 +0,0 @@ -Hisilicon HiP01 system controller - -Required properties: -- compatible : "hisilicon,hip01-sysctrl" -- reg : Register address and size - -The HiP01 system controller is mostly compatible with hisilicon -system controller,but it has some specific control registers for -HIP01 SoC family, such as slave core boot, and also some same -registers located at different offset. - -Example: - - /* for hip01-ca9x2 */ - sysctrl: system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt deleted file mode 100644 index b62c4c5c0dd0bf8..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt +++ /dev/null @@ -1,25 +0,0 @@ -Hisilicon system controller - -Required properties: -- compatible : "hisilicon,sysctrl" -- reg : Register address and size - -Optional properties: -- smp-offset : offset in sysctrl for notifying slave cpu booting - cpu 1, reg; - cpu 2, reg + 0x4; - cpu 3, reg + 0x8; - If reg value is not zero, cpun exit wfi and go -- resume-offset : offset in sysctrl for notifying cpu0 when resume -- reboot-offset : offset in sysctrl for system reboot - -Example: - - /* for Hi3620 */ - sysctrl: system-controller@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml new file mode 100644 index 000000000000000..b65807574d92f95 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon system controller + +maintainers: + - Wei Xu + +description: | + The Hisilicon system controller is used on many Hisilicon boards, it can be + used to assist the slave core startup, reboot the system, etc. + + There are some variants of the Hisilicon system controller, such as HiP01, + Hi3519, Hi6220 system controller, each of them is mostly compatible with the + Hisilicon system controller, but some same registers located at different + offset. In addition, the HiP01 system controller has some specific control + registers for HIP01 SoC family, such as slave core boot. + + The compatible names of each system controller are as follows: + Hisilicon system controller --> hisilicon,sysctrl + HiP01 system controller --> hisilicon,hip01-sysctrl + Hi6220 system controller --> hisilicon,hi6220-sysctrl + Hi3519 system controller --> hisilicon,hi3519-sysctrl + +allOf: + - if: + properties: + compatible: + contains: + const: hisilicon,hi6220-sysctrl + then: + required: + - '#clock-cells' + +properties: + compatible: + oneOf: + - items: + - const: hisilicon,sysctrl + - items: + - const: hisilicon,sysctrl + - const: syscon + - items: + - const: hisilicon,hip01-sysctrl + - const: hisilicon,sysctrl + - items: + - const: hisilicon,hi6220-sysctrl + - const: syscon + - items: + - const: hisilicon,hi3519-sysctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + smp-offset: + description: | + offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go + $ref: /schemas/types.yaml#/definitions/uint32 + + resume-offset: + description: offset in sysctrl for notifying cpu0 when resume + $ref: /schemas/types.yaml#/definitions/uint32 + + reboot-offset: + description: offset in sysctrl for system reboot + $ref: /schemas/types.yaml#/definitions/uint32 + + '#clock-cells': + description: the number of cells occupied by one clock ID. + const: 1 + +required: + - compatible + - reg + +examples: + - | + /* Hisilicon system controller */ + system-controller@fc802000 { + compatible = "hisilicon,sysctrl"; + reg = <0xfc802000 0x1000>; + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + }; + + /* HiP01 system controller */ + system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; + + /* Hi6220 system controller */ + system-controller@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0xf7030000 0x2000>; + #clock-cells = <1>; + }; + + /* Hi3519 system controller */ + system-controller@12010000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12010000 0x1000>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt deleted file mode 100644 index 8defacc44dd5b9e..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt +++ /dev/null @@ -1,14 +0,0 @@ -* Hisilicon Hi3519 System Controller Block - -This bindings use the following binding: -Documentation/devicetree/bindings/mfd/syscon.yaml - -Required properties: -- compatible: "hisilicon,hi3519-sysctrl". -- reg: the register region of this block - -Examples: -sysctrl: system-controller@12010000 { - compatible = "hisilicon,hi3519-sysctrl", "syscon"; - reg = <0x12010000 0x1000>; -}; From patchwork Sun Sep 27 06:21:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313581 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2397930ilg; Sat, 26 Sep 2020 23:27:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy+TdcZ/gKDnwAXrcZPCx9dSIZb6bMQLTIS2j05xSEoCiG6zWKO4/E1MeFxuXOi9Aslpkjw X-Received: by 2002:a17:906:a101:: with SMTP id t1mr9906414ejy.203.1601188031031; Sat, 26 Sep 2020 23:27:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188031; cv=none; d=google.com; s=arc-20160816; b=MtQHAxbRzKoOYgM8WPhVZoG1AjOo2mgwCiBsQJRkLQn4C0DZVqN+fa5vr7ryhnIJ1W r5MtVZPR/2XO4skLy0vQJvx4xfale36lxok2fwX7FsvjJxV1N53SXQuglnaeAgJA7CrA /za+iJGTodaaepUF4wzRbJBXJhsyXrZUoEoYM8fTSgUdUyT8jkFwqq5qUKxGVgsaNJj9 Z0WL5qtajChx7RHj6N6X2Kbd1gcOiZVpzVvxpSWwWwZd2kv5VhN/FwBGUfuQa/cVw3cN GJ6Y5d2J8tWTm9leLsqgDPTG/Y+Y0lwPBDeF7lyGFQJfj6fzwvonqIEVRhuwKI3Y/7cI ly8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=YwHZm9/TLCKFQwiHlCCYUZy3RSl6CMh2VNhK/d5igEc=; b=kJP628qaFRhmqlByZq5b2dE+KCxSzHoFt09tDqeYiUkU1BUGFbo2XCPHNDeotz2gNi TFNXrViucJO7LWap/V5W2pVDeyl+ntIFXmwrpIXOxtzmwhuzv697gqQoJtOoEI7k389H Fyiv6iPJrrNKNwsDW40c3nGESlpLINStcD7XmZsN9Nrn70MOhgVFopKmQHf61Zf8I1rQ kexFNOv54AvAbG4OszofLQkePa5wKu1LZm9Q2ciKvW+EXakGZ1PQVmQq+Jho098NQR8M M8nlfe7HhA7rrdGwfn7Q0v2mKi7Sw8+97QSkxIm8hFFDvDXsiZv/TO0VRv58gW6dKY9Y XSbw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q6si5583044edw.446.2020.09.26.23.27.10; Sat, 26 Sep 2020 23:27:11 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730419AbgI0G1I (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:08 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14289 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730357AbgI0G05 (ORCPT ); Sun, 27 Sep 2020 02:26:57 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id AE6672F5B8EBA4184497; Sun, 27 Sep 2020 14:26:52 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:46 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 09/21] dt-bindings: arm: hisilicon: convert hisilicon, peri-subctrl bindings to json-schema Date: Sun, 27 Sep 2020 14:21:17 +0800 Message-ID: <20200927062129.4573-10-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon HiP05/HiP06 PERI subsystem controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,peri-subctrl.txt | 16 ---------- .../controller/hisilicon,peri-subctrl.yaml | 34 ++++++++++++++++++++++ 2 files changed, 34 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt deleted file mode 100644 index 95e58d43913c0d9..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt +++ /dev/null @@ -1,16 +0,0 @@ -Hisilicon HiP05/HiP06 PERI sub system controller - -Required properties: -- compatible : "hisilicon,peri-subctrl", "syscon"; -- reg : Register address and size - -The PERI sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. The peripheral -controllers include mdio, ddr, iic, uart, timer and so on. - -Example: - /* for HiP05 sub peri system */ - peri_c_subctrl: syscon@80000000 { - compatible = "hisilicon,peri-subctrl", "syscon"; - reg = <0x0 0x80000000 0x0 0x10000>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml new file mode 100644 index 000000000000000..838b1a2a2c8a9a1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP05/HiP06 PERI subsystem controller + +maintainers: + - Wei Xu + +description: | + The PERI sub system controller is shared by peripheral controllers in + HiP05 or HiP06 Soc to implement some basic configurations. The peripheral + controllers include mdio, ddr, iic, uart, timer and so on. + +properties: + compatible: + items: + - const: hisilicon,peri-subctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +examples: + - | + /* for HiP05 sub peri system */ + peri_c_subctrl: syscon@80000000 { + compatible = "hisilicon,peri-subctrl", "syscon"; + reg = <0x80000000 0x10000>; + }; +... From patchwork Sun Sep 27 06:21:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313599 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398427ilg; Sat, 26 Sep 2020 23:28:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxwxGIgglU3ItBuSBbMYZckEo/180bn5rc34r24/QA0IUqrcfOMmjQBl3DGskp4MWrO7bL8 X-Received: by 2002:a17:906:8508:: with SMTP id i8mr10469076ejx.390.1601188107294; Sat, 26 Sep 2020 23:28:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188107; cv=none; d=google.com; s=arc-20160816; b=RsWldeB6NSHjwZl8h6jyMEPDkr4+w6vApG6AbUrCyIqTe7oCBd5KeaXm6Qbl43JUPQ dEhSBV+KMBe2qnh7jPMP+52EHSBLbx5lAOBZ/EM19Wi3/JmXofVfsD3nBmJdFtxX9CJ+ 7zCxkkBEzzg1SvC4FVmpb07XA8quAPIC11xElyQn7dHGNhdgvd4xWpd1FZDO4ec55ZVJ sEKPT6D/3YizsAq+yf54prwvzMtXyrK8ww1jdFOhs9bpQ69wGKxnhZQ2fi7ld//0eL+j UZd7UQe4IK+VUleWohPFUrIzgDnHUHHpJi26oaCrUIArICBhjE8QcLLquPMSn74ofBX+ 2p2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=bSh9V39hYNs1gXrXSKPLApib7S20dJbG+b/5eYHSR0o=; b=pg77cuw+PgqycCkCYepYt5AVH7cCMQlKV8lx2k+P8sHIAaOIurvO9xmqG4UICQbTXI vtSicVmtur23wvJUkckGwkgwOspxxSF8khkYCOYm+kKa8IFnaGYhOoiJ25WVlHHlOia6 1eaD7MAMt3kJQwhYRMmk5EzkifayMJLa8j3etcaQlWIXo5DxO1/5Yk6Q+ln4DNQD2siT eemawQhN7R5MZ01Ekpb6a4gs4Vcxv0k83LM2S6WEHQfg58xBZ7N91h9AxQ042WElEv2a ILJQfofjMF/G9u2R/mQBs4A9vilC6z5eCj/lcP5PNQRhXgEfpMtx/9tErYqw2aId9dRo f18Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qt16si4926110ejb.352.2020.09.26.23.28.27; Sat, 26 Sep 2020 23:28:27 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730361AbgI0G04 (ORCPT + 6 others); Sun, 27 Sep 2020 02:26:56 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14287 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729713AbgI0G0z (ORCPT ); Sun, 27 Sep 2020 02:26:55 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A0CF8F58B3A948F004C5; Sun, 27 Sep 2020 14:26:52 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:46 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 10/21] dt-bindings: arm: hisilicon: convert hisilicon, pcie-sas-subctrl bindings to json-schema Date: Sun, 27 Sep 2020 14:21:18 +0800 Message-ID: <20200927062129.4573-11-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,pcie-sas-subctrl.txt | 15 --------- .../controller/hisilicon,pcie-sas-subctrl.yaml | 37 ++++++++++++++++++++++ 2 files changed, 37 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt deleted file mode 100644 index 43efdaf408f6fe1..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt +++ /dev/null @@ -1,15 +0,0 @@ -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller - -Required properties: -- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; -- reg : Register address and size - -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 PCIe-SAS sub system */ - pcie_sas: system_controller@b0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0xb0000000 0x10000>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml new file mode 100644 index 000000000000000..8d1341022de587d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller + +maintainers: + - Wei Xu + +description: | + The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in + HiP05 or HiP06 Soc to implement some basic configurations. + +properties: + compatible: + items: + - const: hisilicon,pcie-sas-subctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for HiP05 PCIe-SAS sub system */ + pcie_sas: system_controller@b0000000 { + compatible = "hisilicon,pcie-sas-subctrl", "syscon"; + reg = <0xb0000000 0x10000>; + }; +... \ No newline at end of file From patchwork Sun Sep 27 06:21:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313590 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398176ilg; Sat, 26 Sep 2020 23:27:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwnNQ7y61JlCJjb0roqxHLEmEcxrgLuVQpJu0FAjVqhgGWp8pA1ivGDVQiZsZYS9RMZwlse X-Received: by 2002:a50:d94d:: with SMTP id u13mr9424766edj.365.1601188066875; Sat, 26 Sep 2020 23:27:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188066; cv=none; d=google.com; s=arc-20160816; b=QrR/01twn13R8bnZ+MZXSy3W+fZpkJH8TYgTPry1riJblscan1m9a3pWd5lkGuk53v PgtwzhAei5NuCxfBMvjuV1HFCfJAZjP8labAbIhzJg8L7rTlmSLBXQX+Y2QMcl81bTo6 kf8PGOT2HeoOcyZdalPbc9hJSUQfPp81WS93frMf5DiJ7O1sKkNfEb6cwUSN5DyYIHKd i0QzoyRDLaEOUmXaKN5djdP8wEkQ4JGpFHiK4gW4+0sYAbLxxqqInNJobZTBekFKnBmZ aGhqc6KEdtQ9imutRK6iwD+mWcA7JJu7jUqdVqez5AnqidBoZ+nMcM1sVyPL2oVw/rzj TGRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=bvbno9/OzuoeIRTlC3fAAvz01jlEXXaHH9DfidPALL0=; b=OEMbpHY5bVCHlW+2KWo4f7a3qvn2nybnjbkEbIMWklciStl1S1NNWfDWiSFggszcp6 rKBYAlj6pWmNOnmjfOZtgfhbcbMKqlNSNZfSX7XrsOM57ZECy1wgCEHdE9lFHhKuVGgp 2SfSnQWOrvktsUP0aMXdszF4YhnPcWPWpccBvWEaMKEFaY5cjh6TDTwwXWEabKPB33se JnqW30TLh4HhOKuJBa5Ea4gh1XSJdJYdQGOX4HtwCXyahQT+ElkZv5YlQasp9B2B5DKd MWgMEzVbW/Y0unSkjICkNX6+Jovpved/NDJrOmvxRWlXg+MaiYDWCXtUmfrqvNYUsVB0 n//A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e25si5050492ejb.260.2020.09.26.23.27.46; Sat, 26 Sep 2020 23:27:46 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730511AbgI0G1p (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:45 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14297 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730259AbgI0G1A (ORCPT ); Sun, 27 Sep 2020 02:27:00 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B71CA7A10266CD3EECD7; Sun, 27 Sep 2020 14:26:57 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:47 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 11/21] dt-bindings: arm: hisilicon: convert hisilicon, cpuctrl bindings to json-schema Date: Sun, 27 Sep 2020 14:21:19 +0800 Message-ID: <20200927062129.4573-12-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon CPU controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 ------- .../hisilicon/controller/hisilicon,cpuctrl.yaml | 28 ++++++++++++++++++++++ 2 files changed, 28 insertions(+), 8 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt deleted file mode 100644 index 0188ec93d2df70d..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt +++ /dev/null @@ -1,8 +0,0 @@ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml new file mode 100644 index 000000000000000..6db2da3fe3352da --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,cpuctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon CPU controller + +maintainers: + - Wei Xu + +description: | + The clock registers and power registers of secondary cores are defined + in CPU controller, especially in HIX5HD2 SoC. + +properties: + compatible: + items: + - const: hisilicon,cpuctrl + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg +... \ No newline at end of file From patchwork Sun Sep 27 06:21:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313594 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398328ilg; Sat, 26 Sep 2020 23:28:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy6eDsY5OEqHpBfc8hK3dD8I72TWeSqdoZP4VQvNlR04olLczcXw3aYgSa3mVB+DkqofaKP X-Received: by 2002:aa7:d991:: with SMTP id u17mr9862990eds.11.1601188090734; Sat, 26 Sep 2020 23:28:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188090; cv=none; d=google.com; s=arc-20160816; b=Q5gv40cqAKuvYO2pVXbgZaQa9//DJCeo1NtHySmt4nehn7bLJKZgJu2uw+Vu/CUNwq 0QrwIvd/MjNM6UWFYzbxY+C/eEIL46CBNKILnLGfHWiXW2Y76tGKrCfF0BOfMy1/7aL5 e4ZwfbboHRf/WsumYEVLs++4zeoO6BV+LSR2BPgYT/kt7B2HA8ELJyW37JzoJqpN9Wk9 Zy3VddvVVmmACToHIoXcmzg/DVMmHpIrURKNXUZhiYsTPbuWHl437N9Bnb13wowMAiPw Z3N29sUU2rWbqltKyYj6RGFNqgS/yEPm5TTEgrIOgxQwkv11Rab49SgD/ZelDwQN5ngi fcvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=tlvqJasHnWM3YsAzfl6S110k/DDO7HAQWYxgppw6yjc=; b=LcvlpUy2LreSVVztp4D3xiOlYoOMH9NfvWy/BD3NzXmikizKfPYR6MAkYX6sP7D/8e slZ6elriFEubGzHmYk91QuLEe/u7cmJcKa/N+AG4mEzksE6cGigUfwJUX824XgRWK/vd U82BWeYn+cG4scuJsq+26CVQbBrs5VoEdGq/IQkQDTwVBToeIoAx7siR8nydgCpjqCGm qf8/xIj+fVt/pCZaT9sXau44zK1PbApUKvRc6t9bwdz/EdMgmFKof+arjGRJMdhg//MS rDJ3TUfxIURjw1YnEYjvkYxNgt0wyJ/rleTmDr2ARVAtvf2VTxa1y6ImuywE5O7iB4lQ ZsQA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a10si4787191ejy.454.2020.09.26.23.28.10; Sat, 26 Sep 2020 23:28:10 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729125AbgI0G2K (ORCPT + 6 others); Sun, 27 Sep 2020 02:28:10 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14298 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730396AbgI0G1A (ORCPT ); Sun, 27 Sep 2020 02:27:00 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id BBA8CF15D34F14C1068E; Sun, 27 Sep 2020 14:26:57 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:47 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 12/21] dt-bindings: arm: hisilicon: convert hisilicon, pctrl bindings to json-schema Date: Sun, 27 Sep 2020 14:21:20 +0800 Message-ID: <20200927062129.4573-13-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon peripheral misc control register binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 --------- .../arm/hisilicon/controller/hisilicon,pctrl.yaml | 34 ++++++++++++++++++++++ 2 files changed, 34 insertions(+), 13 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt deleted file mode 100644 index cb89a217c243066..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt +++ /dev/null @@ -1,13 +0,0 @@ -PCTRL: Peripheral misc control register - -Required Properties: -- compatible: "hisilicon,pctrl" -- reg: Address and size of pctrl. - -Example: - - /* for Hi3620 */ - pctrl: pctrl@fca09000 { - compatible = "hisilicon,pctrl"; - reg = <0xfca09000 0x1000>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml new file mode 100644 index 000000000000000..5380f98c5d2c781 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,pctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral misc control register + +maintainers: + - Wei Xu + +description: Peripheral misc control register + +properties: + compatible: + items: + - const: hisilicon,pctrl + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for Hi3620 */ + pctrl: pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; +... \ No newline at end of file From patchwork Sun Sep 27 06:21:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313593 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398317ilg; Sat, 26 Sep 2020 23:28:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMWDU63vSdYaFaum6tuixAcyB+H5QmmTsZ86dTNISASkfbJ+P2PgyUcKf40Gv8r6MGdFij X-Received: by 2002:aa7:d043:: with SMTP id n3mr9315614edo.243.1601188090111; Sat, 26 Sep 2020 23:28:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188090; cv=none; d=google.com; s=arc-20160816; b=pkaTNpspsxbYBHlerzBHJQHchoewUyKD6MqsRURDnHsFXKoNJbJbKxWLcMYnmnoAJ9 Hxhe6zgRe5jUlHG2YkIVROBuACO9/T6gzuVQZGjJ8wuacpNKvZ38Wwoe73k7mWV4/bof FrOLrXYQnCZsYxmhLTzyXCHh7i6KhfgfMZaRbJyKHwBaUeCQ272nQQwTlBRc+/k6u6kS BCg1+2+hiW07Yeg23DtYQrSyFJDOLOGjGYJf6TYazse49wIluXxe3Auuj4VVAKGO86x1 k2o/Pbr7uAoVHF9QviU/sHsCVQ+Umgju6DsuWGL1nQnH2FJJovymPhgAagx7nZ9H86rM IEOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Vt9ONBYUgC7dhtHYmfC3yoaZPTllglzdNg7LLC1wz+Y=; b=bryDSjYIJor1AUS5gAqUhANaBl4fAcu4SI5GBwr6nRSwjDdzyUAFj0k+NjmAeC0OKY gb+9DrLtoWXdo/ST/9UeWnDWq0yCA8VBLRLnMml3yEfF+7risS4SsF8+4jqWIvPjH3xX PEl/kvib6v5YezyYO86ThXBKW/aodG/hWX5WokkgRin1BgdSMBiQcEfgVZgvmsUCuOSD KS29AYWupdPhbzwPx0sNfplGWeRJ5POOThVYW6XQXGwYMFgKKubU6hJKR9Bwoai3gfLk QlU1Vz2VkoSoumuIyDzIZ18j3koE3Ts/4GKnRMfxhxly3KJBm1cpQFFfOX9KqQiUPOs3 vgUw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a10si4787191ejy.454.2020.09.26.23.28.09; Sat, 26 Sep 2020 23:28:10 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730373AbgI0G2C (ORCPT + 6 others); Sun, 27 Sep 2020 02:28:02 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14300 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730407AbgI0G1A (ORCPT ); Sun, 27 Sep 2020 02:27:00 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C48B124BE39FE0B645C5; Sun, 27 Sep 2020 14:26:57 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:48 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 13/21] dt-bindings: arm: hisilicon: convert hisilicon, hi3798cv200-perictrl bindings to json-schema Date: Sun, 27 Sep 2020 14:21:21 +0800 Message-ID: <20200927062129.4573-14-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ---------- .../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 ++++++++++++++++++++++ 2 files changed, 45 insertions(+), 21 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt deleted file mode 100644 index beca239e0830e76..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt +++ /dev/null @@ -1,21 +0,0 @@ -Hisilicon Hi3798CV200 Peripheral Controller - -The Hi3798CV200 Peripheral Controller controls peripherals, queries -their status, and configures some functions of peripherals. - -Required properties: -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" - and "simple-mfd". -- reg: Register address and size of Peripheral Controller. -- #address-cells: Should be 1. -- #size-cells: Should be 1. - -Examples: - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml new file mode 100644 index 000000000000000..8c285f1f1b75e23 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi3798CV200 Peripheral Controller + +maintainers: + - Wei Xu + +description: | + The Hi3798CV200 Peripheral Controller controls peripherals, queries + their status, and configures some functions of peripherals. + +properties: + compatible: + items: + - const: hisilicon,hi3798cv200-perictrl + - const: syscon + - const: simple-mfd + + reg: + description: Register address and size + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + +examples: + - | + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; +... \ No newline at end of file From patchwork Sun Sep 27 06:21:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313589 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398171ilg; Sat, 26 Sep 2020 23:27:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxF8Fo6Q1j0GxAFDhsUEZn1Ieb99r5gd53a+Qexu5oKqfucD2UfwLFT8TSGbDwxm42zFBDM X-Received: by 2002:a50:ef0c:: with SMTP id m12mr9511767eds.264.1601188066512; Sat, 26 Sep 2020 23:27:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188066; cv=none; d=google.com; s=arc-20160816; b=kxFBSY1vhBrRpVH4J8XkMecOiyqNwfXQCGU649MdK5uIghZegMfEdeAvJe7INSBxEg fWY5oXqwMuINemsaR7Nr3/zSo+ixqN3PBNwz/T11wxJhVicfu2I/dc4Rh1246Utkzw+a /VreeDSRO8Clj8TRxv3zPK6NOICpU7SEje9JwWS/0vu0FEiHHBzCbpp3ssqwMOJXgt+P k0FeX3uHm0GHBChDj/zNKHfZX8p7UJxCtyKAarMMTxCEcw1dJD9tAQ/wNbHaQVnDROHU Bu5QgcENeuFk4ps5OMtT6M5aokzwwS34nt1Vyw2U0m0AY9dpGCxTIPLLx65bqgvyvqNO P9mQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=3UwjV0L2Xew+PXu+SiCQh+Tj88fbhVx6a7rFDmDm9D4=; b=hYDqeazK8I0HgP/QdxWEQTWleQl8506zKSHWCm+nVUdHxB9vUCMt42j2UxXH5/rZyi G4IICUhRWfo/dRyWvPGcfMywP+GTyKRcwhfLycqz4Z+gvuw3mO6umDMG2X0tFMHfrfBS p7uBEVpYdYRdjwuE7WXRplOkMGrI5CpGfNyo+NmhqDOkS35ZWK65vbCyXx4U5TZ4GUmW Y4wCKzTlgEtQClO9mzDlINADRRacnHzB+dBlkUxnEjnzGIqduj+nx/X4RbzbtRYdBhqT x3oxv15HI9PxMK6aPn4ENDHfuLoIQVAkZkkvtW3ADQrauImwot+JAOEas1GR5A11IqrB xkgQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e25si5050492ejb.260.2020.09.26.23.27.46; Sat, 26 Sep 2020 23:27:46 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730508AbgI0G1p (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:45 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14296 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730393AbgI0G1A (ORCPT ); Sun, 27 Sep 2020 02:27:00 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B27CDDA9EFB4BC5EB9C9; Sun, 27 Sep 2020 14:26:57 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:49 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 14/21] dt-bindings: arm: hisilicon: convert hisilicon, dsa-subctrl bindings to json-schema Date: Sun, 27 Sep 2020 14:21:22 +0800 Message-ID: <20200927062129.4573-15-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon HiP05/HiP06 DSA subsystem controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../hisilicon/controller/hisilicon,dsa-subctrl.txt | 15 --------- .../controller/hisilicon,dsa-subctrl.yaml | 37 ++++++++++++++++++++++ 2 files changed, 37 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt deleted file mode 100644 index 88f81760ddc8621..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt +++ /dev/null @@ -1,15 +0,0 @@ -Hisilicon HiP05/HiP06 DSA sub system controller - -Required properties: -- compatible : "hisilicon,dsa-subctrl", "syscon"; -- reg : Register address and size - -The DSA sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 dsa sub system */ - pcie_sas: system_controller@a0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0xa0000000 0x10000>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml new file mode 100644 index 000000000000000..f5dabeede5cff26 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP05/HiP06 DSA subsystem controller + +maintainers: + - Wei Xu + +description: | + The DSA sub system controller is shared by peripheral controllers in + HiP05 or HiP06 Soc to implement some basic configurations. + +properties: + compatible: + items: + - const: hisilicon,dsa-subctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for HiP05 dsa sub system */ + pcie_sas: system_controller@a0000000 { + compatible = "hisilicon,dsa-subctrl", "syscon"; + reg = <0xa0000000 0x10000>; + }; +... \ No newline at end of file From patchwork Sun Sep 27 06:21:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313582 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2397959ilg; Sat, 26 Sep 2020 23:27:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy2hmmzXjPgwkf29fw5OPzxo7jAU6JG13JaXF3lNhXygfjBNCT6zepndrCeMAW6N9YCa6QD X-Received: by 2002:aa7:d88a:: with SMTP id u10mr9738787edq.217.1601188035423; Sat, 26 Sep 2020 23:27:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188035; cv=none; d=google.com; s=arc-20160816; b=YBXSq6CnRZ+6wEjRwwEJ6ZCMy6t1KLhyCJPbXheXUDT04RjQDTjbYjG2T1TPWAthw0 Kc24Efl99fzlcaO6Gj9phe1QEnKyRzrpQZF+gTBT6rwKNGQBl6Uwd4pSHI65H1egwnFI OQbOlPB5y5tIn665MSVUUX7aAxK1kF3KgRO3V+MNeDRv8U/NMVEwPKmfrJheTZm2+jzZ GPO845QXu0Pxx2h4KFKHmLE6leILt5nIUSVuRt7xldEBnu9+XQXzPrn6tpbI270s0No4 1fwZah7VPebEBAMbe6+9SYKBooA9jEUG8r23+bUFL4+IGxGzo98g+zidT75GBeGcDZh5 YjZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=JPOc+YYLYhHidFRjooanU2S7MTXp4tsu1alsC/6kk88=; b=OzsRisc0bEjh1qPBXxoVnS4VIgXD8o5j4hVshppZqcow9OLqvsIPkYqy8D17IPHlu9 QzLi5pT1s69gYjgu/4rUturF5RLBhpQw4Wu19LFEP2YX3COBTgdoSkx3dETVvlHfzv/P 88kIyQ1jTw/Q0rohY3+Xk1mBtGSK773PJrNFcCho0JRlOavpmLJZtC8fHlVtmoylh6qA dr7ai5DGO3E1Nn14atBpO/kv5xsDuXpgR9mJPHb/EYeUzQ8xKYxg1e1EvJHH17hwXdei TQceRzOeMjFOZpSL53XLGOwWdIwyrKFfOlemCq4zdcVv/5R1t0iF7LKAwzrr8rWf3LjK 8wsA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bu20si5521192edb.311.2020.09.26.23.27.15; Sat, 26 Sep 2020 23:27:15 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730421AbgI0G1O (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:14 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14301 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730357AbgI0G1M (ORCPT ); Sun, 27 Sep 2020 02:27:12 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C9A547748221436D5460; Sun, 27 Sep 2020 14:26:57 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:49 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 15/21] dt-bindings: arm: hisilicon: convert hisilicon, hip04-fabric bindings to json-schema Date: Sun, 27 Sep 2020 14:21:23 +0800 Message-ID: <20200927062129.4573-16-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Fabric controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hipxx/hisilicon,hip04-fabric.txt | 5 ----- .../controller/hipxx/hisilicon,hip04-fabric.yaml | 26 ++++++++++++++++++++++ 2 files changed, 26 insertions(+), 5 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.txt deleted file mode 100644 index 1709ac91d4cd99c..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.txt +++ /dev/null @@ -1,5 +0,0 @@ -Fabric: - -Required Properties: -- compatible: "hisilicon,hip04-fabric"; -- reg: Address and size of Fabric \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.yaml new file mode 100644 index 000000000000000..ae0a4e68aa8d628 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hipxx/hisilicon,hip04-fabric.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Fabric controller + +maintainers: + - Wei Xu + +description: Hisilicon Fabric controller + +properties: + compatible: + items: + - const: hisilicon,hip04-fabric + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg +... \ No newline at end of file From patchwork Sun Sep 27 06:21:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313586 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398146ilg; Sat, 26 Sep 2020 23:27:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxJfKt57AaVCjMzP/xdBuEGXEChXEP3GSOHsSv0EXYXM9MH7PwKmnA0U4qa/C0Ps88yTTzo X-Received: by 2002:a50:cd51:: with SMTP id d17mr9456722edj.93.1601188064194; Sat, 26 Sep 2020 23:27:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188064; cv=none; d=google.com; s=arc-20160816; b=CYC7wVkDtNo/7Q28QIGJz1p8OeWrMHi7OVSSMhz9sup7hA5mQCS94+ta1gD76GBJZD J2k5IuAtOaBu10Lds9sJ4Fc30PFJ5FxEu3/uCrZzV0JDXiZEk7aM2pilxadQFA+rvGQB DvBqqZ28YgnOeEAfc7LW0ugYFdliARyeRMU7YhAGdSsmz4vs6dq6vLLHsvGTzV2KWXMy 8RAo9wtSU2Eetn03Yoz/V2vrdPHlY/K50CgUOWcXIVft4Pq+L7Ws998PvT0tIRFN7jTr +YQ8/ZuLWRDJQPTOxIpoLnusOvR4b8We4K1bFV77qtzySKtLSssngUH7q+Ki8SxPSHNw ew7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=g3liQk+4gzqszdycqr8zPA2ntClYmH6icuecHMwCI8I=; b=tBBpYER94kTB/ZmfW2FH8KzXygCxC0Kk1Soja1ZxGCG1ksk+kBBJlRgtgVm0Jt2xHl Jq97VemISERoVJDjbllzd68D0LveZjeXSxlX5SowMl9iowYg0iIR0DfY39bDu4AhUc5X qW0PdbQVJUi1WW/3HDqkXeGTZ+M6RAT5yjJmVjjd4TxbjUaMSeBDR70xb5ydwzoAaKQP PEFFvMpwMm6oOR66dhYqPIh7ibf/tsJWHU0f37EueNsCT9f3zk8bW7kON1mjGid19CeE c0XN4siMoPsmWIWLHzH18OKWvrww1Jt8VOD1d07zmm0+ROWX9He40mTcjrB/E3pLr3Px WUOw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e25si5050492ejb.260.2020.09.26.23.27.44; Sat, 26 Sep 2020 23:27:44 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730475AbgI0G1f (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:35 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14299 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730398AbgI0G1B (ORCPT ); Sun, 27 Sep 2020 02:27:01 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C014CC958B1746AE4098; Sun, 27 Sep 2020 14:26:57 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:50 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 16/21] dt-bindings: arm: hisilicon: convert hisilicon, hip04-bootwrapper bindings to json-schema Date: Sun, 27 Sep 2020 14:21:24 +0800 Message-ID: <20200927062129.4573-17-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Bootwrapper boot method binding to DT schema format using json-schema. The property boot-method contains two groups of physical address range information: bootwrapper and relocation. The "uint32-array" type is not suitable for it, because the field "address" and "size" may occupy one or two cells respectively. Use "minItems: 1" and "maxItems: 2" to allow it can be written in "" or ", " format. Signed-off-by: Zhen Lei --- .../hipxx/hisilicon,hip04-bootwrapper.txt | 9 ------ .../hipxx/hisilicon,hip04-bootwrapper.yaml | 32 ++++++++++++++++++++++ 2 files changed, 32 insertions(+), 9 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.txt deleted file mode 100644 index baad98ec700e789..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.txt +++ /dev/null @@ -1,9 +0,0 @@ -Bootwrapper boot method (software protocol on SMP): - -Required Properties: -- compatible: "hisilicon,hip04-bootwrapper"; -- boot-method: Address and size of boot method. - [0]: bootwrapper physical address - [1]: bootwrapper size - [2]: relocation physical address - [3]: relocation size \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.yaml new file mode 100644 index 000000000000000..269ea6c45274bb5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hipxx/hisilicon,hip04-bootwrapper.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bootwrapper boot method + +maintainers: + - Wei Xu + +description: Bootwrapper boot method (software protocol on SMP) + +properties: + compatible: + items: + - const: hisilicon,hip04-bootwrapper + + boot-method: + description: | + Address and size of boot method. + [0]: bootwrapper physical address + [1]: bootwrapper size + [2]: relocation physical address + [3]: relocation size + minItems: 1 + maxItems: 2 + +required: + - compatible + - boot-method +... \ No newline at end of file From patchwork Sun Sep 27 06:21:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313597 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398411ilg; Sat, 26 Sep 2020 23:28:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxaGo3UBXNxzdfWbc+hdyE0yys1DF2ALkkCH0qK1l1LT9h6D2Gij8HQvhC4cmGNQOj7nOhh X-Received: by 2002:a17:906:1909:: with SMTP id a9mr10000977eje.127.1601188104302; Sat, 26 Sep 2020 23:28:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188104; cv=none; d=google.com; s=arc-20160816; b=tXJZcyrWFHwNISgOAv+CpNdNRz0hSu1UMVroR2Y1NVC4FfNeeOqePm4KTXYpDbspLC w9P9Kb58bYxRfiFQYj0iDoKi0IcybLyut7QKUtqgnnR5R3KkA01jowTOiJJGtoMy2voT ThMyAfqdTnQEsAzLABMK4vDT6qsHwaLd8AMlQjg4wjf8z2bPI14w4w554y07zJRiuyOh OyylVy27po3+5L0+sjmfb6BJ1txWgGB1V8FQCyoNiZdl4z7Ggdc6J5mi6bBO2HIme+Kz ml4By5Yw+w1Q7or0WpsAk3y5/o7X1dz8CmBUWhoZy5R7+OFuRNwTPrPujHcPjFycYF76 d3jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Um9fc2s9MUeQBoLZ3xiz0fUgOq/SRkxbUMSqm6eKjVk=; b=y3gqLdw0wjVwa4bg/gdWjNbG3/60c5Q5zXELah6ts3NjNTYSrWIrSw9ky4qjuVyC0V 4Tn4GOOCL+24TdLQ335YVHcIjxNtsjwnIueSbZrvV66SFmWgozUfM1qqoyF/WGExaJ3J Y90NK1PewitHTd+LkcJxyWWwlzRPmwcxgkqe2QYxeKmlrPSlwyiqhIxHnu09s+kwpJxr ZLEeWdW4u8As79bzdOLvfVDzjub4s9P/XWBD0hYIaCSRWAoDD1XBet2ePPlF77eE7V3F COh87yr23YHWNlm5Mn8r7DcNOe4338gHZP/jaOmk82WKXgwAh/0BIkfG+SSNkRxtXsSp P1ig== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qt16si4926110ejb.352.2020.09.26.23.28.24; Sat, 26 Sep 2020 23:28:24 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730559AbgI0G2K (ORCPT + 6 others); Sun, 27 Sep 2020 02:28:10 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14295 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730392AbgI0G1A (ORCPT ); Sun, 27 Sep 2020 02:27:00 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id ADA47A8D8515184FE5C6; Sun, 27 Sep 2020 14:26:57 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:50 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 17/21] dt-bindings: arm: hisilicon: convert hisilicon, hi6220-aoctrl bindings to json-schema Date: Sun, 27 Sep 2020 14:21:25 +0800 Message-ID: <20200927062129.4573-18-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 Power Always ON domain controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hi3620/hisilicon,hi6220-aoctrl.txt | 18 ---------- .../controller/hi3620/hisilicon,hi6220-aoctrl.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.txt deleted file mode 100644 index 8f70ac0ebbdf252..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Power Always ON domain controller - -Required properties: -- compatible : "hisilicon,hi6220-aoctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power always -on domain for mobile platform. - -Example: - /*for Hi6220*/ - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.yaml new file mode 100644 index 000000000000000..9e7c7add1caa469 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3620/hisilicon,hi6220-aoctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 Power Always ON domain controller + +maintainers: + - Wei Xu + +description: | + Hisilicon designs this system controller to control the power always + on domain for mobile platform. + +properties: + compatible: + items: + - const: hisilicon,hi6220-aoctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + - | + /*for Hi6220*/ + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0xf7800000 0x2000>; + #clock-cells = <1>; + }; +... \ No newline at end of file From patchwork Sun Sep 27 06:21:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313587 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398159ilg; Sat, 26 Sep 2020 23:27:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxxgL3e3fHgYLPEhtfpxlkTThUkflc7d02KiBzZzjv6aj9yDkoMbpCo5rTKBdDaDdSYstun X-Received: by 2002:a17:906:660f:: with SMTP id b15mr10497370ejp.333.1601188065475; Sat, 26 Sep 2020 23:27:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188065; cv=none; d=google.com; s=arc-20160816; b=VlfgkyAn191uzUMLGML555tfvy4gWAbOwnzt13gNlf3joEGov3yrBBtsiyyZq067Qm fTlO4bdD0ctWVFTq2WStiX/TyDwPnmAlFSb6nc7A5Dz6NF30CGFvjfUkNkF4qiSroLAR GqTHpUhbZrXVO8zjCD4Yx/bObR2hmBPeTZZl+vjKOTIdJGL561kI3sBWrs6YlqKX+SAZ QxbuCjpVX6H6Ri/4SebXUngphbnc1JD/r0oc9za5TbQJ9sMOIaIv9eIMDY6yiVHJ21tL Xy9o+umXWrd9E+4YLo+yFO4iSS4fFQnEDkjUdKp/V42N1XfEUwWzf8HTUaf6ViSuhCib l1GA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=IUJ6jdBEOQzcah/BkMrtzz77+e+tw4BiITrGDk0J0xw=; b=Nh/aH12vHPf42r3aJQUjMamyPRWP2OulKxcX8UNE07oDr0FnDHRVUkY9pz007FPmYt KD7EBKkSnrjhGLF8spxkQsa8t2DfJ+zLn6Mc4wAawIo561mnxHYzB993rjDNVxh0mw1X 3pDOCSqSlCPgxzkMLtBwvhdIGxN2R+gDtlGOgsst2ycnHOKL/mO0jN+m+w2Z6JDS8OIa ZEPUHa1YRiCGfxGK/16+uE0Me+lnvnwaXOG2+xZAFLQESIoSLlG6dodXY9hguCk0WXHE Rj/yPpaO2VGIUdr+4QEUFdxRIwjjeZTT2YXp/a6XSIPAFz6deN4PtxVa9a19Z70+qz5w vtMQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e25si5050492ejb.260.2020.09.26.23.27.45; Sat, 26 Sep 2020 23:27:45 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730398AbgI0G1o (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:44 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:47988 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730400AbgI0G1B (ORCPT ); Sun, 27 Sep 2020 02:27:01 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id DC26770E4A45D186E326; Sun, 27 Sep 2020 14:26:57 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:51 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 18/21] dt-bindings: arm: hisilicon: convert hisilicon, hi6220-mediactrl bindings to json-schema Date: Sun, 27 Sep 2020 14:21:26 +0800 Message-ID: <20200927062129.4573-19-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 Media domain controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../hi3620/hisilicon,hi6220-mediactrl.txt | 18 ---------- .../hi3620/hisilicon,hi6220-mediactrl.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.txt deleted file mode 100644 index 95bf5f5c7abed7c..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Media domain controller - -Required properties: -- compatible : "hisilicon,hi6220-mediactrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the multimedia -domain(e.g. codec, G3D ...) for mobile platform. - -Example: - /*for Hi6220*/ - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.yaml new file mode 100644 index 000000000000000..1cb6c21a137b87b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3620/hisilicon,hi6220-mediactrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 Media domain controller + +maintainers: + - Wei Xu + +description: | + Hisilicon designs this system controller to control the multimedia + domain(e.g. codec, G3D ...) for mobile platform. + +properties: + compatible: + items: + - const: hisilicon,hi6220-mediactrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + - | + /* for Hi6220 */ + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0xf4410000 0x1000>; + #clock-cells = <1>; + }; +... \ No newline at end of file From patchwork Sun Sep 27 06:21:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313585 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398115ilg; Sat, 26 Sep 2020 23:27:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw4lqVA99GJ3XmAwvTy9JnQFATD8/6hE0KmImwcX++HByV9fsZdaNoAnsQ0XeFAjv7jZasY X-Received: by 2002:aa7:cd85:: with SMTP id x5mr10030457edv.0.1601188055658; Sat, 26 Sep 2020 23:27:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188055; cv=none; d=google.com; s=arc-20160816; b=ghYG28iI6Smsi4y7B+OXEMdR7gbzguLPIKPk+okoG1UikdtzrQhb6XTFK3oBULgjUO TwdOHPQHe3j6PfsruSFJaoz1kFBP0GuCZedCMzbOlIKKngj++IpPJvgT4j19ExJI4sPM qv8mEux1OI+wt11Ont6N9xRc5XDDecyThYoUBSZHbsNokg/nhefSfDT1r5QeSZkDoVGk UgPKLPexBHGjFk7or+7qFrZUJd5frLgPUSKO3oNdJXSAJcESnL67vnPtt+gcxY4jVlvo UCH2o0HimkD1actiVOUkTcpn6s0Tlw/vxwnzv22+1EpTFM5431DNswkxdvMcpE5cFZK2 j4JQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=lR8g3LTZV0+R5n3SHDFm3xmtyAKErU6zq07hsQmMv8Y=; b=Ca/aFcGBbCes6U4jqzThbz6Zdc3HXds8xPaIVJAHi08AT8f6GJp0qFWISMuwft8o6C Jkqdqto10iKu+SeMW1hYsCXzRmyF0RtFEE/Ly/6qHclOCrRj2ZMQDrL9Xmd5clO/uQoF t0q1qvPrszIcyErgRA2P2vb2xpqBYGdO7JxzwumWAcdwC0iJ1LBGE7kitA5Q5hHW4Kcd q5+YMhOFi9oNpsOkDz1dKfYg6+OB2sWGN752V5srCDz65rMHlzkIY0FE2l05RESAz0mS W1FUP6w3wIiOZxq+xtG313W8PmT5Rb8GPah5WUzIOniHMt+utOXsyNN9ysHsPHFPgbuZ vb7g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u16si5331615edr.507.2020.09.26.23.27.35; Sat, 26 Sep 2020 23:27:35 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730460AbgI0G1Y (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:24 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14237 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730358AbgI0G1F (ORCPT ); Sun, 27 Sep 2020 02:27:05 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C300174747B8D1288C3B; Sun, 27 Sep 2020 14:27:02 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:52 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 19/21] dt-bindings: arm: hisilicon: convert hisilicon, hi6220-pmctrl bindings to json-schema Date: Sun, 27 Sep 2020 14:21:27 +0800 Message-ID: <20200927062129.4573-20-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 Power Management domain controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hi3620/hisilicon,hi6220-pmctrl.txt | 18 ---------- .../controller/hi3620/hisilicon,hi6220-pmctrl.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.txt deleted file mode 100644 index 46f5d8c775cea25..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Power Management domain controller - -Required properties: -- compatible : "hisilicon,hi6220-pmctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, some clock registers are define - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power management -domain for mobile platform. - -Example: - /*for Hi6220*/ - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.yaml new file mode 100644 index 000000000000000..5454b43f538c245 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3620/hisilicon,hi6220-pmctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 Power Management domain controller + +maintainers: + - Wei Xu + +description: | + Hisilicon designs this system controller to control the power management + domain for mobile platform. + +properties: + compatible: + items: + - const: hisilicon,hi6220-pmctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + - | + /* for Hi6220 */ + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0xf7032000 0x1000>; + #clock-cells = <1>; + }; +... \ No newline at end of file From patchwork Sun Sep 27 06:21:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313583 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398036ilg; Sat, 26 Sep 2020 23:27:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy24KnVmzypPNzNqTD+deeIFmE+D+GsuKU9+u0fzXja2UPMcZViNvGD8RkM/wtaRjiOX3XE X-Received: by 2002:aa7:ce97:: with SMTP id y23mr9889269edv.128.1601188045458; Sat, 26 Sep 2020 23:27:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188045; cv=none; d=google.com; s=arc-20160816; b=WJ2oWw1lKCiht9VVF454YsqzZM4qA9FORWsO4Vmvv7JvfShNfmeCe0AFi3tOsTYLRV xrU2OvUxT94hV6ppabkBXJvSdOV1Y0ZFnS44ASBfbfu+oQW3OS9Mv5UPZHubMLq1UdAw mjX/5R6t32aRuzxf/bAIKv34u0IOejzaOL4tlswVXc1IoBt0d3smkBaZjb827FBCPyJQ Fg7kzLy3/4AFKstRz+hfE7ZuevHL1Za49ePJkNe4WG4HD0HyKstrsOObaCxkt2XIqS1W L9l3UK731X7hjRV3ir29Ohnz7iWRvXJuhWV0L3miLL36ZFStZf3+sPcaotbsUONkDCEJ 5iDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=lfP9tjWwStY6OZq7LcovOoRnjytNhrowwJiyhZ0pG3A=; b=JnqgzEmmkLle5ZZYUsrbEyq4eZM5bC9DW+Tt3bZouIZzkU/968kKUHhC43ZegIwSda z2DkyfzzE1lrKvebkTpneL/y11HLJJueGDhbbbbT12f8BzEnlZAqO6U9kSZL8+6dqthp A08cD7fftof3v2arvSEzf+SBEYK+IfeHZlS7zoppS4D2i4E3ppEjbz1IOzXm+kD7QZ7v q3BvA2THZ8wcSFE8vYARPPhxok0rBS2hjU7dIoCTR4FwXMBo/DozOht79WH/hDBulNTF yNMyQGkYcRPfabh2mV1zh96/1omQzUGvEwWjEo55wV9jGFed+/t0wT//KZgWzucWd1Ib womw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r27si5180708edw.410.2020.09.26.23.27.25; Sat, 26 Sep 2020 23:27:25 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730456AbgI0G1X (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:23 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14239 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730418AbgI0G1H (ORCPT ); Sun, 27 Sep 2020 02:27:07 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id ED2C6FC572A46CB6871A; Sun, 27 Sep 2020 14:27:02 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:52 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 20/21] dt-bindings: arm: hisilicon: convert hisilicon, hi6220-sramctrl bindings to json-schema Date: Sun, 27 Sep 2020 14:21:28 +0800 Message-ID: <20200927062129.4573-21-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 SRAM controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../hi3620/hisilicon,hi6220-sramctrl.txt | 16 --------- .../hi3620/hisilicon,hi6220-sramctrl.yaml | 38 ++++++++++++++++++++++ 2 files changed, 38 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.txt deleted file mode 100644 index 963a2cb13a249d9..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.txt +++ /dev/null @@ -1,16 +0,0 @@ -Hisilicon Hi6220 SRAM controller - -Required properties: -- compatible : "hisilicon,hi6220-sramctrl", "syscon" -- reg : Register address and size - -Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several -SRAM banks for power management, modem, security, etc. Further, use "syscon" -managing the common sram which can be shared by multiple modules. - -Example: - /*for Hi6220*/ - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.yaml new file mode 100644 index 000000000000000..f66d414a7a48071 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3620/hisilicon,hi6220-sramctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 SRAM controller + +maintainers: + - Wei Xu + +description: | + Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several + SRAM banks for power management, modem, security, etc. Further, use "syscon" + managing the common sram which can be shared by multiple modules. + +properties: + compatible: + items: + - const: hisilicon,hi6220-sramctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for Hi6220 */ + sram: sram@fff80000 { + compatible = "hisilicon,hi6220-sramctrl", "syscon"; + reg = <0xfff80000 0x12000>; + }; +... \ No newline at end of file From patchwork Sun Sep 27 06:21:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 313584 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2398046ilg; Sat, 26 Sep 2020 23:27:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz+jKJha46/Y8jan2OD7XOIHWEHDdc8o5lpK9I88KNSqGay9Z9QeBzVBVSKYNl5aGoAPFdF X-Received: by 2002:a17:906:f157:: with SMTP id gw23mr9995386ejb.325.1601188045898; Sat, 26 Sep 2020 23:27:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601188045; cv=none; d=google.com; s=arc-20160816; b=rggR/NQV1mlW7muyvVYy6OH+9VHWUmhdYBNeJJ29dkciqA/gdypOmqguA0UwgNvKB8 Gjfv8iqKZXMxfM+WWHMIFnMdVGWMKolVnwsnELyfsQhp9ASSoQT9C5BHxuH+2YmLrRig tt2R79yoeQBCOGvw588ZW/q2Egegl1OM0WTuDsjqTJclxxodT8XaTlHaX3mOnv4g+Irh 9KNhmUkuZRoofFnlyziXSgededzcMiZ9WntWgOR557piRRcJZg1D/e8XOjuT2YQ8/LOI c3DXzkh0UM+o5BSQcDr2F8B6jMdEWKHR+mRa5VectNsogxO/vkLWexmfdAU290/TKSUe tybg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=HhDm1C+P/A/61Idxz25k6PsG+rEBguRC/5tTAUSWLPw=; b=TP5z0zRijIV9brzHEhUeKaiYh3V/O0H2rzqpucz58CSSHwk1P8beZ6N3Irw6oCEmj/ 8IpC6HriTYCRNrDugUsMz4DlyD4XTNAf+SaHayzhShyNzSHrXncEHGyCz8WDCO/s3xjm PonybNiRA3h+ZI4a4nRbtMArvNtx68i5YpySOIaveRdQRlv9GiwwQPNFBwy2MscPfQvk qpf5oHNUeySwNwt1OKevoN82uQamwAXhBthGP3Oy/CX+cXgClSZ6iOWOqz1Ia2DbLUME AHe7NNpUIvy/ChJEpyeJcIOKc0/21cBBHEtOLTLM5a1++aWS+3VunwOATH1V2R79TOpv hr0w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r27si5180708edw.410.2020.09.26.23.27.25; Sat, 26 Sep 2020 23:27:25 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730458AbgI0G1Y (ORCPT + 6 others); Sun, 27 Sep 2020 02:27:24 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14238 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730417AbgI0G1F (ORCPT ); Sun, 27 Sep 2020 02:27:05 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C7D474B50986BD0C0B37; Sun, 27 Sep 2020 14:27:02 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sun, 27 Sep 2020 14:26:53 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v3 21/21] dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema Date: Sun, 27 Sep 2020 14:21:29 +0800 Message-ID: <20200927062129.4573-22-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200927062129.4573-1-thunder.leizhen@huawei.com> References: <20200927062129.4573-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------ .../arm/hisilicon/hisilicon-low-pin-count.yaml | 63 ++++++++++++++++++++++ 2 files changed, 63 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt deleted file mode 100644 index 10bd35f9207f2ee..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hip06 Low Pin Count device - Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which - provides I/O access to some legacy ISA devices. - Hip06 is based on arm64 architecture where there is no I/O space. So, the - I/O ports here are not CPU addresses, and there is no 'ranges' property in - LPC device node. - -Required properties: -- compatible: value should be as follows: - (a) "hisilicon,hip06-lpc" - (b) "hisilicon,hip07-lpc" -- #address-cells: must be 2 which stick to the ISA/EISA binding doc. -- #size-cells: must be 1 which stick to the ISA/EISA binding doc. -- reg: base memory range where the LPC register set is mapped. - -Note: - The node name before '@' must be "isa" to represent the binding stick to the - ISA/EISA binding specification. - -Example: - -isa@a01b0000 { - compatible = "hisilicon,hip06-lpc"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml new file mode 100644 index 000000000000000..a43f8b65547c10f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon-low-pin-count.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hip06 Low Pin Count device + +maintainers: + - Wei Xu + +description: | + Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which + provides I/O access to some legacy ISA devices. + Hip06 is based on arm64 architecture where there is no I/O space. So, the + I/O ports here are not CPU addresses, and there is no 'ranges' property in + LPC device node. + +properties: + $nodename: + pattern: '^isa@[0-9a-f]+$' + description: | + The node name before '@' must be "isa" to represent the binding stick + to the ISA/EISA binding specification. + + compatible: + oneOf: + - items: + - const: hisilicon,hip06-lpc + - items: + - const: hisilicon,hip07-lpc + + reg: + description: base memory range where the LPC register set is mapped. + maxItems: 1 + + '#address-cells': + description: must be 2 which stick to the ISA/EISA binding doc. + const: 2 + + '#size-cells': + description: must be 1 which stick to the ISA/EISA binding doc. + const: 1 + +required: + - compatible + - reg + +examples: + - | + isa@a01b0000 { + compatible = "hisilicon,hip06-lpc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xa01b0000 0x1000>; + + ipmi0: bt@e4 { + compatible = "ipmi-bt"; + device_type = "ipmi"; + reg = <0x01 0xe4 0x04>; + }; + }; +... \ No newline at end of file