From patchwork Wed Sep 23 22:09:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 313432 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp848551ilg; Wed, 23 Sep 2020 15:09:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx/CcGMY82uWGe0R8uefuRK5yos8t44OhAqs2eP3ylivMJN9khdV7Rurnyf3fbb6a3RSdyw X-Received: by 2002:aa7:d34b:: with SMTP id m11mr1565873edr.178.1600898994249; Wed, 23 Sep 2020 15:09:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600898994; cv=none; d=google.com; s=arc-20160816; b=MvIVwZrL0HCh7jn32ouV6pIQCEzFHgIHoKXWv0+E44VY6xmZBLryapXhsCWyILhYTK DbxVi/XkcBOuWPA1IhkTXdEEXT3YEL3p+cnwvU0/LCKvOS0b0JUJQ389Idz+88IXEBKM KIj/Lerx7VO5OlzaY83rVK9fQ2/lhI31J4PvZJbbPqmvF0Eye9vvo+neEjTpYVKDYhD4 Z5ErZ50m1WmI/1VeHi2vgFlSg0fbV3Fs/WuUcgf1CzDLkZHiEeNE7xyFJzYfuFfAmAPM 0hpZHnxBPwwXo7OJ0/MqKa+WMLDFMnteCgsjJBo1zPdoeI9h62S51VuRVwpaWeyS9s70 xAxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Jg0udFslsQmi5iIK71UKn6uMHLsLqUEcva0Jc1wUErQ=; b=F/o62qxJGpyPDjMnS5J5vd19jBFbb7JCwRQULXVEQAyVNeUHDpVbESF7BwDgzOmo86 SwdCEHXlZhU67jSYLeBTR52cBNkteAqautVdbI2kRQhh3cAI1Hmn4uIvADlYDneE027m O1hsaCRish/tig6lxSNQDqwiey4MNnjO7FjDTPt16RdQ/0XjDhCPbiGhXuhIrCEq/RlG d1A7WUMi6k7oA14hqxV5wzli96goYFACGqh1sKCMZZgXggnhz/tqaku1soAEzbFygBkI 39ELdzXZcXA9gJxGOTFrikDMIABw6co1osuvtAFJPgCLtX/FZLA+gy/6PlJXUt9cpPMg BwMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fOycuvNz; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q17si813634ejn.24.2020.09.23.15.09.54; Wed, 23 Sep 2020 15:09:54 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fOycuvNz; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726746AbgIWWJx (ORCPT + 6 others); Wed, 23 Sep 2020 18:09:53 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33402 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726199AbgIWWJx (ORCPT ); Wed, 23 Sep 2020 18:09:53 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08NM9n3n113986; Wed, 23 Sep 2020 17:09:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600898989; bh=Jg0udFslsQmi5iIK71UKn6uMHLsLqUEcva0Jc1wUErQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fOycuvNzQo2QOxMcK3SVMimYuP1ov2xqwm8sD2WYeZ4hpdx6gHZBNgK+1SqfU1E4R QvikWtJ8k8DMUkkBALz+i5SXwvucZNKCmaGnbLVWVWka/zVg0mDJkW3mmyidCX+CB3 dcDU6QhQPApJsU3nPV9bB5G5dYfJzJ8F90B3htiM= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08NM9ndF049612 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 23 Sep 2020 17:09:49 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 23 Sep 2020 17:09:49 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 23 Sep 2020 17:09:49 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08NM9mSq045198; Wed, 23 Sep 2020 17:09:48 -0500 From: Grygorii Strashko To: Tero Kristo , Rob Herring , Nishanth Menon CC: Peter Ujfalusi , Sekhar Nori , , , , Vignesh Raghavendra , Suman Anna , Kishon Vijay Abraham I , Grygorii Strashko Subject: [PATCH v4 1/4] arm64: dts: ti: k3-j7200: add DMA support Date: Thu, 24 Sep 2020 01:09:35 +0300 Message-ID: <20200923220938.30788-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200923220938.30788-1-grygorii.strashko@ti.com> References: <20200923220938.30788-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Peter Ujfalusi Add the ringacc and udmap nodes for Main and MCU NAVSS. Signed-off-by: Peter Ujfalusi Signed-off-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 36 +++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 44 +++++++++++++++++++ 2 files changed, 80 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 3df49577b06a..a44c3388c1a8 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -93,6 +93,42 @@ interrupt-names = "rx_011"; interrupts = ; }; + + main_ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x00 0x3c000000 0x00 0x400000>, + <0x00 0x38000000 0x00 0x400000>, + <0x00 0x31120000 0x00 0x100>, + <0x00 0x33000000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <1024>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <211>; + msi-parent = <&main_udmass_inta>; + }; + + main_udmap: dma-controller@31150000 { + compatible = "ti,j721e-navss-main-udmap"; + reg = <0x00 0x31150000 0x00 0x100>, + <0x00 0x34000000 0x00 0x100000>, + <0x00 0x35000000 0x00 0x100000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <212>; + ti,ringacc = <&main_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>, /* TX_HCHAN */ + <0x10>; /* TX_UHCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>, /* RX_HCHAN */ + <0x0c>; /* RX_UHCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; }; main_pmx0: pinctrl@11c000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index ec2745e0768e..334c2fb2c082 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -92,4 +92,48 @@ ti,sci-dev-id = <137>; ti,interrupt-ranges = <16 960 16>; }; + + mcu_navss: bus@28380000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; + dma-coherent; + dma-ranges; + ti,sci-dev-id = <232>; + + mcu_ringacc: ringacc@2b800000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x00 0x2b800000 0x00 0x400000>, + <0x00 0x2b000000 0x00 0x400000>, + <0x00 0x28590000 0x00 0x100>, + <0x00 0x2a500000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <286>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <235>; + msi-parent = <&main_udmass_inta>; + }; + + mcu_udmap: dma-controller@285c0000 { + compatible = "ti,j721e-navss-mcu-udmap"; + reg = <0x00 0x285c0000 0x00 0x100>, + <0x00 0x2a800000 0x00 0x40000>, + <0x00 0x2aa00000 0x00 0x40000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <236>; + ti,ringacc = <&mcu_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>; /* TX_HCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>; /* RX_HCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + }; }; From patchwork Wed Sep 23 22:09:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 313433 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp848612ilg; Wed, 23 Sep 2020 15:10:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJywpfUsc573J5ej2oG3UmXb1m9JBfS29h3s5zejlyRwPb4vRhQ6gOVFcHnQTT8Fipb9/Zb6 X-Received: by 2002:a50:d4d8:: with SMTP id e24mr1536144edj.1.1600899000230; Wed, 23 Sep 2020 15:10:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600899000; cv=none; d=google.com; s=arc-20160816; b=Hybnt0PC0PO8ar1SEtRwGmm49HD3m+6BoYZqcXem+efMl1M2WveRjOyFSJjv8cNnpv WqePOn9/Mu2tTSiPos1nvQzkalpWWMjpO/A7kejknq/Qxmx5L+EV25prIbkGOU5HPwOP HeNWlfk9IJ7Ntsx+pCbzT8OMR7pbT7R9LvLWV4eNd2RNmB9BnJO8u4NsY0ckNTb9X3w5 NruSYyxvxVwkyeRSs8k4Sk8H0F9UIoAByThUFOeZEKq4CAcJ1t03wny/QUTLbgi8UyNn +BsJLSakaVnlH/IPRDL9ytcu3e4+VdmGd6EcvPJFh5b9YnZyrpPQZxNsEpr5E9xOcZrb OoBw== ARC-Message-Signature: i=1; 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Signed-off-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index a44c3388c1a8..c2a986affb0e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -129,6 +129,18 @@ <0x0c>; /* RX_UHCHAN */ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; + + cpts@310d0000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x310d0000 0x00 0x400>; + reg-names = "cpts"; + clocks = <&k3_clks 201 1>; + clock-names = "cpts"; + interrupts-extended = <&main_navss_intr 391>; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; + }; }; main_pmx0: pinctrl@11c000 { From patchwork Wed Sep 23 22:09:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 313434 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp848687ilg; Wed, 23 Sep 2020 15:10:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxVk1hzSs5Ahh00dU46n8Wz2NtT75d9Sc2bKTlhxlEzCuxo2U5b9qnObYW5R+rnFsp5YUBv X-Received: by 2002:aa7:c154:: with SMTP id r20mr1467033edp.337.1600899008092; Wed, 23 Sep 2020 15:10:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600899008; cv=none; d=google.com; s=arc-20160816; b=hFhBL8sYMBndsjeCWgXLBstrdaIYkIQ6eTwhpqMHjL233D1p1e9dWSN/G4WY3Bvil5 196FwQWiI59bpZEdZNYyxT5xYaT7nluVko0NclbeOt7D739vY0xGyfyoTR3nhtfZnJB3 hzGvJ+0LKH2ogmBS5CEjbPnLdcUUcNxLm2nEIyHK+8hAUril9MdhvnIjzfM5wCKlkkn2 qAeghWvyiFfcSpT0+CIb1giK5hiYzmeHol3o4kLxnKHxJgPh7QjIW3A5LCmDp/lJA5OU +kP1/+75HOpZs06BgkIfFboiVHJ/Xjzsn0AX8BCs0dZvfB7DWFOzB1CohhHcY9ixeu/V jzyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=GD1fEmEazARBk317pqpPuhv10qzudlYM1CkQIflwrTc=; b=J9fHmf4lvBt10eLjQFFRvqgp6z5K3xZ6JZ+2yjtEgP8ihrQVhu8s7CTKDBWWUqcy6L 1bUZvrhHrDOpy6/KUtuj0xQRG1fhgA6ZrT2gmtYVotD3ceWJ8vWNFMKxfTk9x3uUzwLo ggOFbxHOEgDHEZm3DVw69F32Gp5fjHv22C7HrcB6nyDKgkn6MIM/Sh4pMNGbBmv06wt7 Bo2nQA7MzoevHwioYf10MRLqJppuXyYlacAb1pc95aNHuefvln3B0Q00FMyQFoafPd/D Nw9iWcNj5ILsbuhZYsnzgQEHneo0DeM0JeVhHXThxmmQcXcHicOhHEFZefHFspycAJhH Ss/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Uqnwngat; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Grygorii Strashko --- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 334c2fb2c082..c168171da429 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -34,6 +34,20 @@ }; }; + mcu_conf: syscon@40f00000 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x40f00000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x40f00000 0x20000>; + + phy_gmii_sel: phy@4040 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4040 0x4>; + #phy-cells = <1>; + }; + }; + chipid@43000014 { compatible = "ti,am654-chipid"; reg = <0x00 0x43000014 0x00 0x4>; @@ -136,4 +150,64 @@ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; }; + + mcu_cpsw: ethernet@46000000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0x46000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; + dma-coherent; + clocks = <&k3_clks 18 21>; + clock-names = "fck"; + power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&mcu_udmap 0xf000>, + <&mcu_udmap 0xf001>, + <&mcu_udmap 0xf002>, + <&mcu_udmap 0xf003>, + <&mcu_udmap 0xf004>, + <&mcu_udmap 0xf005>, + <&mcu_udmap 0xf006>, + <&mcu_udmap 0xf007>, + <&mcu_udmap 0x7000>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + ti,syscon-efuse = <&mcu_conf 0x200>; + phys = <&phy_gmii_sel 1>; + }; + }; + + davinci_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 18 21>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 18 2>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; }; From patchwork Wed Sep 23 22:09:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 313435 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp848768ilg; Wed, 23 Sep 2020 15:10:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwVZADuOemli1T6oz5Y94suDrT1Rs1F7wxW4ABSNv55aRXnWVO8qEGLUkR8xO2CuXNLu40f X-Received: by 2002:a50:9fa1:: with SMTP id c30mr1427622edf.207.1600899014699; Wed, 23 Sep 2020 15:10:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600899014; cv=none; d=google.com; s=arc-20160816; b=ZTfCw+4V/oy2Lx/g5R9mrq90IsKXPF6h0zQcKedL8IcZaioX2JEXrzSElKV+UnMaw8 CG+MXD0tV4SqmCevUKu4QgaRlLCm6LMXwaoLJWyLSUMWiCDuv++PHDJL5pN3QJckJ/Yj qe9pgw1r667K++pfl80+V+9/JiBRebkY/6zjNcUBldAxKh1kCQ6ms6y1uz8rXpE4s7N5 JbvCm4lE3Wu11fY8RhiWSzG7S5R3tpBjrpiU7iqwlF+8O9FuvFtRCT+MhvCHBN3mhtps Ht6wk/WTQwHPLfys5ts0AI7Mwq4JJiXDSlMo90exHdaUTXQErqK2FSfoVnp2TOokN9Uc 3gpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=zMPM4B2dMQw73A2K8MNlHJFwOwVnrAGVJ/8mNIZQ5dQ=; b=X2VxEiJMZOJ2odNSTmKXR8nFIRSNjjh0U1s4JHVMWJo6xGlsTkfYNoPtszDa81KkO7 vVSOfZS3OU26TtuCRRdWfy31DUT91NJiXHzsQTPsYFVU/eYqGRQb6vjjuD0Uuy3JEQUB KxCIzMkcY3aKJ2RdLRNx3qpeMzxiKO+GMoGsFcJjsjxI8SFUWYEY2f1aGleBxnt0ZSW2 Tht3CmYhziE9khY7dCxBHZVUqKKgtaruy+DU0ZvgsIc2zUpI4fWzAhGmnwlYTlyKChq7 G3ozIzaWmynFsGh7eeVEcr97rqyTnWJ/50ru9eZoRbhv6YAhEF4EWnCWmVwgkALC3CTF wW5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qrPefx9h; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id fx6si762921ejb.432.2020.09.23.15.10.14; Wed, 23 Sep 2020 15:10:14 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qrPefx9h; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726718AbgIWWKO (ORCPT + 6 others); Wed, 23 Sep 2020 18:10:14 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33894 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726199AbgIWWKN (ORCPT ); Wed, 23 Sep 2020 18:10:13 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08NMAAnR114434; Wed, 23 Sep 2020 17:10:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600899010; bh=zMPM4B2dMQw73A2K8MNlHJFwOwVnrAGVJ/8mNIZQ5dQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qrPefx9hoY1Wueb1a9YLMjHsx+/KXgbynwdd3KMUuRyunpa/D+GRN3mCdybWftH75 8QkWYBbFA3jDUSYMoDDi/XqlLgVVL5V12PPcIE8EKyj2ht++3Whw0cJk0Re829L4hS t/2mHt94Is3pbJ/dffR1qsjKP2ZnJ13ZqqD93a9M= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08NMAA9H081199 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 23 Sep 2020 17:10:10 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 23 Sep 2020 17:10:09 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 23 Sep 2020 17:10:09 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08NMA8VM046679; Wed, 23 Sep 2020 17:10:09 -0500 From: Grygorii Strashko To: Tero Kristo , Rob Herring , Nishanth Menon CC: Peter Ujfalusi , Sekhar Nori , , , , Vignesh Raghavendra , Suman Anna , Kishon Vijay Abraham I , Grygorii Strashko Subject: [PATCH v4 4/4] arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs Date: Thu, 24 Sep 2020 01:09:38 +0300 Message-ID: <20200923220938.30788-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200923220938.30788-1-grygorii.strashko@ti.com> References: <20200923220938.30788-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The TI j7200 EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI j7200 SoC MCU Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko --- .../dts/ti/k3-j7200-common-proc-board.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index d257d23e27f5..b8000dfb791c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include / { chosen { @@ -14,6 +15,32 @@ }; }; +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + >; + }; +}; + &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "disabled"; @@ -63,3 +90,21 @@ /* UART not brought out */ status = "disabled"; }; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +};