From patchwork Thu Dec 21 11:12:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 122540 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp737369qgn; Thu, 21 Dec 2017 03:13:53 -0800 (PST) X-Google-Smtp-Source: ACJfBosZlLhtNrdNLTNQEMzYw/xHpsghJq95n0ybVpnPQn9Y51ILJlBZNwcF4BpDwY/aJdVqGGat X-Received: by 10.84.248.132 with SMTP id q4mr10428515pll.121.1513854833181; Thu, 21 Dec 2017 03:13:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513854833; cv=none; d=google.com; s=arc-20160816; b=zyylTyk6uXtdCDoXwXlwe4NpxantCJxPYklQFOmRJrrF7XQ2CKAxUcJAFoJhEDeY9b ddJgknaX4XwgWgcam20FHvT0YVmzhIv/CBKWEhgrNWpKJ3zVB1r/IUJlhCmFBBH/iLy7 1+mt0a9OyyzW6o0TFr3M9wfa7mP6k3YVsZSZYocUrwBwC3orY9R+M3b/FOUCQ8xV+1jQ MmaoSEXkbHlRXJuvbgBgwGMeJa8UbaMNnGhRq3m2wpQ5oIBfT6GSAtQN1S3b9YTqPjdq FXnSbNrqnd8yN+d0ZoFOq4M0TrtsWkIfYzF/t5Me4iaqM/xidUnXU8lkE3SoMq9HRrMX KGGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=YO9ooKASunF06X+EcxvVyhrxWRPvU7Bs+VLjjMez1zw=; b=Mm+JcsgylJ1lWqNpCPzhMqewPl4p6EcTSD9y6rLJZEp84jcFtwXVusiOQWRyOYDM8w nX2TwGpjiZrcgPJLbGuHRePLPbTPFSVk59U1oPYLBNjCatDPbsyaiA/ugm4MgbXv8meK HQjUfYeXIqyUVR0CBGBmcvY15iIv/uxFBhaxSQM3cvPGajPJ+PnrqQMjId/LQXfANl71 zUbshs4u+1fz3NYRZft12PYF5LqUWbmeNNuV/E9PHxf7ZuVQL99qJyE2m46C0rPLw2rk zIN2eK4bX7YHFm2wQHj6ourMALNhcRFKw+D11YIy84srpnJF4q2dCL2bI87mdonb8Fqg cpYA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j5si14861776pfk.24.2017.12.21.03.13.52; Thu, 21 Dec 2017 03:13:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753191AbdLULNt (ORCPT + 28 others); Thu, 21 Dec 2017 06:13:49 -0500 Received: from mx.socionext.com ([202.248.49.38]:36276 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752556AbdLULNK (ORCPT ); Thu, 21 Dec 2017 06:13:10 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 21 Dec 2017 20:13:09 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 26EAC180B47; Thu, 21 Dec 2017 20:13:09 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 21 Dec 2017 20:13:09 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id B29B11A2540; Thu, 21 Dec 2017 20:13:08 +0900 (JST) From: Kunihiko Hayashi To: David Miller , netdev@vger.kernel.org Cc: Andrew Lunn , Florian Fainelli , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masahiro Yamada , Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH net-next v7 1/2] dt-bindings: net: add DT bindings for Socionext UniPhier AVE Date: Thu, 21 Dec 2017 20:12:55 +0900 Message-Id: <1513854776-4149-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513854776-4149-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1513854776-4149-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DT bindings for the AVE ethernet controller found on Socionext's UniPhier platforms. Signed-off-by: Kunihiko Hayashi Signed-off-by: Jassi Brar Acked-by: Rob Herring --- .../bindings/net/socionext,uniphier-ave4.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt new file mode 100644 index 0000000..c73a6f2 --- /dev/null +++ b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt @@ -0,0 +1,45 @@ +* Socionext AVE ethernet controller + +This describes the devicetree bindings for AVE ethernet controller +implemented on Socionext UniPhier SoCs. + +Required properties: + - compatible: Should be + - "socionext,uniphier-pro4-ave4" : for Pro4 SoC + - "socionext,uniphier-pxs2-ave4" : for PXs2 SoC + - "socionext,uniphier-ld11-ave4" : for LD11 SoC + - "socionext,uniphier-ld20-ave4" : for LD20 SoC + - reg: Address where registers are mapped and size of region. + - interrupts: Should contain the MAC interrupt. + - phy-mode: See ethernet.txt in the same directory. Allow to choose + "rgmii", "rmii", or "mii" according to the PHY. + - phy-handle: Should point to the external phy device. + See ethernet.txt file in the same directory. + - clocks: A phandle to the clock for the MAC. + +Optional properties: + - resets: A phandle to the reset control for the MAC + - local-mac-address: See ethernet.txt in the same directory. + +Required subnode: + - mdio: Device tree subnode with the following required properties: + +Example: + + ether: ethernet@65000000 { + compatible = "socionext,uniphier-ld20-ave4"; + reg = <0x65000000 0x8500>; + interrupts = <0 66 4>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + clocks = <&sys_clk 6>; + resets = <&sys_rst 6>; + local-mac-address = [00 00 00 00 00 00]; + mdio { + #address-cells = <1>; + #size-cells = <0>; + ethphy: ethphy@1 { + reg = <1>; + }; + }; + };