From patchwork Fri Sep 18 15:38:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 313207 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1492780ilg; Fri, 18 Sep 2020 09:46:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwO0AUvcBzS4KMx17/tZOho8yZJUkLfe0E3OoKyTETXSSahcJ6KbKTzuIikE/A72jdR9xiN X-Received: by 2002:a17:906:f92:: with SMTP id q18mr35643186ejj.237.1600447608440; Fri, 18 Sep 2020 09:46:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600447608; cv=none; d=google.com; s=arc-20160816; b=cQ7Q7PDNfc3f9rWKOGxGfRpgJSmy7PxMBQFN+FWA79ZzGaBxR5YIwuv8/LslTeKdCm 2QuX2HeQh+9Z3laIt3QpcODPqFFC/50gPwmAAVkvHKz44EcNWHlAdi5NXHojrQ8zmleZ E6XTsI1mwhc+6WGWcbaeh3eqfM+oxsFEuMtCJAla8BPVzV1YMajiKvYP8BhzkPEzoprT E/+cMvGe7RiXr2tZj38Gmdj3z2fGsaveKQ8BCFAR4LtTs2BoAkZc7/tRahut1KxPfIrN VQMg1s74MopSO/4st7g+S42pwAoLO+pRMVgqAbkAMwZkST/JfPR3/AHcHQXzWJ0Ka2Yy NRgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=WxwKsniN95GxFXt38joTOrhR5U6EWbgf2dDdlx0+WD8=; b=CHdXgkeHMkW4SvH2sInpoWdTggMVh9S0LkSutQdRLP/kPMX4G+jvhgxAj930IW0v+E GSumi9P3xqAMXeauSAPtK0WO4N7SYWRw0sZOQvVhoIgV3R2OHy28XDix4d6+Nlz6TYia dGRxkep5xH3sHxdou69fv3SnRxkUESeUPRVXRCTbPAof0sLziJXK2pjpFLT+5MOPzLdX 8njv4UGi6ouC+/wM8XK+3hVyg/USvzyn4AavismHH4tQ1vKBZmBHaNYeRYyEN9jiog3j je+PEE9rdY0g7vuw98f10JXyIO99mjI9/RTzTGgrYOYGWjvLNSqJax5PkS2vwLhg37yA AItg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jSOnU8gj; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id gw6si2710176ejb.240.2020.09.18.09.46.48; Fri, 18 Sep 2020 09:46:48 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jSOnU8gj; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726462AbgIRQqr (ORCPT + 6 others); Fri, 18 Sep 2020 12:46:47 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:57582 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726421AbgIRQqr (ORCPT ); Fri, 18 Sep 2020 12:46:47 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08IFck4t117018; Fri, 18 Sep 2020 10:38:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600443526; bh=WxwKsniN95GxFXt38joTOrhR5U6EWbgf2dDdlx0+WD8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jSOnU8gjoHFaBcJcKRMODaCtBZRN6silWN8qnzIWx8B3jAroQzSB8u1BlL1voLFzz NV45AmXv7xnbmN4LkBK1ZuIDB+pzRnMCAuSsZL1L39TUa1/Oj9RFWhMMYUGUJayrH+ PZMBtE3swDs5u7lC+XgkmBNcOccVN+wSqPF04/5U= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08IFckBk056323; Fri, 18 Sep 2020 10:38:46 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 18 Sep 2020 10:38:46 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 18 Sep 2020 10:38:45 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08IFciCk026243; Fri, 18 Sep 2020 10:38:45 -0500 From: Grygorii Strashko To: Tero Kristo , Rob Herring , Nishanth Menon CC: Peter Ujfalusi , Sekhar Nori , , , , Vignesh Raghavendra , Suman Anna , Kishon Vijay Abraham I , Grygorii Strashko Subject: [PATCH v3 1/4] arm64: dts: ti: k3-j7200: add DMA support Date: Fri, 18 Sep 2020 18:38:26 +0300 Message-ID: <20200918153829.14686-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200918153829.14686-1-grygorii.strashko@ti.com> References: <20200918153829.14686-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Peter Ujfalusi Add the intr, inta, ringacc and udmap nodes for main and mcu NAVSS. Signed-off-by: Peter Ujfalusi Signed-off-by: Grygorii Strashko Tested-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 36 +++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 44 +++++++++++++++++++ 2 files changed, 80 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 3df49577b06a..c5015df58cd4 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -93,6 +93,42 @@ interrupt-names = "rx_011"; interrupts = ; }; + + main_ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <1024>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <211>; + msi-parent = <&main_udmass_inta>; + }; + + main_udmap: dma-controller@31150000 { + compatible = "ti,j721e-navss-main-udmap"; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x100000>, + <0x0 0x35000000 0x0 0x100000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <212>; + ti,ringacc = <&main_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>, /* TX_HCHAN */ + <0x10>; /* TX_UHCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>, /* RX_HCHAN */ + <0x0c>; /* RX_UHCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; }; main_pmx0: pinctrl@11c000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index ec2745e0768e..7ecdfdb46436 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -92,4 +92,48 @@ ti,sci-dev-id = <137>; ti,interrupt-ranges = <16 960 16>; }; + + cbass_mcu_navss: navss@28380000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-coherent; + dma-ranges; + ti,sci-dev-id = <232>; + + mcu_ringacc: ringacc@2b800000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <286>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <235>; + msi-parent = <&main_udmass_inta>; + }; + + mcu_udmap: dma-controller@285c0000 { + compatible = "ti,j721e-navss-mcu-udmap"; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + msi-parent = <&main_udmass_inta>; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <236>; + ti,ringacc = <&mcu_ringacc>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>; /* TX_HCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>; /* RX_HCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + }; + }; }; From patchwork Fri Sep 18 15:38:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 313205 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1454299ilg; Fri, 18 Sep 2020 08:58:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzWt+/aNMfWm2xqA1iHPZUE3+SqBMezG2Chy1E9DX5cfoN5tWtqe2bOMKwxBV7g2/IICGu6 X-Received: by 2002:a50:fc83:: with SMTP id f3mr40490220edq.102.1600444717700; Fri, 18 Sep 2020 08:58:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600444717; cv=none; d=google.com; s=arc-20160816; b=Al+1vJQMpi7lwX3HHUkJbF8ckcR0a9tzgBzVZqYlc9w/lf7Dh7L7OvGMHYVZaV1jTW WwmzFrPhc+3jPpHXE8g3GCtqXfCyx0cMqNKiVWwlXtjAFuS/KW7PIWXsSpXugXCimbvR BNFvPrZxJztfSTOegpaXDy6YjQuNzAez6gFxVERxTynuTKOguYhrTKESz4kBEgkX/Olu hmHmJLKccdevW8aeLBemL21/v97syQzJWYm7FwwVTSii0RrgMj07XEiyM+Z10KoqIpv3 pCG97TMlTGhuyLQiUMYT0i83fAx1zU4d5NxpEQOInTUxdHti/RUO/WZWagODLey9xi9v QYJw== ARC-Message-Signature: i=1; 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Signed-off-by: Grygorii Strashko Tested-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index c5015df58cd4..31bd0c5ffb8b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -129,6 +129,18 @@ <0x0c>; /* RX_UHCHAN */ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; + + cpts@310d0000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x310d0000 0x0 0x400>; + reg-names = "cpts"; + clocks = <&k3_clks 201 1>; + clock-names = "cpts"; + interrupts-extended = <&main_navss_intr 391>; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; + }; }; main_pmx0: pinctrl@11c000 { From patchwork Fri Sep 18 15:38:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 313203 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1440993ilg; Fri, 18 Sep 2020 08:39:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzXqx/WyS+C8dgmEfSC+jNIy4gmMCwDa4ROZqZD0mPNZDys3vjSm54A9KdCouwLVuV9kcqD X-Received: by 2002:aa7:c38a:: with SMTP id k10mr40233554edq.325.1600443544616; Fri, 18 Sep 2020 08:39:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600443544; cv=none; d=google.com; s=arc-20160816; b=FwBRBXTcUupxv7BwNzv7emKww1tdWvulEq1cSJ8dX5Dp7CW8kumjACtjhgLs8LE6ju lu0nPv9JhPDq3DP6bMamX8BUSYAw4ZwSYiR7NNQ22nD58i7yjjahf8gXbSleSlsycXFB i0twQSt7oyWc8EbCiNDPc6FqvwVWXyavYBn6ME6gLIaRNWm583HPfKOzCfc1A24wJj9T h0+7yY01SdTMcdcSPG1I0bOqHt1y+fw35P4+F+qatlhUg7IYiv/40u69nHA8A977H7kK 1pT8zShfVC3/eay4PUEhBNM7ZQ8iz79iHB0C6F4/bG3TdJbfOjXWtxoaBAVRB6wS/h2z 9yhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Xpkc999VL1q+aCe7qStcFHCXh85l2a98/PejKs0Xb38=; b=aToUVwoUfeqmLQdRETDW56Dm5XUrz3iGaPr9IjIX0U1QpNf1wBjDNHgsZ5K4ZqtmeX glxmfy76KxI0XhJXuqUwb0IAsyCOdJeo/GkmLF6wlizfkjmnIpckOTOFNLmYTaNuQttg WesJZoXHlTcg8lRYFZCzcsZpGTgIH9DDKKulllLab8oETAmlf9K/BJe2ziPy17DIDKwU BBVY/G9/eQkp+6ce6+fICyK7kwLd0rMg7dppdLTXpUVSOvPt7zvElBzgr4dn8IUEVoXK 8uNZ7MNCoEFosLcCqep+IWShgU7/GFBReV3TXy0lOWMnujjs+zxwUyG4mEbETzxc33B6 D/9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=yDzcKFut; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x1si2408616ejw.494.2020.09.18.08.39.04; Fri, 18 Sep 2020 08:39:04 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=yDzcKFut; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726115AbgIRPjD (ORCPT + 6 others); Fri, 18 Sep 2020 11:39:03 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:42340 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725955AbgIRPjD (ORCPT ); Fri, 18 Sep 2020 11:39:03 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08IFctWP029256; Fri, 18 Sep 2020 10:38:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600443535; bh=Xpkc999VL1q+aCe7qStcFHCXh85l2a98/PejKs0Xb38=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yDzcKFutiljP+DfjEsTSjSFbjndM3NaoNwbyLHFNSgqTB6gG1wdVqr13Wri/9xuJy IBhX340YfNGTfbEucKn3Rs0pwze5oSSzZbK340YCziNOYYx0Lc5gpBAUs0xV8AAWxf ZZWekjcLeQpSs6VbbQqWc77ZTnM6NIHla2mJ6b/I= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08IFct2h024588 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Sep 2020 10:38:55 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 18 Sep 2020 10:38:55 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 18 Sep 2020 10:38:55 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08IFcsxD014767; Fri, 18 Sep 2020 10:38:54 -0500 From: Grygorii Strashko To: Tero Kristo , Rob Herring , Nishanth Menon CC: Peter Ujfalusi , Sekhar Nori , , , , Vignesh Raghavendra , Suman Anna , Kishon Vijay Abraham I , Grygorii Strashko Subject: [PATCH v3 3/4] arm64: dts: ti: k3-j7200-mcu: add mcu cpsw nuss node Date: Fri, 18 Sep 2020 18:38:28 +0300 Message-ID: <20200918153829.14686-4-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200918153829.14686-1-grygorii.strashko@ti.com> References: <20200918153829.14686-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT node for The TI j7200 MCU SoC Gigabit Ethernet two ports Switch subsystem (MCU CPSW NUSS). Signed-off-by: Grygorii Strashko Tested-by: Kishon Vijay Abraham I --- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 7ecdfdb46436..a994276a8b3d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -34,6 +34,20 @@ }; }; + mcu_conf: syscon@40f00000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x40f00000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40f00000 0x20000>; + + phy_gmii_sel: phy@4040 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4040 0x4>; + #phy-cells = <1>; + }; + }; + chipid@43000014 { compatible = "ti,am654-chipid"; reg = <0x00 0x43000014 0x00 0x4>; @@ -136,4 +150,64 @@ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; }; + + mcu_cpsw: ethernet@46000000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x46000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; + dma-coherent; + clocks = <&k3_clks 18 21>; + clock-names = "fck"; + power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&mcu_udmap 0xf000>, + <&mcu_udmap 0xf001>, + <&mcu_udmap 0xf002>, + <&mcu_udmap 0xf003>, + <&mcu_udmap 0xf004>, + <&mcu_udmap 0xf005>, + <&mcu_udmap 0xf006>, + <&mcu_udmap 0xf007>, + <&mcu_udmap 0x7000>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + ti,syscon-efuse = <&mcu_conf 0x200>; + phys = <&phy_gmii_sel 1>; + }; + }; + + davinci_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 18 21>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 18 2>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; }; From patchwork Fri Sep 18 15:38:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 313204 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1441069ilg; Fri, 18 Sep 2020 08:39:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxhrfXD7Uf7NUXEGkd+faiAyKOf8BnlxxI/DoWIk2Ntqb8hnhGtZhQWiL7sAIg1fOFk35ng X-Received: by 2002:a17:906:770c:: with SMTP id q12mr35700110ejm.518.1600443550499; Fri, 18 Sep 2020 08:39:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600443550; cv=none; d=google.com; s=arc-20160816; b=IC9IPKOX6s5lnSSQFooQiRfq8QJ5bNrpurVEiFCk9Xa2PfOrOVatF1M5UObno9NR9c x83bGgsc/1d5xcZebqDSNd+Y4pkB3GZ0Zs5vSHViImACpR5XgHJwVpsoIp03FjOo0Dph Eifl61A4Mu6td7eGYIxAHDB/FjxBk5Z3RCag3WlMIVWniQOZhDO1ZCfsO9KpiWusTb84 M0Fvp9nDzHhFzkptuZVLMIXuelimzVOBJ+hNprW5MEx9eIdiLeA7uD2xh3oAj3Or2LE0 6nlqc1kkeIv0/q4iasEKdabhgdMWx3N5y/qyCSTkIRiP9ZrtC0DMmyHF1+RWzUDcFN54 JfWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=7XDPRqUzl+JVINgiR0D8+gFPVzJBv1P361gPvzhvl6M=; b=zuCAiOnUajDXqzCw7krIWyjkB7b8tS8DPAcPvhcvtCUCboou1mUcyb5IJluYf7hkYy g+bhVvuIXAnZTWgUjQN8MYgRU3/Sg62f9PSyiTczobhBzCku2V+Cu4Hj3CnMHrUISeZi F1UxOZFlca12SyAXcXOhlGYeUB+PdTQzuFuel14ClFryHkCvXSuy4UrtnssSD8/3TZgb qomJOhQaP+7EkcbgxscCB/VToouXvljdsTdMZs5vWtoKvuOGYo6ce25wKYzVexvqankJ RY7Zk4QQwSVYvYmbNx0yzxs580R/BSMnlKpAtRo75mB6lPtZDsgf1H8RECstwDHlSNHG MqvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qO5WKj8V; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r23si2422692ejs.259.2020.09.18.08.39.10; Fri, 18 Sep 2020 08:39:10 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qO5WKj8V; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725955AbgIRPjF (ORCPT + 6 others); Fri, 18 Sep 2020 11:39:05 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:40494 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726044AbgIRPjD (ORCPT ); Fri, 18 Sep 2020 11:39:03 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08IFcvHv011325; Fri, 18 Sep 2020 10:38:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600443537; bh=7XDPRqUzl+JVINgiR0D8+gFPVzJBv1P361gPvzhvl6M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qO5WKj8VqbZ/lc9rJ4Jw7lvR4j11mJyVoxtk8AVuZiSk9TUk7szfS1KASOtSVrvPz iYLbzyxcV0FrOwRomAwh8U/XJ9kmRxnz935hi+G6VCBG91xi4chbz8lyNhPCjkQAjo HX282NG5ttuq5L37cAzrzqQegdI7ZFVujaEhpu/o= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08IFcvoQ122262 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Sep 2020 10:38:57 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 18 Sep 2020 10:38:57 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 18 Sep 2020 10:38:57 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08IFcuB3094740; Fri, 18 Sep 2020 10:38:56 -0500 From: Grygorii Strashko To: Tero Kristo , Rob Herring , Nishanth Menon CC: Peter Ujfalusi , Sekhar Nori , , , , Vignesh Raghavendra , Suman Anna , Kishon Vijay Abraham I , Grygorii Strashko Subject: [PATCH v3 4/4] arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs Date: Fri, 18 Sep 2020 18:38:29 +0300 Message-ID: <20200918153829.14686-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200918153829.14686-1-grygorii.strashko@ti.com> References: <20200918153829.14686-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The TI j7200 EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI j7200 SoC MCU Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko Tested-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j7200-common-proc-board.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index e27069317c4e..f7e6b9b5ef5f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "k3-j7200-som-p0.dtsi" +#include / { chosen { @@ -14,6 +15,32 @@ }; }; +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + >; + }; +}; + &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "disabled"; @@ -62,3 +89,21 @@ /* UART not brought out */ status = "disabled"; }; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +};