From patchwork Fri Sep 18 13:22:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313189 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333254ilg; Fri, 18 Sep 2020 06:23:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzc0ux6IrjzKG2XW3QPLTDn3GjCxaXnaxkqWjWcLj3OYNfloGg1XT3OC4FIEWvbTjoOIK06 X-Received: by 2002:a05:6402:17fc:: with SMTP id t28mr38561054edy.244.1600435395170; Fri, 18 Sep 2020 06:23:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435395; cv=none; d=google.com; s=arc-20160816; b=uwUbi3jZq55uqls39ECDTXtdtL00VXuPmcBPezmDjhRQYt1f/Lo5fhQZbLzowWmzBc S7uwuacR8ZZLRbf1YNiLBwbeINz2vJhhEsi+7FpaDO+EjHxLy1qqsxCJ/fXNxzmbVcHU qyNc/T6iMggal+igrgF+7wG2lRTbbKaI+hl/dm5tp82uF16YOxGl87zmBgXIu89Pmitd iAPTT1S66qbS7V+j582KK0Fa5YVdUdD6XF0Wd15KbXxQvM83OyDTb0P+wDXQ5H0KGbTL an0JVBN/dRGei220Xa0SCo/58rlq9M5AoQD7b+fb1aQFZuA2EP01ldPIktBIrvHU8tH3 0flw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Wm2ja0ywcREULPypt/DxvBVz7jxDFM+ZjJ9C1LJ9Paw=; b=fINU68yMKvEeZBq4Btr7xEMGyxYSoPI1O2lOJ8Uxa3psrgCQJMJIkMdH33CCnxaMMX 0F86gDy7FMb1UC9ZL10j38EoKxQEE6Y9tYFo0XMXgoV9AHK6z0lXWZUXDA2Tnae57vBi Js49Y9Zn6rNwohhVxIBG6zAI6zcNsArQdMM1I033rQy1jL/X9FUGK7/VuN+aN+NFnDu/ I0z7PGUdeskn8/cmgCki6i0VelTpMPwyNnnUxTfCrZhB+AhKnszZ8lt9RiGq8YF+8SEa sGnDRGvnkJ2Mt1p/3LXM4YbmMeCOEY2t/JmislBSKYg9Y06bNYAGvZFwPjwwgE1+09tV WapA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x18si2160452ejn.61.2020.09.18.06.23.15; Fri, 18 Sep 2020 06:23:15 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726683AbgIRNXM (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:12 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:13306 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726121AbgIRNXL (ORCPT ); Fri, 18 Sep 2020 09:23:11 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 7661B4A67D1F7224016B; Fri, 18 Sep 2020 21:23:08 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:22:58 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 1/9] clocksource: sp804: cleanup clk_get_sys() Date: Fri, 18 Sep 2020 21:22:29 +0800 Message-ID: <20200918132237.3552-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kefeng Wang Move the clk_get_sys() part into sp804_get_clock_rate(), cleanup the same code. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp804.c | 30 ++++++++++-------------------- 1 file changed, 10 insertions(+), 20 deletions(-) -- 1.8.3 diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index 5cd0abf9b3965fe..bec2d372e0df018 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -22,11 +22,18 @@ #include "timer-sp.h" -static long __init sp804_get_clock_rate(struct clk *clk) +static long __init sp804_get_clock_rate(struct clk *clk, const char *name) { long rate; int err; + if (!clk) + clk = clk_get_sys("sp804", name); + if (IS_ERR(clk)) { + pr_err("sp804: %s clock not found: %ld\n", name, PTR_ERR(clk)); + return PTR_ERR(clk); + } + err = clk_prepare(clk); if (err) { pr_err("sp804: clock failed to prepare: %d\n", err); @@ -72,16 +79,7 @@ int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, { long rate; - if (!clk) { - clk = clk_get_sys("sp804", name); - if (IS_ERR(clk)) { - pr_err("sp804: clock not found: %d\n", - (int)PTR_ERR(clk)); - return PTR_ERR(clk); - } - } - - rate = sp804_get_clock_rate(clk); + rate = sp804_get_clock_rate(clk, name); if (rate < 0) return -EINVAL; @@ -173,15 +171,7 @@ int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct struct clock_event_device *evt = &sp804_clockevent; long rate; - if (!clk) - clk = clk_get_sys("sp804", name); - if (IS_ERR(clk)) { - pr_err("sp804: %s clock not found: %d\n", name, - (int)PTR_ERR(clk)); - return PTR_ERR(clk); - } - - rate = sp804_get_clock_rate(clk); + rate = sp804_get_clock_rate(clk, name); if (rate < 0) return -EINVAL; From patchwork Fri Sep 18 13:22:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313198 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333894ilg; Fri, 18 Sep 2020 06:23:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxmZr0EKAOD2gXhZVTHzJCr5R+XhSGq5jhHYCDT6mo0lgSDHi5EgNgvNOdZT8QOj+bB9Vbt X-Received: by 2002:a17:906:9389:: with SMTP id l9mr36796287ejx.537.1600435435088; Fri, 18 Sep 2020 06:23:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435435; cv=none; d=google.com; s=arc-20160816; b=ZjEnctx0y52u530pETM10XFDdaoPWibKlcZBsmG5ABUOHsVX/W5p1r/iQyCFcqXDQM DFx3qolJwjcWSRmGLaHlVsmXdMgPV20nionQbhneM6z+Y1OSPLMKDMFONLM0fLyDkz6P I5oI9CEJFqAH8Hues2ZuN7t2KXglUZ7y/WGWg1zAtGwGgevi1HrchDk8OBTMvWnFU72U j0Zz35Hu0rpRIfHzyW1e+cAlP8pPuUVeIegsyoDz6YI0DpGOzLnXfubRI2PFgH4h9ptb 4Vpozej2aNAjuT6aAl+1eRFgDK/ONrBEruDXexLr/ZK+GcwVQkSiO+4MC2c5BepzrC/s xcZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=E3IqX37sMCbqf8PcQVppmAfIeIjmK+IXBpADaUCEHbY=; b=maB7T+CLl4yu9kMH0+8XlJmUchpvsstHIljvk/JksaVEnp3m7/2C97uXCvseTd27pm vpW1PnuG5onIyocMQBXznMXavJqsu5H3FaX2nUTqVWh7wijJO6S9siyRhTL4lxprGio/ dTji2oTgUsIa3W67NOUrDqWtELlP23e1SYG5Pcs+TfK1JS2RVFjj5Ha+9/IaRz/cmlvR 22vwrHiOrUGvkOAkB4Ray0lKUjYIMVlEAFNFuRtbCMLFrX9bhPAK9lmvW5v6fhvp0m1X NqKfdU0+uF4k9z4cOk12UAkxmFDeuvH7zBTLB6HDGmY1eyGYCDV8pXN6pCLqgzxXeRLl XCog== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bh20si2139620ejb.294.2020.09.18.06.23.54; Fri, 18 Sep 2020 06:23:55 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726768AbgIRNXq (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:46 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:13307 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726192AbgIRNXM (ORCPT ); Fri, 18 Sep 2020 09:23:12 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 803D653A966E1384A3D6; Fri, 18 Sep 2020 21:23:08 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:22:59 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 2/9] clocksource: sp804: remove unused sp804_timer_disable() and timer-sp804.h Date: Fri, 18 Sep 2020 21:22:30 +0800 Message-ID: <20200918132237.3552-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since commit 7484c727b636 ("ARM: realview: delete the RealView board files") and commit 16956fed35fe ("ARM: versatile: switch to DT only booting and remove legacy code"), there's no one to use the functions defined or declared in include/clocksource/timer-sp804.h. Delete it. Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp804.c | 7 ------- include/clocksource/timer-sp804.h | 29 ----------------------------- 2 files changed, 36 deletions(-) delete mode 100644 include/clocksource/timer-sp804.h -- 1.8.3 diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index bec2d372e0df018..97b41a493253e0a 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -18,8 +18,6 @@ #include #include -#include - #include "timer-sp.h" static long __init sp804_get_clock_rate(struct clk *clk, const char *name) @@ -67,11 +65,6 @@ static u64 notrace sp804_read(void) return ~readl_relaxed(sched_clock_base + TIMER_VALUE); } -void __init sp804_timer_disable(void __iomem *base) -{ - writel(0, base + TIMER_CTRL); -} - int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, const char *name, struct clk *clk, diff --git a/include/clocksource/timer-sp804.h b/include/clocksource/timer-sp804.h deleted file mode 100644 index a5b41f31a1c256a..000000000000000 --- a/include/clocksource/timer-sp804.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __CLKSOURCE_TIMER_SP804_H -#define __CLKSOURCE_TIMER_SP804_H - -struct clk; - -int __sp804_clocksource_and_sched_clock_init(void __iomem *, - const char *, struct clk *, int); -int __sp804_clockevents_init(void __iomem *, unsigned int, - struct clk *, const char *); -void sp804_timer_disable(void __iomem *); - -static inline void sp804_clocksource_init(void __iomem *base, const char *name) -{ - __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0); -} - -static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base, - const char *name) -{ - __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1); -} - -static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name) -{ - __sp804_clockevents_init(base, irq, NULL, name); - -} -#endif From patchwork Fri Sep 18 13:22:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313194 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333563ilg; Fri, 18 Sep 2020 06:23:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy3OoQePx3NNamQWSmgxfka1a1l6KzZd2kqlNj9UYlEG82II4vIqcpFCgOxMBBYVcPuyyrp X-Received: by 2002:a17:906:3791:: with SMTP id n17mr35291976ejc.216.1600435416218; Fri, 18 Sep 2020 06:23:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435416; cv=none; d=google.com; s=arc-20160816; b=uUDxuRfvlu8wfBKJJveufhK2JasPXlz3iBHc9riWSaQlqT/L2jHmrammbgn5FH78uC chbclfUlwbgSUjdbjklZyLMX9h3N/itEa1FJRCk8pidQgiM63v0k+RW4HanLpITbH8RA TUdbdt680fwEG/8eAt8NVE0KUZKfbS5Ul2C3Hnfsyn1QYyqVWcC2ki28di9nDnZdAjAK hKNCvndbJyCmKdW/8gNZY7MffUF9gU6S3La4kDk+XAVVkZHbNAk9+H7sZj83bmL13gsf OX2Y1J8PD2Uc7DLMAg0G/OGwY0Oc1BdJIWq8UCcc3rAAJuj17i/m6NKpSxRpgcHPRspD dhSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=kQQ8K7DklrtrO+8OXb+dPTsxAw+9SEa3x4EuCPQnC5I=; b=pqBZ8jvCkkmuB4why0Y5ljlK61wnx1Si63VuudwWUXauXgAhED7tS16oW8xTzumNcl cPL4+62FHtAoIFoNnbVb58858TuiNyTLMfNJux7OMZE1Al13bI1aScbo3hsMKNyA2lZC 3m8CUyhVGB8/5hCzw54ggcRfPI5IbZs4fB7IduIogncg8+AX8G1y3Ir5nWp/mcMw/ra8 YMsPWaq0ZCkQObA7VUj4ojTDWws8jF7SWIxKDP8IyuWrIy19mzK/Bce9kc3CG6Gz2kGh CiVw2T+xOlYbHX7brR3z7bpbcnIjoylo2+XLZH2QWFA3Nklw6MQpadwC6VdSeYcezIPo NEtA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z1si2094545edx.584.2020.09.18.06.23.36; Fri, 18 Sep 2020 06:23:36 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726843AbgIRNXf (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:35 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:13310 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726767AbgIRNXO (ORCPT ); Fri, 18 Sep 2020 09:23:14 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 94EF0F938245AE61D408; Fri, 18 Sep 2020 21:23:08 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:00 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 3/9] clocksource: sp804: delete the leading "__" of some functions Date: Fri, 18 Sep 2020 21:22:31 +0800 Message-ID: <20200918132237.3552-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Delete the leading "__" of __sp804_clocksource_and_sched_clock_init() and __sp804_clockevents_init(), make it looks a little more comfortable. Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp804.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) -- 1.8.3 diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index 97b41a493253e0a..097f5a83163c6e1 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -65,10 +65,10 @@ static u64 notrace sp804_read(void) return ~readl_relaxed(sched_clock_base + TIMER_VALUE); } -int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, - const char *name, - struct clk *clk, - int use_sched_clock) +int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, + const char *name, + struct clk *clk, + int use_sched_clock) { long rate; @@ -159,7 +159,8 @@ static int sp804_set_next_event(unsigned long next, .rating = 300, }; -int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) +int __init sp804_clockevents_init(void __iomem *base, unsigned int irq, + struct clk *clk, const char *name) { struct clock_event_device *evt = &sp804_clockevent; long rate; @@ -228,21 +229,22 @@ static int __init sp804_of_init(struct device_node *np) of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); if (irq_num == 2) { - ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); + ret = sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); if (ret) goto err; - ret = __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1); + ret = sp804_clocksource_and_sched_clock_init(base, + name, clk1, 1); if (ret) goto err; } else { - ret = __sp804_clockevents_init(base, irq, clk1 , name); + ret = sp804_clockevents_init(base, irq, clk1, name); if (ret) goto err; - ret =__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, - name, clk2, 1); + ret = sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, + name, clk2, 1); if (ret) goto err; } @@ -282,7 +284,8 @@ static int __init integrator_cp_of_init(struct device_node *np) goto err; if (!init_count) { - ret = __sp804_clocksource_and_sched_clock_init(base, name, clk, 0); + ret = sp804_clocksource_and_sched_clock_init(base, + name, clk, 0); if (ret) goto err; } else { @@ -290,7 +293,7 @@ static int __init integrator_cp_of_init(struct device_node *np) if (irq <= 0) goto err; - ret = __sp804_clockevents_init(base, irq, clk, name); + ret = sp804_clockevents_init(base, irq, clk, name); if (ret) goto err; } From patchwork Fri Sep 18 13:22:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313191 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333437ilg; Fri, 18 Sep 2020 06:23:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzPMi+egRSJO8ikInZ3FXjJdsEaKdbaI/poITc13pz06Q/7OTSm5d9I02vVk1vdFTJ+Uzcb X-Received: by 2002:a17:906:4c58:: with SMTP id d24mr37430749ejw.108.1600435406948; Fri, 18 Sep 2020 06:23:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435406; cv=none; d=google.com; s=arc-20160816; b=Oerxc5QB6M0g1f1F9HzNt4pzO8qzf1IkaWG9QiZglw5vQ8dkZx2M2lWtMrUsjrTDj/ /uvXObed2DZl1+mE+XmXHSB0UHPNICaDdoKHee2uMUHZmiNVFNHq73OQzwgbo6IgswuF 7NYssKed7aHb3Gp57QewPMe7QbU8yUB0WvViArVdfWKbu4fPT6BH+FMGkA+NPToWzOOA udLcfnLOspUbXjHGfmIz4wghdELB7zQ5vhzDQfwse5x3HW2UPD1Nsi8J4Q/x9ZlK+2rW KzaiECMiH7uScl7s4OyCgrtgQW8TyPvG9/CITHcYOkWq28NPs5946Fcah7xSP7SLRTKe yqiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=S0eLwKyVCSo+aLflQiwWV0eJO7FpFWPlnvWmy3olT8A=; b=c9TIZ8rjomWG5VlCkGeeD5T/rAuFctQyJIfRRIAlAJ8zkM8ZlrrJInzV6aYeS8+3zi f8ZiArD4CfdIs7R8Qy/GUYMB42ztK4RFRqDrYHSxxIq4L4s22DDMd2I/lTWCh6b2gH8Y CKkrts7oOAudkl43SClW0irGnyAzrI9fs3ia5YbqISBt8iZVlsZ37Lh77/BKdhhcmuNv 8Wq+0tk1Y4Sh83AfUcyQ1BrC3UMOovb4i17YUs6ejXBuSN1sRCyGUrLNvKDhN83ibBuP FpbLrVaC0b66iO2DSocvUphdS8BNXMP+2DvFx8tpGEtLApvPWY1UMmfRGag9w3tg/IKb 3q6Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dr21si2259981ejc.186.2020.09.18.06.23.26; Fri, 18 Sep 2020 06:23:26 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726825AbgIRNXZ (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:25 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:13305 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726126AbgIRNXR (ORCPT ); Fri, 18 Sep 2020 09:23:17 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 7B91DB9DB31F4614ACC2; Fri, 18 Sep 2020 21:23:08 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:00 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 4/9] clocksource: sp804: remove a mismatched comment Date: Fri, 18 Sep 2020 21:22:32 +0800 Message-ID: <20200918132237.3552-5-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org writel(0, base + TIMER_CTRL); ... ... writel(xxx | TIMER_CTRL_PERIODIC, base + TIMER_CTRL); The timer is just temporarily disabled, and it will be set to periodic mode later. The description of the field TimerMode of the register TimerXControl as shown below: 0 = Timer module is in free-running mode (default) 1 = Timer module is in periodic mode. Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp804.c | 1 - 1 file changed, 1 deletion(-) -- 1.8.3 diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index 097f5a83163c6e1..a443f392a8e7d63 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -76,7 +76,6 @@ int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, if (rate < 0) return -EINVAL; - /* setup timer 0 as free-running clocksource */ writel(0, base + TIMER_CTRL); writel(0xffffffff, base + TIMER_LOAD); writel(0xffffffff, base + TIMER_VALUE); From patchwork Fri Sep 18 13:22:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313196 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333751ilg; Fri, 18 Sep 2020 06:23:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyiN3TivbsGCFsZb0LKIFRddY3e75X9+v9DDAwRezutRStnlrtK1XITr1AXHI0jFvifr2Ab X-Received: by 2002:a17:906:1e51:: with SMTP id i17mr37295643ejj.103.1600435426925; Fri, 18 Sep 2020 06:23:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435426; cv=none; d=google.com; s=arc-20160816; b=vQMXIrRrQK4QMwnItxXb6ofV6b3XAZUon8eHEBK2x+JeaoMPwN6/n4nLdrCo+sVXCF +krcr6uuRvsASAbUw5pE34XwLW0Hwb8k71sDr/Hz9OAURLjPwLslWwFsN/nYoDmdyEBI Td+wfk4pIUr/H/DZLh3IMqsSCxhQBj4HN4CFoKvR9Stvo2Ip13lpmhLBqu4gXs4DKIBb /iFznBO5HgVbpjbBJiR8+XrTgeYihAPR9sxPoPIIjBuYeelvOSzoQaAOTTs0QIEJTx3F OjXxoIgZZEv73tKIzkxbxyyWVsnDdkZb/p/vPvDg4e53FcBaEt6HRJYFTDA3BwRmpCZ4 Z7sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=hMZZAXeX7ChwqJ4QB1x1fLjSU0j10qLtJPtwbE00CZ0=; b=RSrlSYi3fR4hXi505RpTdUjyz4Fr7aR5RSNY7KpJ0+BslEHymO9QAMMGtsXriJfBzV 9pfHVGEJpiERmMLBteqcPnYUVLcHMipqQNrRLRNdrfv3jDH0EpPbOJVyaHdoBg6SgICM o2p0lJJb7+96WH1KhEeklU/EAzpb+uIWjRFo3dXVUFmYQZZ3VCuLMJPOPf5EXacrqohG k9ZE8XTUR8rTTgfJlqgh5m5YJ5A+9nvcVXQzjJSoKZvXdSrqbE6WRaEIZyyoVZ/Si3Z3 VOekZPYIgjsDDD8KbVADloe2JorFc1Xob8/MK7n7AHVKY+1II/SDY70aA2o6oa524Q7l vXoQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v5si2186445edr.49.2020.09.18.06.23.46; Fri, 18 Sep 2020 06:23:46 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726126AbgIRNXp (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:45 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:13304 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726239AbgIRNXM (ORCPT ); Fri, 18 Sep 2020 09:23:12 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 854B552CD0D633A645F3; Fri, 18 Sep 2020 21:23:08 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:01 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 5/9] clocksource: sp804: prepare for support non-standard register offset Date: Fri, 18 Sep 2020 21:22:33 +0800 Message-ID: <20200918132237.3552-6-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add two local variables: timer1_base and timer2_base in sp804_of_init(), to avoid repeatedly calculate the base address of timer2, and make it easier to recognize timer1. Hope to make the next patch looks more clear. No functional change. Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp804.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) -- 1.8.3 diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index a443f392a8e7d63..471c5c6aaf51afd 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -188,6 +188,8 @@ static int __init sp804_of_init(struct device_node *np) { static bool initialized = false; void __iomem *base; + void __iomem *timer1_base; + void __iomem *timer2_base; int irq, ret = -EINVAL; u32 irq_num = 0; struct clk *clk1, *clk2; @@ -197,9 +199,12 @@ static int __init sp804_of_init(struct device_node *np) if (!base) return -ENXIO; + timer1_base = base; + timer2_base = base + TIMER_2_BASE; + /* Ensure timers are disabled */ - writel(0, base + TIMER_CTRL); - writel(0, base + TIMER_2_BASE + TIMER_CTRL); + writel(0, timer1_base + TIMER_CTRL); + writel(0, timer2_base + TIMER_CTRL); if (initialized || !of_device_is_available(np)) { ret = -EINVAL; @@ -228,21 +233,21 @@ static int __init sp804_of_init(struct device_node *np) of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); if (irq_num == 2) { - ret = sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); + ret = sp804_clockevents_init(timer2_base, irq, clk2, name); if (ret) goto err; - ret = sp804_clocksource_and_sched_clock_init(base, + ret = sp804_clocksource_and_sched_clock_init(timer1_base, name, clk1, 1); if (ret) goto err; } else { - ret = sp804_clockevents_init(base, irq, clk1, name); + ret = sp804_clockevents_init(timer1_base, irq, clk1, name); if (ret) goto err; - ret = sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, + ret = sp804_clocksource_and_sched_clock_init(timer2_base, name, clk2, 1); if (ret) goto err; From patchwork Fri Sep 18 13:22:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313195 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333735ilg; Fri, 18 Sep 2020 06:23:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxdMiOALEuOEe8peKxX9LsKB4YC+iEP+raa9a7qwD7J4Zjrx9qAhvPoHXZpvMAEpag1BHz0 X-Received: by 2002:aa7:ce15:: with SMTP id d21mr38561953edv.284.1600435425900; Fri, 18 Sep 2020 06:23:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435425; cv=none; d=google.com; s=arc-20160816; b=OYfcFhOPbDcnyhk7vj15I1EJX7HvuA2eG+OEz17vzFwZ1QAWvNqUs0j1D9y3Ilk8Mn W0FdaB+8F8e0r0SjWBvAonGtwdc3hbMZZNgDsKxY0WUCuxpJ5hMT8Ykc42UgzEaBjBIn 6Kr0bxWy764ijQUVJMpYP9LP4wY0kf9mDtA0C0QdaepJ3PeLy1rfXfxMJequ/FGnQyH/ MHVffWQVboo4Zt6jqUNcVnbR+n7vtc+umDxOBPcD3zgw4Xtai7rZF40zgqXL+QuqE9SK ICXNh9+bhQzKHfE9PyAwHeHnZADSd32xh8N2SjoRPVFTfGGxLSyMjUlscYgd1MTtSPCu FtbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=/Tmknmv4KzAmCc9Rf48zQegI5beZra8gPu4na4cvboM=; b=b6LpLKayK39qbhImgB13eRoet7hvO4XbeHlIDqG4teSCha/dYLg3WI4K286+mM+K78 aimnzzF/Pqq8HIyRzkAxb5qzpx2xcbjOs6A0v2lGiiTnAuNccexIFirHRKafEukCFM3B 19sxHyPMx+0WJ0OYfC1T+/a50RDCLIy6a0AgYHqla3xLT0CrkY4MPbeLQjBFjXDP12Pd 5M0BT7FkCRmYyopcNWwqImdC4Lgp2jfS/i/qKGkkniIcEjI3CTyta7ukIZeypE8bWUID grs2KxpZubbX4QS7uYdLTl+gxhdJxzeuDopiy8LdnX1BWZof2deMf81uryikFel+Ty9j YJcA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v5si2186445edr.49.2020.09.18.06.23.45; Fri, 18 Sep 2020 06:23:45 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726846AbgIRNXf (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:35 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:13309 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726698AbgIRNXN (ORCPT ); Fri, 18 Sep 2020 09:23:13 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 89F52A4931A7FB1009A9; Fri, 18 Sep 2020 21:23:08 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:02 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 6/9] clocksource: sp804: support non-standard register offset Date: Fri, 18 Sep 2020 21:22:34 +0800 Message-ID: <20200918132237.3552-7-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ARM SP804 supports a maximum of 32-bit counter, but Hisilicon extends it to 64-bit. That means, the registers: TimerXload, TimerXValue and TimerXBGLoad are 64bits, all other registers are the same as those in the SP804. The driver code can be completely reused except that the register offset is different. Currently, we get a timer register address by: add the constant register offset to the timer base address. e.g. "base + TIMER_CTRL". It can not be dynamically adjusted at run time. So create a new structure "sp804_timer" to record the original registers offset, and create a new structure "sp804_clkevt" to record the calculated registers address. So the "base + TIMER_CTRL" is changed to "clkevt->ctrl", this will faster than "base + timer->ctrl". For example: struct sp804_timer arm_sp804_timer = { .ctrl = TIMER_CTRL, }; struct sp804_clkevt clkevt; clkevt.ctrl = base + arm_sp804_timer.ctrl. - writel(0, base + TIMER_CTRL); + writel(0, clkevt->ctrl); Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp.h | 26 +++++++++ drivers/clocksource/timer-sp804.c | 108 +++++++++++++++++++++++++++++--------- 2 files changed, 108 insertions(+), 26 deletions(-) -- 1.8.3 diff --git a/drivers/clocksource/timer-sp.h b/drivers/clocksource/timer-sp.h index b2037eb94a41485..1ab75cbed0e09e5 100644 --- a/drivers/clocksource/timer-sp.h +++ b/drivers/clocksource/timer-sp.h @@ -10,6 +10,7 @@ * * Every SP804 contains two identical timers. */ +#define NR_TIMERS 2 #define TIMER_1_BASE 0x00 #define TIMER_2_BASE 0x20 @@ -29,3 +30,28 @@ #define TIMER_RIS 0x10 /* CVR ro */ #define TIMER_MIS 0x14 /* CVR ro */ #define TIMER_BGLOAD 0x18 /* CVR rw */ + +struct sp804_timer { + int load; + int value; + int ctrl; + int intclr; + int ris; + int mis; + int bgload; + int timer_base[NR_TIMERS]; + int width; +}; + +struct sp804_clkevt { + void __iomem *base; + void __iomem *load; + void __iomem *value; + void __iomem *ctrl; + void __iomem *intclr; + void __iomem *ris; + void __iomem *mis; + void __iomem *bgload; + unsigned long reload; + int width; +}; diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index 471c5c6aaf51afd..5f4f979a8ef2c10 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -20,6 +20,17 @@ #include "timer-sp.h" +struct sp804_timer __initdata arm_sp804_timer = { + .load = TIMER_LOAD, + .value = TIMER_VALUE, + .ctrl = TIMER_CTRL, + .intclr = TIMER_INTCLR, + .timer_base = {TIMER_1_BASE, TIMER_2_BASE}, + .width = 32, +}; + +static struct sp804_clkevt sp804_clkevt[NR_TIMERS]; + static long __init sp804_get_clock_rate(struct clk *clk, const char *name) { long rate; @@ -58,11 +69,26 @@ static long __init sp804_get_clock_rate(struct clk *clk, const char *name) return rate; } -static void __iomem *sched_clock_base; +static struct sp804_clkevt * __init sp804_clkevt_get(void __iomem *base) +{ + int i; + + for (i = 0; i < NR_TIMERS; i++) { + if (sp804_clkevt[i].base == base) + return &sp804_clkevt[i]; + } + + /* It's impossible to reach here */ + WARN_ON(1); + + return NULL; +} + +static struct sp804_clkevt *sched_clkevt; static u64 notrace sp804_read(void) { - return ~readl_relaxed(sched_clock_base + TIMER_VALUE); + return ~readl_relaxed(sched_clkevt->value); } int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, @@ -71,22 +97,25 @@ int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, int use_sched_clock) { long rate; + struct sp804_clkevt *clkevt; rate = sp804_get_clock_rate(clk, name); if (rate < 0) return -EINVAL; - writel(0, base + TIMER_CTRL); - writel(0xffffffff, base + TIMER_LOAD); - writel(0xffffffff, base + TIMER_VALUE); + clkevt = sp804_clkevt_get(base); + + writel(0, clkevt->ctrl); + writel(0xffffffff, clkevt->load); + writel(0xffffffff, clkevt->value); writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - base + TIMER_CTRL); + clkevt->ctrl); - clocksource_mmio_init(base + TIMER_VALUE, name, + clocksource_mmio_init(clkevt->value, name, rate, 200, 32, clocksource_mmio_readl_down); if (use_sched_clock) { - sched_clock_base = base; + sched_clkevt = clkevt; sched_clock_register(sp804_read, 32, rate); } @@ -94,8 +123,7 @@ int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, } -static void __iomem *clkevt_base; -static unsigned long clkevt_reload; +static struct sp804_clkevt *common_clkevt; /* * IRQ handler for the timer @@ -105,7 +133,7 @@ static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) struct clock_event_device *evt = dev_id; /* clear the interrupt */ - writel(1, clkevt_base + TIMER_INTCLR); + writel(1, common_clkevt->intclr); evt->event_handler(evt); @@ -114,7 +142,7 @@ static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) static inline void timer_shutdown(struct clock_event_device *evt) { - writel(0, clkevt_base + TIMER_CTRL); + writel(0, common_clkevt->ctrl); } static int sp804_shutdown(struct clock_event_device *evt) @@ -129,8 +157,8 @@ static int sp804_set_periodic(struct clock_event_device *evt) TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; timer_shutdown(evt); - writel(clkevt_reload, clkevt_base + TIMER_LOAD); - writel(ctrl, clkevt_base + TIMER_CTRL); + writel(common_clkevt->reload, common_clkevt->load); + writel(ctrl, common_clkevt->ctrl); return 0; } @@ -140,8 +168,8 @@ static int sp804_set_next_event(unsigned long next, unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE; - writel(next, clkevt_base + TIMER_LOAD); - writel(ctrl, clkevt_base + TIMER_CTRL); + writel(next, common_clkevt->load); + writel(ctrl, common_clkevt->ctrl); return 0; } @@ -168,13 +196,13 @@ int __init sp804_clockevents_init(void __iomem *base, unsigned int irq, if (rate < 0) return -EINVAL; - clkevt_base = base; - clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ); + common_clkevt = sp804_clkevt_get(base); + common_clkevt->reload = DIV_ROUND_CLOSEST(rate, HZ); evt->name = name; evt->irq = irq; evt->cpumask = cpu_possible_mask; - writel(0, base + TIMER_CTRL); + writel(0, common_clkevt->ctrl); if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, "timer", &sp804_clockevent)) @@ -184,7 +212,26 @@ int __init sp804_clockevents_init(void __iomem *base, unsigned int irq, return 0; } -static int __init sp804_of_init(struct device_node *np) +static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *base) +{ + int i; + + for (i = 0; i < NR_TIMERS; i++) { + void __iomem *timer_base; + struct sp804_clkevt *clkevt; + + timer_base = base + timer->timer_base[i]; + clkevt = &sp804_clkevt[i]; + clkevt->base = timer_base; + clkevt->load = timer_base + timer->load; + clkevt->value = timer_base + timer->value; + clkevt->ctrl = timer_base + timer->ctrl; + clkevt->intclr = timer_base + timer->intclr; + clkevt->width = timer->width; + } +} + +static int __init sp804_of_init(struct device_node *np, struct sp804_timer *timer) { static bool initialized = false; void __iomem *base; @@ -199,12 +246,12 @@ static int __init sp804_of_init(struct device_node *np) if (!base) return -ENXIO; - timer1_base = base; - timer2_base = base + TIMER_2_BASE; + timer1_base = base + timer->timer_base[0]; + timer2_base = base + timer->timer_base[1]; /* Ensure timers are disabled */ - writel(0, timer1_base + TIMER_CTRL); - writel(0, timer2_base + TIMER_CTRL); + writel(0, timer1_base + timer->ctrl); + writel(0, timer2_base + timer->ctrl); if (initialized || !of_device_is_available(np)) { ret = -EINVAL; @@ -230,6 +277,8 @@ static int __init sp804_of_init(struct device_node *np) if (irq <= 0) goto err; + sp804_clkevt_init(timer, base); + of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); if (irq_num == 2) { @@ -259,7 +308,12 @@ static int __init sp804_of_init(struct device_node *np) iounmap(base); return ret; } -TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init); + +static int __init arm_sp804_of_init(struct device_node *np) +{ + return sp804_of_init(np, &arm_sp804_timer); +} +TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init); static int __init integrator_cp_of_init(struct device_node *np) { @@ -282,11 +336,13 @@ static int __init integrator_cp_of_init(struct device_node *np) } /* Ensure timer is disabled */ - writel(0, base + TIMER_CTRL); + writel(0, base + arm_sp804_timer.ctrl); if (init_count == 2 || !of_device_is_available(np)) goto err; + sp804_clkevt_init(&arm_sp804_timer, base); + if (!init_count) { ret = sp804_clocksource_and_sched_clock_init(base, name, clk, 0); From patchwork Fri Sep 18 13:22:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313193 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333540ilg; Fri, 18 Sep 2020 06:23:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz5r6KaZampNmrDn7FZVocleh+Bw5CBoZtgDSw7ncJfiLUeSak4oAHhlTfZumQvXfAbI+hx X-Received: by 2002:a17:906:d9d9:: with SMTP id qk25mr5497078ejb.51.1600435415054; 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[23.128.96.18]) by mx.google.com with ESMTP id z1si2094545edx.584.2020.09.18.06.23.34; Fri, 18 Sep 2020 06:23:35 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726798AbgIRNXR (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:17 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:59474 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726773AbgIRNXQ (ORCPT ); Fri, 18 Sep 2020 09:23:16 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 87433CAB032223C9E7FE; Fri, 18 Sep 2020 21:23:13 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:02 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 7/9] clocksource: sp804: add support for Hisilicon sp804 timer Date: Fri, 18 Sep 2020 21:22:35 +0800 Message-ID: <20200918132237.3552-8-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ARM SP804 supports a maximum of 32-bit counter, but Hisilicon extends it to 64-bit. That means, the registers: TimerXload, TimerXValue and TimerXBGLoad are 64bits, all other registers are the same as those in the SP804. The driver code can be completely reused except that the register offset is different. Use compatible = "hisilicon,sp804" mark as Hisilicon sp804 timer. Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp804.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) -- 1.8.3 diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index 5f4f979a8ef2c10..f0783d19522f048 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -20,6 +20,18 @@ #include "timer-sp.h" +/* Hisilicon 64-bit timer(a variant of ARM SP804) */ +#define HISI_TIMER_1_BASE 0x00 +#define HISI_TIMER_2_BASE 0x40 +#define HISI_TIMER_LOAD 0x00 +#define HISI_TIMER_VALUE 0x08 +#define HISI_TIMER_CTRL 0x10 +#define HISI_TIMER_INTCLR 0x14 +#define HISI_TIMER_RIS 0x18 +#define HISI_TIMER_MIS 0x1c +#define HISI_TIMER_BGLOAD 0x20 + + struct sp804_timer __initdata arm_sp804_timer = { .load = TIMER_LOAD, .value = TIMER_VALUE, @@ -29,6 +41,15 @@ struct sp804_timer __initdata arm_sp804_timer = { .width = 32, }; +struct sp804_timer __initdata hisi_sp804_timer = { + .load = HISI_TIMER_LOAD, + .value = HISI_TIMER_VALUE, + .ctrl = HISI_TIMER_CTRL, + .intclr = HISI_TIMER_INTCLR, + .timer_base = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE}, + .width = 64, +}; + static struct sp804_clkevt sp804_clkevt[NR_TIMERS]; static long __init sp804_get_clock_rate(struct clk *clk, const char *name) @@ -315,6 +336,12 @@ static int __init arm_sp804_of_init(struct device_node *np) } TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init); +static int __init hisi_sp804_of_init(struct device_node *np) +{ + return sp804_of_init(np, &hisi_sp804_timer); +} +TIMER_OF_DECLARE(hisi_sp804, "hisilicon,sp804", hisi_sp804_of_init); + static int __init integrator_cp_of_init(struct device_node *np) { static int init_count = 0; From patchwork Fri Sep 18 13:22:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313192 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333532ilg; Fri, 18 Sep 2020 06:23:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzenjc+BpWDIF0I8MbTPjH4yLgaqiLQ8quQhMkEEWCIEWh4GjKmzUvahHMr1EwTdIlEPdDn X-Received: by 2002:a17:906:f1d5:: with SMTP id gx21mr33992339ejb.165.1600435414588; Fri, 18 Sep 2020 06:23:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435414; cv=none; d=google.com; s=arc-20160816; b=eSppM7Z8lRpNI079zHUQxCe1pKKCDO1rSrhID6kCQMAXgqyBNgnkaFaWBLT3XkMmGN pWyKQbHKD+sL9vgcIzVszw5mm7J0+azVKIWEokIed7RDiZdgpMWrFnrFbE72BGePLVj6 JCABU4CAVhTWxoL+A57CNOow6JZHb9PlrG6EbZW60XtgDgyfd6CMMBgt92fGhTnFXxWB a+LiU+B7VR/ZYGHw/6/mXzVxy9CWcDYD7mHlcdRJmxYt6gIu6QkLtQ5R+78DX/H1RBFz XjYlNXswaYF0L7+NeDHbHs9WgunjVFnQC+CdIMLT824Jgy2fdzyfrmX9qnvV7w6ezY1Z 2j6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=iS/+QKeGUcdLyaz3EkJwK8NVcNKZsgz7jbQ84l/NzmQ=; b=kuqn909YNkGbkO7gZTLjqqdZ4tOjHnxEZvG+w2DLWUqb2bo3rQc84pSW1bDihQbkMX QScDLMoytuF+gjB3SXQfjg+XMqM2e/MDTpsXxKYUnCQhZsRm76+vgqCASs8sjKUvAS7K 5tNFVKZdt6o/8GgiiQlUmMuIKGtdEJG4HXvE9rZeF1eEaf8nvW2KPuOagPOgjWsIl34d M7mby8tKU81Ehxrlki51xLYAI0b+xgmjrWHlkm/rHQHp/mKbJykJguusDph55R1b2Lg/ Nh+I7P38Fpbwn8L65/1cSwRNoEyHVNEByGgx8LLzTlYu/3yUBkBNvGzS9nPp/BbgclzX FLDA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z1si2094545edx.584.2020.09.18.06.23.34; Fri, 18 Sep 2020 06:23:34 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726821AbgIRNXZ (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:25 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:59478 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726778AbgIRNXT (ORCPT ); Fri, 18 Sep 2020 09:23:19 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 81C4D9DA680EC872A5B6; Fri, 18 Sep 2020 21:23:13 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:03 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 8/9] clocksource: sp804: enable Hisilicon sp804 timer 64bit mode Date: Fri, 18 Sep 2020 21:22:36 +0800 Message-ID: <20200918132237.3552-9-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A 100MHZ 32-bit timer will be wrapped up less than 43s. Although the kernel maintains a software high 32-bit count in the tick IRQ. But it's not applicable to the user mode APPs. Note: The kernel still uses the lower 32 bits of the timer. Signed-off-by: Zhen Lei --- drivers/clocksource/timer-sp.h | 6 ++++++ drivers/clocksource/timer-sp804.c | 11 +++++++++++ 2 files changed, 17 insertions(+) -- 1.8.3 diff --git a/drivers/clocksource/timer-sp.h b/drivers/clocksource/timer-sp.h index 1ab75cbed0e09e5..811f840be0e52fd 100644 --- a/drivers/clocksource/timer-sp.h +++ b/drivers/clocksource/timer-sp.h @@ -33,12 +33,15 @@ struct sp804_timer { int load; + int load_h; int value; + int value_h; int ctrl; int intclr; int ris; int mis; int bgload; + int bgload_h; int timer_base[NR_TIMERS]; int width; }; @@ -46,12 +49,15 @@ struct sp804_timer { struct sp804_clkevt { void __iomem *base; void __iomem *load; + void __iomem *load_h; void __iomem *value; + void __iomem *value_h; void __iomem *ctrl; void __iomem *intclr; void __iomem *ris; void __iomem *mis; void __iomem *bgload; + void __iomem *bgload_h; unsigned long reload; int width; }; diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c index f0783d19522f048..6e8ad4a4ea3c737 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -24,12 +24,15 @@ #define HISI_TIMER_1_BASE 0x00 #define HISI_TIMER_2_BASE 0x40 #define HISI_TIMER_LOAD 0x00 +#define HISI_TIMER_LOAD_H 0x04 #define HISI_TIMER_VALUE 0x08 +#define HISI_TIMER_VALUE_H 0x0c #define HISI_TIMER_CTRL 0x10 #define HISI_TIMER_INTCLR 0x14 #define HISI_TIMER_RIS 0x18 #define HISI_TIMER_MIS 0x1c #define HISI_TIMER_BGLOAD 0x20 +#define HISI_TIMER_BGLOAD_H 0x24 struct sp804_timer __initdata arm_sp804_timer = { @@ -43,7 +46,9 @@ struct sp804_timer __initdata arm_sp804_timer = { struct sp804_timer __initdata hisi_sp804_timer = { .load = HISI_TIMER_LOAD, + .load_h = HISI_TIMER_LOAD_H, .value = HISI_TIMER_VALUE, + .value_h = HISI_TIMER_VALUE_H, .ctrl = HISI_TIMER_CTRL, .intclr = HISI_TIMER_INTCLR, .timer_base = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE}, @@ -129,6 +134,10 @@ int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, writel(0, clkevt->ctrl); writel(0xffffffff, clkevt->load); writel(0xffffffff, clkevt->value); + if (clkevt->width == 64) { + writel(0xffffffff, clkevt->load_h); + writel(0xffffffff, clkevt->value_h); + } writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, clkevt->ctrl); @@ -245,7 +254,9 @@ static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *ba clkevt = &sp804_clkevt[i]; clkevt->base = timer_base; clkevt->load = timer_base + timer->load; + clkevt->load_h = timer_base + timer->load_h; clkevt->value = timer_base + timer->value; + clkevt->value_h = timer_base + timer->value_h; clkevt->ctrl = timer_base + timer->ctrl; clkevt->intclr = timer_base + timer->intclr; clkevt->width = timer->width; From patchwork Fri Sep 18 13:22:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 313190 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp1333316ilg; Fri, 18 Sep 2020 06:23:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyP8zP2kuE9LNS2CJsClTqqB1Tu80At/2q7dtHbTKckWgvcIrZU1h0zB4pZsb1mzEM4t4wP X-Received: by 2002:a50:d2d1:: with SMTP id q17mr38639101edg.167.1600435399392; Fri, 18 Sep 2020 06:23:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600435399; cv=none; d=google.com; s=arc-20160816; b=FnVp5LJPW1zOrhtByhKFwlFAltgLBTkciilixTgerx+yoD3qsTdckFGeXnK5qhwZGV rhPppSPN8nySe+BPTX2xRwc09pemdEsYyBSBSTL/7HivViMM4OYZOWXHpCIoYJeSnG8c oz5gA3laeGDCBLA8cY2RZ4xmhxE2HhtBLwify/Qdjh0cW3vFDjMI/rBQ5MtQcC8j5lv/ OgjbMfd56FZz4gRNWKLYxeTwQn2tpY6r0hgBDgD8AmIUIYzgc0WzwTHuihNybiQF9Ui0 0N05HHBvagi4KBK+e4XL1VIv8jIZ7bPBxmhZdKSDi4+8mrIROIiIfw9Th7vbQQPE/Z7a kOZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=nSpGz1I1JCh9AExeS5tcimKz15PuRAGKHK1yvVfhZiQ=; b=UIg4VQo3H88DuHmB4VAZaWB46mkYvYSQ/vyQ43Wyam/827mboS+HhISZEzhwwAQv3W t/CQ5qvYS9pWs7hm2fz8kEf1D/m1W3r0C5AqaGQK6jA73IOL5W6axRLFBF+I3u4KzxtP LOwXuz3wUUi3IgtOQ1+DqS8xa8WKscVVaQgLNdAf4QkaynhjTqSMCDzjIyw+3MMM5+P2 VEm5NXP1+BSaZvr9FObTd5OVsmFx+iZhY1dYwyV8OmNTGWiIn75JPBZNetvgqiJkEcV+ +q1Q5r/1rpQ7VUKG4rKlnnMxub3ZW5cVX7QXAClxvs3TT5Pfr93rtZVCAHgP6x9WRRuD JhpQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b7si2304157ejj.57.2020.09.18.06.23.19; Fri, 18 Sep 2020 06:23:19 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726121AbgIRNXQ (ORCPT + 6 others); Fri, 18 Sep 2020 09:23:16 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:59476 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726786AbgIRNXQ (ORCPT ); Fri, 18 Sep 2020 09:23:16 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8C679BFC77A73522B7DA; Fri, 18 Sep 2020 21:23:13 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 18 Sep 2020 21:23:04 +0800 From: Zhen Lei To: Rob Herring , devicetree , Daniel Lezcano , Thomas Gleixner , Haojian Zhuang , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang , Jianguo Chen Subject: [PATCH v3 9/9] dt-bindings: sp804: add support for Hisilicon sp804 timer Date: Fri, 18 Sep 2020 21:22:37 +0800 Message-ID: <20200918132237.3552-10-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200918132237.3552-1-thunder.leizhen@huawei.com> References: <20200918132237.3552-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some Hisilicon SoCs, such as Hi1212, use the Hisilicon extended sp804 timer. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/timer/arm,sp804.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.yaml b/Documentation/devicetree/bindings/timer/arm,sp804.yaml index ba0945cf799ee0b..06dfcbcc7b24255 100644 --- a/Documentation/devicetree/bindings/timer/arm,sp804.yaml +++ b/Documentation/devicetree/bindings/timer/arm,sp804.yaml @@ -15,6 +15,9 @@ description: |+ free-running mode. The input clock is shared, but can be gated and prescaled independently for each timer. + There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon + SoCs, such as Hi1212, should use the dedicated compatible: "hisilicon,sp804". + # Need a custom select here or 'arm,primecell' will match on lots of nodes select: properties: @@ -27,7 +30,9 @@ select: properties: compatible: items: - - const: arm,sp804 + - enum: + - arm,sp804 + - hisilicon,sp804 - const: arm,primecell interrupts: