From patchwork Wed Sep 16 16:34:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 312564 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp651839ilg; Wed, 16 Sep 2020 10:10:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyHSDyLPMqnzTb62uxGX+0gCp6+SVOjckYndTJRwK+5MKYzJl5H5tjfGQNH6IeF7J64wzrm X-Received: by 2002:a50:84e8:: with SMTP id 95mr28046451edq.99.1600276251392; Wed, 16 Sep 2020 10:10:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600276251; cv=none; d=google.com; s=arc-20160816; b=k8QnsZx/ejTLLsP0uh8RyfF3fyAqKGJa0Ob8mn7FBH45cUH4FvdJTblAU9R/y0RLaA Sia77jcbBNrqRmS9yB3km1FwzP4COvnUUJHmsvAlqAQi3OUMrIfuN9eYzKSlji82Gy42 ZIUKEIsbKATwuF210hHOhwC+TMbJjUGYAY79XZHXwx1/0sg3eR8mL5Ks4CvSJyYBUE/5 wIEe0aOfwKcmB/kRzsKetOKcVNP+vZfR9B6lRXTrUFsVF7iQCL3PxqioMPsptS8Dsou5 kvIy1P8efVelute7xRjDcvyXBb8LoF8KzYX6yGU4hsjE1fMNhdlduZMUyvDpCIIiYRaG czXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature; bh=K2uIlebY3b0dggEI+w9z29n5jxZsIoBXf8cK7cjdc8g=; b=l0y7j2VjCpErGmtmgpgREk7i+OvOIwyXIrlLYXGHL7kDbr1mVmzAmSJdBWDZTAHJ5p iYhL3t0ML8JB8vQg+o+94Eg5+NASmmRjS7WzklAWRmHcJY196DyvtvhkDvBV4cCBJNrn 9123NQVDRfTb/gDKKGM3iYWXmbXXj0l8bKAUip6aAMIwPavJqoyvYlXlteNemr6ZsCgs 88OHndZwdEeKXUPo10JLwDsFWIjYhR4avN00F2qAugt7LT6N84cPEPbNrzYUt/6NWx5l g4fUfnaAU+FtEyLRhSIF9bGEYHCeiui9g0cFgdYwmMsYv9nIjNF9DCJq9Jt9+mmOSdVj ly2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yNdLVgRo; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u12si11817627edy.390.2020.09.16.10.10.51; Wed, 16 Sep 2020 10:10:51 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yNdLVgRo; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726877AbgIPRKb (ORCPT + 6 others); Wed, 16 Sep 2020 13:10:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726855AbgIPRJW (ORCPT ); Wed, 16 Sep 2020 13:09:22 -0400 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 537A8C06121C for ; Wed, 16 Sep 2020 09:35:03 -0700 (PDT) Received: by mail-lf1-x141.google.com with SMTP id x77so7720169lfa.0 for ; Wed, 16 Sep 2020 09:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=K2uIlebY3b0dggEI+w9z29n5jxZsIoBXf8cK7cjdc8g=; b=yNdLVgRokoCFPciBBgZXzSRjZpVjKUhrmR30+a+ah87120ONcYyhwy0sp7do7wyVH7 xb9KIvb4CtEF96QtTjeCczmZ2eWiNtJq/bQeBO3NJFZyLMW3h0JGcNE4DRSmZ7E13t16 pQIH1GGfMREIjmcDpxpMC+TiGgD/O/jkRsfQRQ+zVhA4+yqutMJzf9bNEaq56d7VjxAU WyZkQMW3HYaOYfV208P8QdhjGy7wYWzI2keBgKPPDoDDfxRZT3mnNaMROHqLe7mwebuF 7sFo5MolLP9eQjF6N5C78aOjhAX8l+o1iJ6Ejdvc603rhKSDMREsnxQfXo/xZRPwRfVx bpYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=K2uIlebY3b0dggEI+w9z29n5jxZsIoBXf8cK7cjdc8g=; b=e0rsZo3wOxq/XMEutPI0qNfYiqEKmkuUUXIOU3JtMOOQlYk2A9uZ82hi/bJ0/MmlaQ lxoWG/B/2diCQ8QYUHOqHcFPSKTjChn4BnypTgsc0Anvo2oW2neLlaruv7+IwTzGJUuo 4b6qaxgTAw42m6fqv10TrZJ7vynaPZE4NPMMw91sfZqhQXabK+7gEhCrgoLiaNrML3By FwS0oan5iMJ4E6SYfa7C2933AF1We2MM7mjfMugIHm2ikKJOV4uhNkCCM7MzmGPh5Swv yhOiNXIo4it4wbJ1FQZhqoCHEKF5LSubXXP5eVY8StGrc4T9LIQ9uD0VyIeeG7kVGumT wyBQ== X-Gm-Message-State: AOAM530hkfPLt1h5BJ1N8Hlyh3ecKIazFuTyeal/JGxzUsH8SQR9WaA2 XuOD2zIm9AiaEJsPuidRUvFMsg== X-Received: by 2002:ac2:5333:: with SMTP id f19mr9214308lfh.339.1600274100104; Wed, 16 Sep 2020 09:35:00 -0700 (PDT) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id u24sm513058lfo.117.2020.09.16.09.34.58 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Sep 2020 09:34:59 -0700 (PDT) From: Grzegorz Jaszczyk To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, david@lechnology.com, praneeth@ti.com, rogerq@ti.com Subject: [PATCH v7 1/5] dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings Date: Wed, 16 Sep 2020 18:34:54 +0200 Message-Id: <1600274094-30342-1-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna The Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS or simply PRUSS) contains an interrupt controller (INTC) that can handle various system input events and post interrupts back to the device-level initiators. The INTC can support up to 64 input events on most SoCs with individual control configuration and h/w prioritization. These events are mapped onto 10 output interrupt lines through two levels of many-to-one mapping support. Different interrupt lines are routed to the individual PRU cores or to the host CPU or to other PRUSS instances. The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide a higher number of host interrupts (20 vs 10) and can handle an increased number of input events (160 vs 64) from various SoC interrupt sources. Add the bindings document for these interrupt controllers on all the applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci architecture based OMAPL138 SoCs, and the K3 architecture based AM65x and J721E SoCs. Co-developed-by: Andrew F. Davis Signed-off-by: Andrew F. Davis Co-developed-by: Roger Quadros Signed-off-by: Roger Quadros Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Rob Herring --- v6->v7: - Add Co-developed-by tags. - Drop afd@ti.com from tags as the address doesn't exist anymore. v5->v6: - No change. v4->v5: - Fix typo in commit description. - Update interrupt-cells description regarding each cells meaning. v3->v4: - Drop allOf references to interrupt-controller.yaml and interrupts.yaml. - Drop items descriptions and use only maxItems: 1 as suggested by Rob. - Convert irqs-reserved property from uint8-array to bitmask. - Minor descriptions updates. - Change interrupt-cells to 3 in order to provide 2-level mapping description for interrupts routed to the main CPU (as Marc requested). - Merge the irqs-reserved and irqs-shared to one property since they can be handled by one logic. - Drop reviewed-by due to introduced changes. - Add another example illustrating irqs-reserved property usage. v2->v3: - Convert dt-binding to YAML v1->v2: - https://patchwork.kernel.org/patch/11069767/ --- .../interrupt-controller/ti,pruss-intc.yaml | 158 +++++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml -- 2.7.4 diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml new file mode 100644 index 0000000..bbf79d1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI PRU-ICSS Local Interrupt Controller + +maintainers: + - Suman Anna + +description: | + Each PRU-ICSS has a single interrupt controller instance that is common + to all the PRU cores. Most interrupt controllers can route 64 input events + which are then mapped to 10 possible output interrupts through two levels + of mapping. The input events can be triggered by either the PRUs and/or + various other PRUSS internal and external peripherals. The first 2 output + interrupts (0, 1) are fed exclusively to the internal PRU cores, with the + remaining 8 (2 through 9) connected to external interrupt controllers + including the MPU and/or other PRUSS instances, DSPs or devices. + + The property "ti,irqs-reserved" is used for denoting the connection + differences on the output interrupts 2 through 9. If this property is not + defined, it implies that all the PRUSS INTC output interrupts 2 through 9 + (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt + controller. + + The K3 family of SoCs can handle 160 input events that can be mapped to 20 + different possible output interrupts. The additional output interrupts (10 + through 19) are connected to new sub-modules within the ICSSG instances. + + This interrupt-controller node should be defined as a child node of the + corresponding PRUSS node. The node should be named "interrupt-controller". + +properties: + compatible: + enum: + - ti,pruss-intc + - ti,icssg-intc + description: | + Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs, + AM335x family of SoCs, + AM437x family of SoCs, + AM57xx family of SoCs + 66AK2G family of SoCs + Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 8 + description: | + All the interrupts generated towards the main host processor in the SoC. + A shared interrupt can be skipped if the desired destination and usage is + by a different processor/device. + + interrupt-names: + minItems: 1 + maxItems: 8 + items: + pattern: host_intr[0-7] + description: | + Should use one of the above names for each valid host event interrupt + connected to Arm interrupt controller, the name should match the + corresponding host event interrupt number. + + interrupt-controller: true + + "#interrupt-cells": + const: 3 + description: | + Client users shall use the PRU System event number (the interrupt source + that the client is interested in) [cell 1], PRU channel [cell 2] and PRU + host_event (target) [cell 3] as the value of the interrupts property in + their node. The system events can be mapped to some output host + interrupts through 2 levels of many-to-one mapping i.e. events to channel + mapping and channels to host interrupts so through this property entire + mapping is provided. + + ti,irqs-reserved: + $ref: /schemas/types.yaml#definitions/uint8 + description: | + Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC + output interrupts 2 through 9) that are not connected to the Arm interrupt + controller or are shared and used by other devices or processors in the + SoC. Define this property when any of 8 interrupts should not be handled + by Arm interrupt controller. + Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt + connected to MPU + - AM65x and J721E SoCs have "host_intr5", "host_intr6" and + "host_intr7" interrupts connected to MPU, and other ICSSG + instances. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + /* AM33xx PRU-ICSS */ + pruss: pruss@0 { + compatible = "ti,am3356-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; + + - | + + /* AM4376 PRU-ICSS */ + #include + pruss@0 { + compatible = "ti,am4376-pruss"; + reg = <0x0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", + "host_intr6", "host_intr7"; + ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ + }; + }; From patchwork Wed Sep 16 16:36:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 312688 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp788741ilg; Wed, 16 Sep 2020 13:37:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzX+XrV4yzvW/qcL9mFVIhn3+uMyiUxU2Upq+gqlkBLF/AgQ1t0tCf829qGylAm5XJLHQ2H X-Received: by 2002:a17:906:5452:: with SMTP id d18mr28243400ejp.163.1600288665219; Wed, 16 Sep 2020 13:37:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600288665; cv=none; d=google.com; s=arc-20160816; b=mosp6JBpdYswkoP+GC+Hl/TtJVGLDmED0DFtc5/s4KKehWH5dSiw02V5CNU58CFf9u 5MvhL/ZfYu6MLUiUOHzgmQ6SXexrtPUcxvdVXyCWN/px+Ua3yMPygldu8t+Xn9Mhjh4P f0/2pRfqXPzTdDwR8Zix9HWz+VfXSrXdprF6kO1wEY/yqbOvjZZvjYiKo3PmKqRc/fqv noHgLOlgYzrkg2CAs3z2kKQfVcBG5PKr4nQR7BFgfyL46SPiIHcNIL3/KxCpcGuoSyQo 8d5AuPQllk2OLhG81kkY6VVUFLGXobauFozIasbw3KrnwImH4dm0P6UB0NOC791jYR1F ekYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature; bh=jMYu4kXE2sjgBZ9G0n0UMw/4sfdmoPqRtdExz+XAFWs=; b=PsMOIYLWYl2WGWaiUDlKA54cJwCQZuyfR+kIcvVKOMKZOGNO977fdQGWN1eCJX2Ocp xe+mAfiUcQ+IMql9T/XF8nML+X86WV23VYQySimZWDRyNpZllFhS39EAr0EMxWF25USj 6ca7dGf6f2wpGbgIzWqsJmu71rekCp1kXfACpayPFNv2T140mqT0iOEHQn1yHe3+j13+ hhh3t3aAJvOPxONp4+9jhV4gkS/ZDobSHBtw4t7jhDhcfQpKejRaGPjfgwChfEVny4nf d3fUW0oHDWNrW3bw/NfjQa0NVD9DYELdx7zSmzPhxTnChJ+bDGmF2GoCeymEFzeTq5lN VOiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="iA8Gq/Yn"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id g11si13487305edn.496.2020.09.16.13.37.45; Wed, 16 Sep 2020 13:37:45 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="iA8Gq/Yn"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727013AbgIPUhm (ORCPT + 6 others); Wed, 16 Sep 2020 16:37:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726859AbgIPRJW (ORCPT ); Wed, 16 Sep 2020 13:09:22 -0400 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15280C02C295 for ; Wed, 16 Sep 2020 09:37:04 -0700 (PDT) Received: by mail-lf1-x142.google.com with SMTP id q8so7684362lfb.6 for ; Wed, 16 Sep 2020 09:37:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=jMYu4kXE2sjgBZ9G0n0UMw/4sfdmoPqRtdExz+XAFWs=; b=iA8Gq/YnrRpNj705xinp0UvGfAmmUb+FvDWYzbCZILwOStSmi7k7yRicuZ+OFi/Jey EYzGUzcOj1of4kQDN1doygwRCKgkrt1JJyrVwb4lNKemp+17ZddMKiRSlm7auBl/dzOm NFt7vL8nLyuqg85P0OYs8MyEIJ6apy0XF1E7TB6XuJ9YJTwoE8Ri2FYgXCFIW7DwX/kJ MpLNtn1Ms8hNKP/k0kLPjRsS4wWv6sP5m+Et+WGAUh82IJYa43b6pdiC4UlQ//N7Iq70 q0TYiP/+HhXSaaEB1OC6rYWlZ6/WdxdjGMKczjYg8I9zdCjETU5ljUoluDcDZfpzaxR/ 7hzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=jMYu4kXE2sjgBZ9G0n0UMw/4sfdmoPqRtdExz+XAFWs=; b=gpnhm3AMaszeYkivrLRQZ1XwFswXzqmJvlfIcFqpS4J0Gywtjcdx/X2k9GLT4lyJph uk1p/lTZ2Scgpc55rYaJYflHk5NnwNOEOQWEn5VoBAmFqHG7ay92Wg7kFzAnB5uGu/N1 oLVs2f4EFA8dZp71cYd9ZGVXY6Ggg0qc71pqHu0i70thXXlc+rgkvacgS7VCamfN+6D6 ziSl/QWfB+GHhxqC6H2WI3Isl6wpvfJ91EVdUaPR5oNHnPzTekr4SHsF9CX9I0LF0/YW P4byg0/yU4JofcvU+ixFM+0Myhin+5Q3Qakr56I3gAzdXa4helquWPrdyiA68zmZmN5Z xTYg== X-Gm-Message-State: AOAM531p2WuD6juYWl6ha+UPexOjT+RZUkSstVFblPh4kWRBGSBeroJJ 3j/aZk9wBEngRBvbHapKIMSyiglPcxMp3Q== X-Received: by 2002:ac2:494f:: with SMTP id o15mr2729070lfi.355.1600274222391; Wed, 16 Sep 2020 09:37:02 -0700 (PDT) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id o15sm4684400lfo.188.2020.09.16.09.37.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Sep 2020 09:37:01 -0700 (PDT) From: Grzegorz Jaszczyk To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, david@lechnology.com, praneeth@ti.com Subject: [PATCH v7 3/5] irqchip/irq-pruss-intc: Add logic for handling reserved interrupts Date: Wed, 16 Sep 2020 18:36:36 +0200 Message-Id: <1600274198-30470-1-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna The PRUSS INTC has a fixed number of output interrupt lines that are connected to a number of processors or other PRUSS instances or other devices (like DMA) on the SoC. The output interrupt lines 2 through 9 are usually connected to the main Arm host processor and are referred to as host interrupts 0 through 7 from ARM/MPU perspective. All of these 8 host interrupts are not always exclusively connected to the Arm interrupt controller. Some SoCs have some interrupt lines not connected to the Arm interrupt controller at all, while a few others have the interrupt lines connected to multiple processors in which they need to be partitioned as per SoC integration needs. For example, AM437x and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt 5 connected to the other PRUSS, while AM335x has host interrupt 0 shared between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU and a DMA controller. Add logic to the PRUSS INTC driver to ignore both these shared and invalid interrupts. Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk --- v6->v7: - Add Co-developed-by tag. v5->v6: - No change. v4->v5: - Rename: s/invalid_intr/irqs_reserved/ v3->v4: - Due to changes in DT bindings which converts irqs-reserved property from uint8-array to bitmask requested by Rob introduce relevant changes in the driver. - Merge the irqs-reserved and irqs-shared to one property since they can be handled by one logic (relevant change was introduced to DT binding). - Update commit message. v2->v3: - Extra checks for (intc->irqs[i]) in error/remove path was moved from "irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts" to this patch v1->v2: - https://patchwork.kernel.org/patch/11069757/ --- drivers/irqchip/irq-pruss-intc.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index c8bdef4..e7ba358 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -484,7 +484,7 @@ static int pruss_intc_probe(struct platform_device *pdev) struct pruss_intc *intc; struct pruss_host_irq_data *host_data; int i, irq, ret; - u8 max_system_events; + u8 max_system_events, irqs_reserved = 0; data = of_device_get_match_data(dev); if (!data) @@ -504,6 +504,16 @@ static int pruss_intc_probe(struct platform_device *pdev) if (IS_ERR(intc->base)) return PTR_ERR(intc->base); + ret = of_property_read_u8(dev->of_node, "ti,irqs-reserved", + &irqs_reserved); + + /* + * The irqs-reserved is used only for some SoC's therefore not having + * this property is still valid + */ + if (ret < 0 && ret != -EINVAL) + return ret; + pruss_intc_init(intc); mutex_init(&intc->lock); @@ -514,6 +524,9 @@ static int pruss_intc_probe(struct platform_device *pdev) return -ENOMEM; for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { + if (irqs_reserved & BIT(i)) + continue; + irq = platform_get_irq_byname(pdev, irq_names[i]); if (irq <= 0) { ret = (irq == 0) ? -EINVAL : irq; @@ -538,8 +551,11 @@ static int pruss_intc_probe(struct platform_device *pdev) return 0; fail_irq: - while (--i >= 0) - irq_set_chained_handler_and_data(intc->irqs[i], NULL, NULL); + while (--i >= 0) { + if (intc->irqs[i]) + irq_set_chained_handler_and_data(intc->irqs[i], NULL, + NULL); + } irq_domain_remove(intc->domain); @@ -553,8 +569,11 @@ static int pruss_intc_remove(struct platform_device *pdev) unsigned int hwirq; int i; - for (i = 0; i < MAX_NUM_HOST_IRQS; i++) - irq_set_chained_handler_and_data(intc->irqs[i], NULL, NULL); + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { + if (intc->irqs[i]) + irq_set_chained_handler_and_data(intc->irqs[i], NULL, + NULL); + } for (hwirq = 0; hwirq < max_system_events; hwirq++) irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq)); From patchwork Wed Sep 16 16:36:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 312686 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp788696ilg; Wed, 16 Sep 2020 13:37:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyvbUXVNvlt3PSa5iDjcIkaL8hdfkTtExGalfxrULINAgIFXylBSCxlBPyq9xsrKZl9ab78 X-Received: by 2002:a50:ec12:: with SMTP id g18mr20185796edr.309.1600288661587; Wed, 16 Sep 2020 13:37:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600288661; cv=none; d=google.com; s=arc-20160816; b=pAd0Y2mK36g9U2EmHhiphCAO5ehrklyT1N3mD2aGfkMXDelr2dpXXVvaV1lu8fF9zN 9+qvY25ptVf2HF09hYtfgmPckNyj6xXPXnglqVkqiv9lc2mwuB8XMQC4ZXQJ0tXjlyUL VtrKqcC9z8+6jhS8zGiVa+/kEBSkccEo/T2cr9kh6oY4wtjmiFHKGGfrX8WIxuq/fu8e UhX0aVGXH9TkGteFcJJH4X4QrdVTwOn6WjoSdCLaNfljnvMZXS0Cly6a/Lc7CJtaq52s qxC3WsfA+LYRocwONmwCvZZH0ugYs7abU9BxR/yz5sdyNNq4HASNFDZ9KI00nTytid61 3m+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=EkdGaMAWsiITjixL8vtqkk4znvOu3Q/xzFs2YIEcfEY=; b=T/UnDp1Ww6vHp3+LHkPRB6hj2bvDZJiwlVoSD1XyvM4UV7MfwcPHyhfyGgMsS08w41 tWTU45k5XjH50XarwOF2xX8rvtvNlXBO6QtJe4UZ35HhpuLvdgnGrpTqrn4fVgCQ2KEY 0dkzepbo8nKaqYoRNXyOS7xRfCydu5WV8+opKdxANsiXsCPUoUIHCGDobyQPQo4ZJk0R y2veciOnble43ly8liEPw5FJZv0mVZz7WZJQU6pDs+kvwcLSrlZg2dxVsF5tTZh0EkCg JafjlnOHoPBSvUhYz1sH9o6OyD3udJFh//+Gkn4NN3KSAOunesGYyA7SDokivLweLowy ITNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dpvpqsnv; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id o22si14097743edr.356.2020.09.16.13.37.41; Wed, 16 Sep 2020 13:37:41 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dpvpqsnv; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726361AbgIPUhh (ORCPT + 6 others); Wed, 16 Sep 2020 16:37:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726672AbgIPRKN (ORCPT ); Wed, 16 Sep 2020 13:10:13 -0400 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F05D4C02C2B6 for ; Wed, 16 Sep 2020 09:37:09 -0700 (PDT) Received: by mail-lj1-x242.google.com with SMTP id b19so6457707lji.11 for ; Wed, 16 Sep 2020 09:37:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EkdGaMAWsiITjixL8vtqkk4znvOu3Q/xzFs2YIEcfEY=; b=dpvpqsnv1se+B+N0B3X73ZARW0xp0qYtrllJbwUMEaTaPYAhDr3QA1JvBn8NUzvi/Z s8/YO99GSsIQU66VS4Y21URWzrqFy3MCSfvxw+pZqn4rifzBbNx2BJgMeksakO170Z52 JPksnTeACT5MlZRIedoBUIaPfuTTJMYrmuNm4nBCXCwlym2M+aUB2z4kYkJ0ouJaSY00 70k7LERJHRRCJjPRwRId0KijyzilqRY9bkwG2n2Sba11nDKP2TEzW5F79CkYt4U8RCAV +RMne5o9ys2+dp6NFUda1mLsnvldt8KlUv+Tr51FA+G/lZn1INDC4VhR7AUJMAsKGndQ DMuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EkdGaMAWsiITjixL8vtqkk4znvOu3Q/xzFs2YIEcfEY=; b=TWcJfIEjnTm1wFdJjkogXPeGJG2Z2oblhy9TrakDfYAakr1uGgrN9amdPx6w53nlgG hqKL5DNYWcnyPH5TesGE+q6si8CcAMJSpsrzwUWKgcdDd4ftpk02nI+kDdDulHBGE841 agwOJYsDglxr7IIPgJhPMZxeoc8wgYE8ufzvJbZ9bxVpu++Nn6m8RZCCU8juGBGIF/EP WkreUZ+KqamGOKrfHgCbJz/lvw/5ercnNgYeZVK+LdY4JWASPgmcdBI0n3kEwoFHD9CS M4Gvx/jgkQk7tlX+PInjMsF2u5W5GCjPUb8wqdrTrKRT9kbPoIzXv3+efRSp6/0Zeeag R29Q== X-Gm-Message-State: AOAM5310bMOSC/URL7HWhS914v4qd004b+suuqANyGY+XgzHOH+cgPIk UxdCXoHBeampdaVLEfanOGcZvw== X-Received: by 2002:a2e:a587:: with SMTP id m7mr8896222ljp.133.1600274227566; Wed, 16 Sep 2020 09:37:07 -0700 (PDT) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id o15sm4684400lfo.188.2020.09.16.09.37.06 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Sep 2020 09:37:07 -0700 (PDT) From: Grzegorz Jaszczyk To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, david@lechnology.com, praneeth@ti.com Subject: [PATCH v7 4/5] irqchip/irq-pruss-intc: Implement irq_{get, set}_irqchip_state ops Date: Wed, 16 Sep 2020 18:36:37 +0200 Message-Id: <1600274198-30470-2-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600274198-30470-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1600274198-30470-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: David Lechner This implements the irq_get_irqchip_state and irq_set_irqchip_state callbacks for the TI PRUSS INTC driver. The set callback can be used by drivers to "kick" a PRU by injecting a PRU system event. Co-developed-by: Suman Anna Signed-off-by: Suman Anna Signed-off-by: David Lechner Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Lee Jones --- v6->v7: - Add Co-developed-by tags. v5->v6: - Drop example from the commit log v4->v5: - No change. v3->v4: - Update commit message v2->v3: - Get rid of unnecessary pruss_intc_check_write() and use pruss_intc_write_reg directly. v1->v2: - https://patchwork.kernel.org/patch/11069769/ --- drivers/irqchip/irq-pruss-intc.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) -- 2.7.4 diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index e7ba358..bfe529a 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -12,6 +12,7 @@ * Copyright (C) 2019 David Lechner */ +#include #include #include #include @@ -323,6 +324,43 @@ static void pruss_intc_irq_relres(struct irq_data *data) module_put(THIS_MODULE); } +static int pruss_intc_irq_get_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, + bool *state) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + u32 reg, mask, srsr; + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + reg = PRU_INTC_SRSR(data->hwirq / 32); + mask = BIT(data->hwirq % 32); + + srsr = pruss_intc_read_reg(intc, reg); + + *state = !!(srsr & mask); + + return 0; +} + +static int pruss_intc_irq_set_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, + bool state) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (state) + pruss_intc_write_reg(intc, PRU_INTC_SISR, data->hwirq); + else + pruss_intc_write_reg(intc, PRU_INTC_SICR, data->hwirq); + + return 0; +} + static struct irq_chip pruss_irqchip = { .name = "pruss-intc", .irq_ack = pruss_intc_irq_ack, @@ -330,6 +368,8 @@ static struct irq_chip pruss_irqchip = { .irq_unmask = pruss_intc_irq_unmask, .irq_request_resources = pruss_intc_irq_reqres, .irq_release_resources = pruss_intc_irq_relres, + .irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state, + .irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state, }; static int pruss_intc_validate_mapping(struct pruss_intc *intc, int event, From patchwork Wed Sep 16 16:36:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Jaszczyk X-Patchwork-Id: 312563 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp651504ilg; Wed, 16 Sep 2020 10:10:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAB2nQLpf5yi3/KUkOLMCXsXICFDarSNQL3U8k/sT3n6dDLj/nsXGOKOSYNryxGDI5rzvf X-Received: by 2002:a17:906:2786:: with SMTP id j6mr26144893ejc.73.1600276224076; Wed, 16 Sep 2020 10:10:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600276224; cv=none; d=google.com; s=arc-20160816; b=pFjdTwS71LXY1ApdIel1XEzuIiUDupxCPcKVJ5HctWfhX714zLpFixcG+xqKXOBUbe avAxTkwmFrbM8u0cdIMsF/HLIPCkgr7Xeyzp5Z+QhJelBg/vUSe8yQpWNdBxaXrWHLsp 1Cg+KOp+L2gJPwaL9dv7y5sFfVdE8hyrvddTEtO+WjwGea9VByJs/DvoeyO543fWDgBc zIpXbpdfkSE2yBh6DkjjNT36PKuLxGzhMoufLFqBqo71uOeFhHTopxkHV+jNlgdc1dRt 4CmDGHZyGOocjPsqjI4FX8KoW2s83VeOk9M09k7Q4cSc43trQ3Lgu8+OiHh0cqPtZm0R fZaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=i7gj/Nh8EGIMLYny0ckHHCC3KzEEY3dk78DyFkalFas=; b=WlHC5iKTS356xlLadRqy9STRyPPysmrdOEtm/MTjGN7+7t+XsqstughZvEHiZLGgFn Vb7X0Yb3CE6l3yonzqkFdLQ/dcpqXJ/OVrW+t0R7VxwWvt5N7x2SStAhjxOYGjOEZFYM QhJW4g/4PeXRz7FbzP5Z8ypYuHV1S2QA38yfdXIVKkJspT64YG9PPluRL0Un9IKDBzw1 MLZPNN/r8UUgN8ZJpHwiAhJHRRCXLbfRdHeSunWRwEkNiFdNGxtoAc53CgPXmrrZ4Uoa d0ledZl14ecsISBKeCS/58j7qyc+6a5S5XyzorlKgDILAJvdel64JPd/TOg+9Hp3Ty8I mayQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OXV2czXH; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ca20si12864501edb.445.2020.09.16.10.10.23; Wed, 16 Sep 2020 10:10:24 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OXV2czXH; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726873AbgIPRKN (ORCPT + 6 others); Wed, 16 Sep 2020 13:10:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726854AbgIPRJW (ORCPT ); Wed, 16 Sep 2020 13:09:22 -0400 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD189C02C2B9 for ; Wed, 16 Sep 2020 09:37:12 -0700 (PDT) Received: by mail-lf1-x141.google.com with SMTP id q8so7684880lfb.6 for ; Wed, 16 Sep 2020 09:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=i7gj/Nh8EGIMLYny0ckHHCC3KzEEY3dk78DyFkalFas=; b=OXV2czXHSzNB9gK5puIx4OtBccuHuoEEXxTJymesg/maaUyhIbM4Fp67x5jajv9xHZ ky++sC7oCo8Ln/6QkYF+T28lpqc7eFfJRuv8wx2mYDF3PEVoQ2Rsrm6ZMKrwIWHNnOKo y3+OacNOhef2bvFe61dQWjg53Z9MfRuAMNqzRbdiSvDYlatalaUsUiB2m8nY9t+xgD04 /VoWYu3MjSidCsvpVLuLd/QNmEYcv2RvrMLyYeG5Jk+ja7oG4nq7fpF3Em4kz06wuQa0 Q2L8pevz8GXJ+FoYBjJsxwTLumKGa1yZ7gV/3RI2zxdc00Mo6Hc4+ui1U03TQP6YmkVk C+QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=i7gj/Nh8EGIMLYny0ckHHCC3KzEEY3dk78DyFkalFas=; b=NdeIC6Gs5il6GVcWfoqV2uG1jovnli+I8x/ot0NplU5Zzs+iFpIeYZHpkOW8d62h8r IWLBcjBu+PPfEOCsBXKVmY7n0QU0Ha0lZvrPgTuLj8QQEirBOKD+sqqcoAaF2Vy+QTNn /hVIn1Do7pT7SHN1RUJndHN0Ie0YHFIsnIZzD0PTnH+UAa0Tadbo86T16bTDpkcwZywu AKvlXrHySjJT55FBhZxmZbmNTk3vZaIlxSWe6a6iMSJ9+ZlOsSp2Zio3cPqEEktyVfLM O0CFPBQhEIoK7FqnILMgLoO6TSY9VLhAoB4vGToS/6PxinU7gU2JmcpNL8keIYmMnhLX lhWg== X-Gm-Message-State: AOAM533NPLr+Ia6pq5kDQK8eFbjfyr3dCMylPgXKY7omYpXdLBGT4SUt kqzci+AOyU8o7vHvK/A41rgI2orPMpSfPQ== X-Received: by 2002:a19:8142:: with SMTP id c63mr7926347lfd.175.1600274231059; Wed, 16 Sep 2020 09:37:11 -0700 (PDT) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id o15sm4684400lfo.188.2020.09.16.09.37.10 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Sep 2020 09:37:10 -0700 (PDT) From: Grzegorz Jaszczyk To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, david@lechnology.com, praneeth@ti.com Subject: [PATCH v7 5/5] irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs Date: Wed, 16 Sep 2020 18:36:38 +0200 Message-Id: <1600274198-30470-3-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600274198-30470-1-git-send-email-grzegorz.jaszczyk@linaro.org> References: <1600274198-30470-1-git-send-email-grzegorz.jaszczyk@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The PRUSS INTC present within the ICSSG supports more System Events (160 vs 64), more Interrupt Channels and Host Interrupts (20 vs 10) compared to the previous generation PRUSS INTC instances. The first 2 and the last 10 of these host interrupt lines are used by the PRU and other auxiliary cores and sub-modules within the ICSSG, with 8 host interrupts connected to MPU. The host interrupts 5, 6, 7 are also connected to the other ICSSG instances within the SoC and can be partitioned as per system integration through the board dts files. Enhance the PRUSS INTC driver to add support for this ICSSG INTC instance. Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk --- v6->v7: - Add Co-developed-by tag. v5->v6: - No change. v4->v5: - Rename: s/num_host_intrs/num_host_events/ regarding to change introduced in patch #2. v3->v4: - Move generic part to "irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts" patch and leave only platform related code. v2->v3: - Change patch order: use it directly after "irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops" and before new "irqchip/irq-pruss-intc: Add event mapping support" in order to reduce diff. v1->v2: - https://patchwork.kernel.org/patch/11069773/ --- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-pruss-intc.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 733e59f..25c8944 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -495,7 +495,7 @@ config TI_SCI_INTA_IRQCHIP config TI_PRUSS_INTC tristate "TI PRU-ICSS Interrupt Controller" - depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE + depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 select IRQ_DOMAIN help This enables support for the PRU-ICSS Local Interrupt Controller diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index bfe529a..92fb578 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -628,11 +628,20 @@ static const struct pruss_intc_match_data pruss_intc_data = { .num_host_events = 10, }; +static const struct pruss_intc_match_data icssg_intc_data = { + .num_system_events = 160, + .num_host_events = 20, +}; + static const struct of_device_id pruss_intc_of_match[] = { { .compatible = "ti,pruss-intc", .data = &pruss_intc_data, }, + { + .compatible = "ti,icssg-intc", + .data = &icssg_intc_data, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, pruss_intc_of_match);