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[81.169.180.215]) by mx.google.com with ESMTP id 34si133252edy.347.2017.12.20.07.33.10; Wed, 20 Dec 2017 07:33:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=P7eFfX2t; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 2DA34C2201D; Wed, 20 Dec 2017 15:31:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8C511C21F35; Wed, 20 Dec 2017 15:30:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AF48EC21F35; Wed, 20 Dec 2017 15:30:33 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 33BC9C22119 for ; Wed, 20 Dec 2017 15:30:29 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBKFURT5026341; Wed, 20 Dec 2017 09:30:27 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513783827; bh=AcAFRplinuCCSq8UHw+6jrjXfApu6TYc71CA4+2TKS4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=P7eFfX2tOfOowkYhrlekkuQRE92mzcFySLCop5osaKy6DjnG+zuvgMgpoYLC9JIxj qh26H0b7s/5j1xyTFN7D6K4kSpJx4qIpCWVmvmLqpng3bOY/z6yn915fyc1TkfF5VR gllmxPqftdsS9NVDfNduAHCuMTuaCwhmbgnL8X5I= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBKFURbW023450; Wed, 20 Dec 2017 09:30:27 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Wed, 20 Dec 2017 09:30:27 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Wed, 20 Dec 2017 09:30:27 -0600 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBKFUFCc026407; Wed, 20 Dec 2017 09:30:25 -0600 From: Lokesh Vutla To: Tom Rini , Date: Wed, 20 Dec 2017 20:59:40 +0530 Message-ID: <20171220152940.27950-6-lokeshvutla@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171220152940.27950-1-lokeshvutla@ti.com> References: <20171220152940.27950-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH v2 5/5] board: ti: dra76: mux wakeup2 as gpio1_2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tomi Valkeinen gpio1_2 is used for HPD interrupt with DRA76's DVI add-on board, so mux the pin as gpio and PIN_INPUT. Signed-off-by: Tomi Valkeinen --- board/ti/dra7xx/mux_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 3c3a19a0e1..b5dcaa584a 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -882,7 +882,7 @@ const struct pad_conf_entry dra76x_core_padconf_array[] = { {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */ {WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */ {WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */ - {WAKEUP2, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq2 */ + {WAKEUP2, (M14 | PIN_INPUT)}, /* N/A.gpio1_2 */ {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */ };