From patchwork Thu Oct 29 13:40:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 319590 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp485875ilc; Thu, 29 Oct 2020 06:48:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAQm7pRC99/OerThJpxtYN2M/+OYMbPoSXOIGFhMaekL0B/MXALFB++e2Hp+AuY/ex0Vqk X-Received: by 2002:a17:906:1c50:: with SMTP id l16mr4101462ejg.144.1603979285842; Thu, 29 Oct 2020 06:48:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1603979285; cv=none; d=google.com; s=arc-20160816; b=yCSxwTtyYFQh0GCw1w7mVsWswNezkBPk+49Y2ubrdKn6QxeX+nOKYHTgpnZq7Fv/uD kPOjHVX2knp7HzJZZueXmWlrDQXsum2zKFRTqUaGCEadbHUhcCYfmHgdAD1sP+NtlErH s5G0LcGOytt+N6nDyC3GoIsBbVZiGT6SDYLwLMkZP1XPQA4k/E7EqXGY/3AWtxf+wtX2 n/7cv4nLVoEMIgBVJxBtPkBJfEEYw5pcIF5yEyI9tWX47IXZkOkWtH64BJEHGNdSSjGp B7LoiFRkNIVfREV6J0FkjDFJ/pXt7ww6xi7KeKu3MEZGDv1RjJn7/opXFu9PRMdai5Sn msAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:cms-type:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter; bh=Xy+FsHgST2UjrlJrA5Urtuej2IuCVrFsZHKkLfZioK8=; b=W1Y42/4GyHBjCIIf+hsiJhBR31yiZiLBcda6dtrwNLRMnPV+SPs7bJoMNw7SeENGAI k8LAptJ0SWG5VGQWmB5+jI4tSeE54m7Gz0mkl0haNtWiUs6c3TuSRiOjvpxSHgnYyTIM ScfhrbdraGs1WLVZ1U3jSpLGQ7/86C8TZ1EAgrGQgHmo+cIwVS4KT3CnIcLbi7br/rwQ ZCTtMaQksw2F7c36kzph1Y5anG0FxnmKe6YGzVAT7AcZpurP5YPHm9sQ5Sp5rUUmkRQb QId0SaxDOug8PMcbh6b5k/ANiuuMwqjaSkyDaDclNr7giKa/q3pI/AbmxDTjNc+scfV6 WLGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@samsung.com header.s=mail20170921 header.b=ZLvAwyXq; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k25si2042949ejk.10.2020.10.29.06.48.05; Thu, 29 Oct 2020 06:48:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@samsung.com header.s=mail20170921 header.b=ZLvAwyXq; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=samsung.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727674AbgJ2NsF (ORCPT + 4 others); Thu, 29 Oct 2020 09:48:05 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:39907 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727247AbgJ2NsE (ORCPT ); Thu, 29 Oct 2020 09:48:04 -0400 Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20201029134041euoutp029abaf708db8326dcfda82309e5eb6e4a~CekIGi0Zx1310413104euoutp02h for ; Thu, 29 Oct 2020 13:40:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20201029134041euoutp029abaf708db8326dcfda82309e5eb6e4a~CekIGi0Zx1310413104euoutp02h DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1603978841; bh=Xy+FsHgST2UjrlJrA5Urtuej2IuCVrFsZHKkLfZioK8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZLvAwyXq1eYqGKcForsVWfNOTskEBdDflqatjvlaZixfoUGNnCjGBaBllsVmcLDug BkBjgzC3bqeMab0RTNnyloNQZTda2SkOyBV2wKRz98mLnhyYB5gf+8jJsXiyWDMmuQ S5uDceHXb4r1pWccSJoQrkzPg2bnvulTYkpLdinU= Received: from eusmges2new.samsung.com (unknown [203.254.199.244]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20201029134038eucas1p2ed790bc82b33747988e71958b91d9612~CekFMEnem0279102791eucas1p2o; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges2new.samsung.com (EUCPMTA) with SMTP id 09.99.05997.656CA9F5; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) Received: from eusmtrp1.samsung.com (unknown [182.198.249.138]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20201029134037eucas1p275bad9fe08eff145711cc36ac8c685f7~CekE1Iu9o1017310173eucas1p2Y; Thu, 29 Oct 2020 13:40:37 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20201029134037eusmtrp13766ec9d9c582572612133ce74632ea8~CekE0W6SR1072610726eusmtrp1G; Thu, 29 Oct 2020 13:40:37 +0000 (GMT) X-AuditID: cbfec7f4-677ff7000000176d-36-5f9ac65692dd Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 8B.91.06017.556CA9F5; Thu, 29 Oct 2020 13:40:37 +0000 (GMT) Received: from AMDC2765.digital.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20201029134037eusmtip1fe195cc094475eafe10889cb8b339f80~CekENPGdX1812718127eusmtip1t; Thu, 29 Oct 2020 13:40:37 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH v3 1/6] dt-bindings: pci: drop samsung,exynos5440-pcie binding Date: Thu, 29 Oct 2020 14:40:12 +0100 Message-Id: <20201029134017.27400-2-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201029134017.27400-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTYRjG+Xa2nePwxGkqfsxKGGQW5KUiDnjBImp/WEh28YKXUx5U2qZt zkt/eJliOkSaBuoaU7uomJou8bI0cslW2dxQqZFTihJMHVhqqZnlPGn/Pc/z/l6ej5cPQ/g6 jgBLl2bRMiklFnJ57B7TmvXoFZMmKWjhNZt8qEwj64dHOaR9vZRDtizXoaRtpoJLWq2dKDlu 0HJJi87MJWutz1nkwq9ZlGwfnkLJPwN9KNnveIVE4KI2XRsQ9WumUFGDXiHSt5ZzRZXdrUBk tveyREv6A1FoHC80hRanZ9OywPBkXtqj3i6Q2eiVW1MyDwqBfa8KuGGQOAHrTGagAjyMT7QA +HT5LcqYZQCn3zSxGLME4O1KFXdn5dmGnsMMmgF8/8HO3V2Zu6dluyguEQxVTtcGhnkSEXB1 hXQxCFGPQPX0JMvFeBBRsHjl2zbDJg7Ciapcl8SJMPhx7SrT5Qsfd75AXLEbEQ5NSiETt6Lw nfoCo8/A/s/9LEZ7wDlzN8rofXCkuoLtaoVEMYCfRttRxlQAOK6sBQwVAh2j69tPQIjD8Ikh kIlPQVunYzuGxB5od25fC9mSVT01CBPjsKyUz9B+UGPu2K0dso39Q0TwblMkcxs1gCOr88gd 4Kv539UAQCvwphVySSotPyalcwLklESukKYGXM+Q6MHWrxnZNC/3AcPGNSMgMCB0x22TdUl8 DpUtz5MYAcQQoSd+2jKSyMdTqLxbtCwjSaYQ03Ij8MHYQm/8+P2vCXwilcqib9B0Ji3bmbIw N0EhQOvFuHagpOiH5KZOrYzdLA9VW/KN+2OS02YiJ0yLftGbXrb46OpBf/+ZnyeNjrPC2eaL ho6XEZW1Y3rp6vkeVrygYA4/NxUfsnio4/KlxAfq3u+LzkkkP8xSrSqSumeW5fTFNySgsblx MRpn0BfB4G8fqss4M7yADGmpxgIhW55GBR9BZHLqL+BLzy0xAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42I5/e/4Xd3QY7PiDf5u07ZY0pRhMf/IOVaL G7/aWC1WfJnJbnHhaQ+bxfnzG9gtLu+aw2Zxdt5xNosZ5/cxWbz5/YLdYu2Ru+wW//fsYLfY eecEswOvx5p5axg9ds66y+6xYFOpx6ZVnWwefVtWMXocv7GdyePzJrkA9ig9m6L80pJUhYz8 4hJbpWhDCyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TUnMyy1CJ9uwS9jKXbNzIWLBStmN7ymrGB 8YZgFyMnh4SAicTuP5tYuxi5OIQEljJK9O24yQqRkJE4Oa0ByhaW+HOtiw2i6BOjxPzDJxhB EmwChhJdb0ESnBwiAk4S7ydfZAaxmQVWMksc3JYHYgsL+Em8WvWNpYuRg4NFQFXiyqQKEJNX wFbiwc9wiPHyEqs3HGAGCXMK2Ekca1ICCQsBVew79Yp5AiPfAkaGVYwiqaXFuem5xUZ6xYm5 xaV56XrJ+bmbGIGhv+3Yzy07GLveBR9iFOBgVOLhvXB7ZrwQa2JZcWXuIUYJDmYlEV6ns6fj hHhTEiurUovy44tKc1KLDzGaAl00kVlKNDkfGJd5JfGGpobmFpaG5sbmxmYWSuK8HQIHY4QE 0hNLUrNTUwtSi2D6mDg4pRoY+x19bSQVNswP/xXdOvd+rdrM58udjWLWnzp+yDo/vV1ZpmPh OgWZzb/OMBZcfab86ryIMPfKja1dqiYT+w9xFYvJveFt7PW7GqtmIxE6yfR+WU9J4bNrTeq9 5+UElq4pfT7FZqb7mRMOnWt5p7T9in0vOptt/bwJprttjyc/ixXmLFzvMSFDiaU4I9FQi7mo OBEAqUh1gJMCAAA= X-CMS-MailID: 20201029134037eucas1p275bad9fe08eff145711cc36ac8c685f7 X-Msg-Generator: CA X-RootMTR: 20201029134037eucas1p275bad9fe08eff145711cc36ac8c685f7 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201029134037eucas1p275bad9fe08eff145711cc36ac8c685f7 References: <20201029134017.27400-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM: dts: exynos: Remove Exynos5440"). Drop the obsolete bindings for exynos5440-pcie. Signed-off-by: Marek Szyprowski Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Reviewed-by: Jingoo Han --- .../bindings/pci/samsung,exynos5440-pcie.txt | 58 ------------------- 1 file changed, 58 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt deleted file mode 100644 index 651d957d1051..000000000000 --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Samsung Exynos 5440 PCIe interface - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. - -Required properties: -- compatible: "samsung,exynos5440-pcie" -- reg: base addresses and lengths of the PCIe controller, -- reg-names : First name should be set to "elbi". - And use the "config" instead of getting the configuration address space - from "ranges". - NOTE: When using the "config" property, reg-names must be set. -- interrupts: A list of interrupt outputs for level interrupt, - pulse interrupt, special interrupt. -- phys: From PHY binding. Phandle for the generic PHY. - Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt - -For other common properties, refer to - Documentation/devicetree/bindings/pci/designware-pcie.txt - -Example: - -SoC-specific DT Entry (with using PHY framework): - - pcie_phy0: pcie-phy@270000 { - ... - reg = <0x270000 0x1000>, <0x271000 0x40>; - reg-names = "phy", "block"; - ... - }; - - pcie@290000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x290000 0x1000>, <0x40000000 0x1000>; - reg-names = "elbi", "config"; - clocks = <&clock 28>, <&clock 27>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - phys = <&pcie_phy0>; - ranges = <0x81000000 0 0 0x60001000 0 0x00010000 - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - num-lanes = <4>; - }; - -Board-specific DT Entry: - - pcie@290000 { - reset-gpio = <&pin_ctrl 5 0>; - }; - - pcie@2a0000 { - reset-gpio = <&pin_ctrl 22 0>; - }; From patchwork Thu Oct 29 13:40:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 311048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A649C2D0A3 for ; Thu, 29 Oct 2020 13:42:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 220F1206E9 for ; Thu, 29 Oct 2020 13:42:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="AtJM75Wv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727526AbgJ2Nme (ORCPT ); Thu, 29 Oct 2020 09:42:34 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:39490 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727345AbgJ2Nme (ORCPT ); Thu, 29 Oct 2020 09:42:34 -0400 Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20201029134049euoutp0149b5dee11b2f50b83c48e5e6c66e7d3f~CekPeX_NZ0675306753euoutp01i for ; Thu, 29 Oct 2020 13:40:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20201029134049euoutp0149b5dee11b2f50b83c48e5e6c66e7d3f~CekPeX_NZ0675306753euoutp01i DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1603978849; bh=TW2zV34il+4ssikQflYGXlUkM7Maf+DpRyVZ9mOsGDE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AtJM75WvonyDC5eZ1EggLTuOKm7EzoCBSW2X9wzqSW0dGSxQLnnssgngiH5VLTThR SaR84NxLqRSSitd94OJ+gRbcyI7pQs/aWcuihJK0MK4jEoYS4ob1hjQF8XZ8tJ/ieN V4Wy62o7jfWSM4lhG8jAKcGAYVYbJ1c3DwQ5jSbs= Received: from eusmges1new.samsung.com (unknown [203.254.199.242]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20201029134038eucas1p11288c6202ab7061cdc7f18420f7bc450~CekF5gFNs0836708367eucas1p1h; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges1new.samsung.com (EUCPMTA) with SMTP id 3E.D1.06456.656CA9F5; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20201029134038eucas1p28d9bd33bc9e36b960b021a40ef299b47~CekFUx-EN0341003410eucas1p25; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20201029134038eusmtrp2dbfe6b3133008dc4801b9b7fe1c2e2d7~CekFUCXGb0454004540eusmtrp2Y; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) X-AuditID: cbfec7f2-7efff70000001938-2c-5f9ac6566949 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 8C.91.06017.656CA9F5; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) Received: from AMDC2765.digital.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20201029134037eusmtip1898222eae6be92848e98563a1d0ab958~CekEvleht2175221752eusmtip18; Thu, 29 Oct 2020 13:40:37 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH v3 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding Date: Thu, 29 Oct 2020 14:40:13 +0100 Message-Id: <20201029134017.27400-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201029134017.27400-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIKsWRmVeSWpSXmKPExsWy7djP87phx2bFG5xrMLVY0pRhMf/IOVaL G7/aWC1WfJnJbnHhaQ+bxfnzG9gtLu+aw2Zxdt5xNosZ5/cxWbz5/YLdYu2Ru+wW//fsYLfY eecEswOvx5p5axg9ds66y+6xYFOpx6ZVnWwefVtWMXocv7GdyePzJrkA9igum5TUnMyy1CJ9 uwSujHU/N7EU3JWrOPzkIVMD43bxLkYODgkBE4nnN9K6GLk4hARWMEosvL2FGcL5wiixs+0k lPOZUeJk8zLGLkZOsI4X9/4wQSSWM0q0zf6B0LLy9U8WkCo2AUOJrrddbCA7RAQcJH58tQCp YRaYzywx8d5tJpAaYQF/if+vT4DVswioShze0Qi2gVfAVuL4++NsENvkJVZvOMAMModTwE7i WJMSyBwJgWXsEgtvHoG6yEXi9aw+JghbWOLV8S3sELaMxP+d85kgGpoZJR6eW8sO4fQwSlxu mgHVbS1x59wvsEuZBTQl1u/Shwg7SsxYsZ8JEkh8EjfeCoKEmYHMSdumM0OEeSU62oQgqtUk Zh1fB7f24IVLzBC2h0TvJZAzQeEzkVHi19IbLBMY5WchLFvAyLiKUTy1tDg3PbXYMC+1XK84 Mbe4NC9dLzk/dxMjMOGc/nf80w7Gr5eSDjEKcDAq8fBeuD0zXog1say4MvcQowQHs5IIr9PZ 03FCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeY0XvYwVEkhPLEnNTk0tSC2CyTJxcEo1MHZ/vvLx bi+7U5HHTXa9oxeEjh3QXlrfu7Lmn+k8nt/iq/ZwBsgKL5lpX7uvpYPnQ2yfvsnPINvWj6s2 TTBpKwmL+essXOa9dsK3RecUp99Tcr1+UURU3bS2tmS5jrBMsm35n6vqrTuU//3nSJO8GmQ8 R9tsy0KljSof709deeRvs7WQ3sGnLUosxRmJhlrMRcWJAMcqWog0AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpikeLIzCtJLcpLzFFi42I5/e/4Xd2wY7PiDd4f4rNY0pRhMf/IOVaL G7/aWC1WfJnJbnHhaQ+bxfnzG9gtLu+aw2Zxdt5xNosZ5/cxWbz5/YLdYu2Ru+wW//fsYLfY eecEswOvx5p5axg9ds66y+6xYFOpx6ZVnWwefVtWMXocv7GdyePzJrkA9ig9m6L80pJUhYz8 4hJbpWhDCyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TUnMyy1CJ9uwS9jHU/N7EU3JWrOPzkIVMD 43bxLkZODgkBE4kX9/4wdTFycQgJLGWUWHP+AhtEQkbi5LQGVghbWOLPtS42iKJPjBL3O96B FbEJGEp0ve0Cs0UEnCTeT77IDGIzC6xklji4LQ/EFhbwlVg5cx5YDYuAqsThHY2MIDavgK3E 8ffHoZbJS6zecACol4ODU8BO4liTEkhYCKhk36lXzBMY+RYwMqxiFEktLc5Nzy020itOzC0u zUvXS87P3cQIDP9tx35u2cHY9S74EKMAB6MSD++F2zPjhVgTy4orcw8xSnAwK4nwOp09HSfE m5JYWZValB9fVJqTWnyI0RToponMUqLJ+cDYzCuJNzQ1NLewNDQ3Njc2s1AS5+0QOBgjJJCe WJKanZpakFoE08fEwSnVwKidKGla+/PvP76WPz2Z5ZxZljZcU06c7lN1zC+/9KYrcN0251yF 2kK9I0KhoSafbyTwn0q6tj+ifQer6eESnU1OBn2WYkeKFqW/eTiXRVvI4lean/RN7WNVzos1 rz86WFA54eW3zY1vDP/Nbv+5u0/52CcL1uvB915cNnLl+/wuhWFbTsiCOUosxRmJhlrMRcWJ AEGWV86VAgAA X-CMS-MailID: 20201029134038eucas1p28d9bd33bc9e36b960b021a40ef299b47 X-Msg-Generator: CA X-RootMTR: 20201029134038eucas1p28d9bd33bc9e36b960b021a40ef299b47 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201029134038eucas1p28d9bd33bc9e36b960b021a40ef299b47 References: <20201029134017.27400-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433 variant). Based on the text dt-binding posted by Jaehoon Chung. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../bindings/pci/samsung,exynos-pcie.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml new file mode 100644 index 000000000000..1810bf722350 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe Host Controller Device Tree Bindings + +maintainers: + - Marek Szyprowski + - Jaehoon Chung + +description: |+ + Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + designware-pcie.txt. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: samsung,exynos5433-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: External Local Bus interface (ELBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: elbi + - const: config + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PCIe bridge clock + - description: PCIe bus clock + + clock-names: + items: + - const: pcie + - const: pcie_bus + + phys: + maxItems: 1 + + vdd10-supply: + description: + Phandle to a regulator that provides 1.0V power to the PCIe block. + + vdd18-supply: + description: + Phandle to a regulator that provides 1.8V power to the PCIe block. + + num-lanes: + const: 1 + + num-viewport: + const: 3 + +required: + - reg + - reg-names + - interrupts + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + - ranges + - bus-range + - device_type + - num-lanes + - num-viewport + - clocks + - clock-names + - phys + - vdd10-supply + - vdd18-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pcie: pcie@15700000 { + compatible = "samsung,exynos5433-pcie"; + reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = ; + clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; + clock-names = "pcie", "pcie_bus"; + phys = <&pcie_phy>; + pinctrl-0 = <&pcie_bus &pcie_wlanen>; + pinctrl-names = "default"; + num-lanes = <1>; + num-viewport = <3>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + vdd10-supply = <&ldo6_reg>; + vdd18-supply = <&ldo7_reg>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + }; +... From patchwork Thu Oct 29 13:40:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 319583 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp481805ilc; Thu, 29 Oct 2020 06:43:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxL10UCRs4cYZde0RlijYQhSWmXmKuWx1XDj6ZeXGd02z7EOHIwaKGYJX8WZ3/v8tJ3ARxF X-Received: by 2002:a17:906:138a:: with SMTP id f10mr4260021ejc.360.1603978991268; Thu, 29 Oct 2020 06:43:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1603978991; cv=none; d=google.com; s=arc-20160816; b=vvKBtdFxbAoeGKcwRpe/r8Yx0ckO02RtADUcl2dCI8EcU3wSDN+eM17xcARSKh3fyN 1YE+ATu93FxVG5+Yjh4ELPWtPbJDAhuMGpexwVnDRHfja/ppyRT4I8sk5hVtVJ0IjOSf xzaKz6yLIUYdayUgv19HVE2+/aqfgqAq7oENdeJZ9coYPQ+NIUXbQVz4hN+V5HOomxj3 dGZsr3Ik55kQYDa22+gckejoju1kl3nODqjQUuU5m1wakcIQdYi6B1/KOauDjTPhOdhf 53EWhMj2mzRwnr/+YidtycM+kPaG0tHNfFNDNI/ce+9ibelQb+uJ5mawbtRu0IdaYOkL 0n1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:cms-type:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter; bh=5LWk+rJhbViO9l0AuP2OfsCbsmcQL6wtHWsnyEYFN8U=; b=YdXiH5VFrrISjGx5wHHnm2CHEYyJUv5J9BjzOZ9URkYhPAuFCSrD8I8FhMOwfJ4mls W4rbjRzrPABaf8dqU1+qXCyJEYSViqdzZBFCDlItEnZCrGRMTONlqrMKzUkcVzZX2az7 OV6w0lvrB3uYaN72/vj2i/slp404dX7jmzEZoeVpUb6rcZryrsiNAs1ULbJQbX5P0LHD cUOPF4G5n15c4b3dRJNSKv8G0qYhsrfLnVYcEEy1U2KfTSunaKxL/ML85OU//vliv+9B vLTz7ClJ9vljJXFE3NZo+egVRhbsVuHvjHdUU/82FBY1xXxPrYy2KkMJLGOrjKwnKzRo U2Gg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@samsung.com header.s=mail20170921 header.b=NUoA1PaI; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c24si2102707edy.580.2020.10.29.06.43.11; Thu, 29 Oct 2020 06:43:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@samsung.com header.s=mail20170921 header.b=NUoA1PaI; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=samsung.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726292AbgJ2NnK (ORCPT + 4 others); Thu, 29 Oct 2020 09:43:10 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:38055 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727081AbgJ2Nmd (ORCPT ); Thu, 29 Oct 2020 09:42:33 -0400 Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20201029134041euoutp02a8002ffaa2db6229da922a536fe66334~CekIWzwfo1310413104euoutp02k for ; Thu, 29 Oct 2020 13:40:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20201029134041euoutp02a8002ffaa2db6229da922a536fe66334~CekIWzwfo1310413104euoutp02k DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1603978841; bh=5LWk+rJhbViO9l0AuP2OfsCbsmcQL6wtHWsnyEYFN8U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NUoA1PaIgM8ut7ybKGlQ6OnAXZUIheMtBRQyapnXPk0WokZybHxAcnOzsyForiAS2 TEB9Xjt7Q/sjq9VcnaSHKC23RpGAIHcjk3Qx+Rj+os1yUSBd/FJ4lf/ofH2o3JwPCk hSolcEXegF7VSYoeCAkVEocKC5tHyJBk4oH5fMwk= Received: from eusmges1new.samsung.com (unknown [203.254.199.242]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20201029134039eucas1p1a717cfe00759ba1c2cf67d17f9feb5a7~CekGRenc83127831278eucas1p1G; Thu, 29 Oct 2020 13:40:39 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges1new.samsung.com (EUCPMTA) with SMTP id 3F.D1.06456.756CA9F5; Thu, 29 Oct 2020 13:40:39 +0000 (GMT) Received: from eusmtrp1.samsung.com (unknown [182.198.249.138]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20201029134038eucas1p2d550a45ff3222ccb72d15d5c89d4f938~CekF4bxxM0841008410eucas1p2Y; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20201029134038eusmtrp1a3d9d615288a64e6127794c76b238423~CekF3gOA51072510725eusmtrp1e; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) X-AuditID: cbfec7f2-7efff70000001938-2e-5f9ac6572a19 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 7B.90.06314.656CA9F5; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) Received: from AMDC2765.digital.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20201029134038eusmtip15a5b0613dfd3b26193055bc341ac57df~CekFSABis1565515655eusmtip1u; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH v3 3/6] dt-bindings: phy: add the samsung,exynos-pcie-phy binding Date: Thu, 29 Oct 2020 14:40:14 +0100 Message-Id: <20201029134017.27400-4-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201029134017.27400-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSbUhTYRjl9W733kmT1yn4YpKxSChKXYVdysRC4hYUgj+iItfSi442lc1Z SpApaS4TP7B02pyfE5tf8yNnoTXFGeIHWmg4JSHLylk4LVuQeb1q/845z3nec3h4SUxk4PuS 8oRkRpUgU4hxd17nwO/Rw5cGdNLg7CUPqiYjnqroH+FTU64sPlW/UkpQY/O5ODU62kJQE93l ODWst+FUyWiPG7X4Z4GgGvtnCGr9ZRdBWeyDWLiQNulNgLboZgjaYNbQ5oYcnM5rbwC0beq5 G+0074kkrriHxjIKeQqjCgq77h5fPesgkpzwtv2TnpcOPgq1QEAieAxZWnU8LXAnRbAeoHtl NQRHVgBa6i3kc8QJkH3dQGyv1L+o2sQiaAQos+PqzkZB9U8+O8ChBGkdWlwLSNIbhqO1VYr1 YLACQwWz026sxwtGoYd9FTiLeXA/Guzr5bF+ITyFKuelXJY/etbyCmNlAQxDAxli9hkE6wj0 a9yEcZ4I1Fjn2MJe6KutfaunHxoqyuVxC5kAzY00EhzJBWgiowRwrpPIPuLaLIrBA6i5O4iT T6PhGiPBygh6oCmHJytjG7Cw8wnGyUL0IEvEuQOQzta0E/t6bHyrDo16lt9j3HkKADKnN+L5 wF/3P8wAQAPwYTRqZRyjliQwtwLVMqVakxAXGJOoNIONfzP017bcBVbHb1gBJIF4l3BsulQq 4stS1KlKK0AkJvYWnhkeihYJY2WpaYwqUarSKBi1FewmeWIf4dGqL9dEME6WzNxkmCRGtT11 IwW+6aDNc7iptsMQMmesfFcU01RutTqy+9/mTOwtrnWSeeLPi1l6uf3Ij7T5p/vou6sxydXR +ZczSyeDv0fpH9Wdqw23AL8lPFRz3lH8wWVqs1wIbi0LiPhW2mWE99dSL06GKMQpEkP+WV3z Y8EdWefCm4Xj44em8k5EVk1WN7uKyuRinjpeJjmIqdSyf4UEwzQzAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42I5/e/4Xd2wY7PiDZa/NbJY0pRhMf/IOVaL G7/aWC1WfJnJbnHhaQ+bxfnzG9gtLu+aw2Zxdt5xNosZ5/cxWbz5/YLdYu2Ru+wW//fsYLfY eecEswOvx5p5axg9ds66y+6xYFOpx6ZVnWwefVtWMXocv7GdyePzJrkA9ig9m6L80pJUhYz8 4hJbpWhDCyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TUnMyy1CJ9uwS9jMX33rIXfBaouPNsHksD 4xPeLkZODgkBE4kVuxexdzFycQgJLGWUeLvpPytEQkbi5LQGKFtY4s+1LjYQW0jgE6PEu2NC IDabgKFE11uIuIiAk8T7yReZQWxmgZXMEge35YHYwgKBEnM/LGIBsVkEVCVOHN4PZHNw8ArY Six8Gg8xXl5i9YYDzCBhTgE7iWNNShCbbCX2nXrFPIGRbwEjwypGkdTS4tz03GJDveLE3OLS vHS95PzcTYzA0N927OfmHYyXNgYfYhTgYFTi4b1we2a8EGtiWXFl7iFGCQ5mJRFep7On44R4 UxIrq1KL8uOLSnNSiw8xmgKdNJFZSjQ5HxiXeSXxhqaG5haWhubG5sZmFkrivB0CB2OEBNIT S1KzU1MLUotg+pg4OKUaGIv63vgpLeSKvZt+xPau61q5XZE6n+cv22fpd+BV8PGi1VEv/dyv O+k/Mg6+4ZVnkWIjdJKluob/U1V3s+7P7m8q5mnz7vJ/euLw1uWf1qQnTTV7/2/KcHxnEmHd 3f/b8YTOobTKFy9N17LuLZRT8ds15dLWmncMDCbntSJuVN9amPov6eLHKiWW4oxEQy3mouJE AOhvhbeTAgAA X-CMS-MailID: 20201029134038eucas1p2d550a45ff3222ccb72d15d5c89d4f938 X-Msg-Generator: CA X-RootMTR: 20201029134038eucas1p2d550a45ff3222ccb72d15d5c89d4f938 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201029134038eucas1p2d550a45ff3222ccb72d15d5c89d4f938 References: <20201029134017.27400-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433 variant). Based on the text dt-binding posted by Jaehoon Chung. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski --- .../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml new file mode 100644 index 000000000000..ac0af40be52d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe PHY Device Tree Bindings + +maintainers: + - Marek Szyprowski + - Jaehoon Chung + +properties: + "#phy-cells": + const: 0 + + compatible: + const: samsung,exynos5433-pcie-phy + + reg: + maxItems: 1 + + samsung,pmu-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for PMU system controller interface, used to + control PMU registers bits for PCIe PHY + + samsung,fsys-sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for FSYS sysreg interface, used to control + sysreg registers bits for PCIe PHY + +required: + - "#phy-cells" + - compatible + - reg + - samsung,pmu-syscon + - samsung,fsys-sysreg + +additionalProperties: false + +examples: + - | + pcie_phy: pcie-phy@15680000 { + compatible = "samsung,exynos5433-pcie-phy"; + reg = <0x15680000 0x1000>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&syscon_fsys>; + #phy-cells = <0>; + }; +... From patchwork Thu Oct 29 13:40:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 319571 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp481670ilc; Thu, 29 Oct 2020 06:43:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyduFqbsNbkHUsirQ8Vv5qC6rtkb+RBVTDIOGVaO0t6+uE2VRmECAjaefaThFQz5qwJAZoT X-Received: by 2002:a17:906:2a41:: with SMTP id k1mr4018787eje.33.1603978980268; Thu, 29 Oct 2020 06:43:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1603978980; cv=none; d=google.com; s=arc-20160816; b=czswGPhdDcktbWFzZCYHA67I9WkdYHOtj62YNpAlbhWalHH7oVLxBkn2MH/AEjmFTD kmlUaE/489RH8wZkODawJlc/TRx5d1Sp+9+RU42oFtXxSClARoAX6og4lnD6OCeaclDW zetlZNsSi+raoHh60BDGUvC3YiZ1Qa7mkfZw+RlhVw3tIKi2D7QuvpRqwzZ80gmWaLPH ytkYU8gvHeHZR/w0iD2LVzAZy/7BQ+EIt8TdmXfBSxQBqA31TLNA7uMf2ia87oaqGDuS nVC/Elssneud4nLY2pEnt1LQDuFRtZRCRxULQHfuIMZYbvzoakOJ4SaMlZwHJeT/Aa/J N3Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:cms-type:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter; bh=gdjMW45LH1V7a5PoXN2PEBDKCHwl6twq6OwR+g7pkZc=; b=k5KXx9zbf7V3i/VkhcYvUsSKURkUBafNSAz7gjf5lIei0MDjipposeeHoTm5KrdK7U AuJ87UBVByZl9KrQmCAd4NymHKiX7a0WLW7nDmHHBUj6Aue73N93bnsHkQ/aB/9ItNWi icJjOu0I/lJ4jYktbR+AxuKgTuSQEsaFwjomk+H7BWobseVlS02F0RSa6Q5mzceUgOLN JGjcBc5KLixn14OGoS556aS8Yzr9weh1AipLjbzdC70w5JJ3iPAwNt8+1qq2E6FdLADn PWKuJnYb+XDQUvBLkmAJ3S16zeYkjV0fL/3gEyGHeytD6nG67tAeQ00toNRrYmGImLZA gjUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@samsung.com header.s=mail20170921 header.b=Isqg3YK7; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id s16si1863422ejy.687.2020.10.29.06.42.59; Thu, 29 Oct 2020 06:43:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@samsung.com header.s=mail20170921 header.b=Isqg3YK7; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=samsung.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727689AbgJ2Nm7 (ORCPT + 4 others); Thu, 29 Oct 2020 09:42:59 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:38059 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727265AbgJ2Nme (ORCPT ); Thu, 29 Oct 2020 09:42:34 -0400 Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20201029134041euoutp02675cf0b021e676127e7506a0b5610649~CekId2AtP1443114431euoutp02p for ; Thu, 29 Oct 2020 13:40:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20201029134041euoutp02675cf0b021e676127e7506a0b5610649~CekId2AtP1443114431euoutp02p DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1603978841; bh=gdjMW45LH1V7a5PoXN2PEBDKCHwl6twq6OwR+g7pkZc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Isqg3YK7OO+0bnLGEfHT4I7TVFek6ysBnM7yfHV3LdsySgV2uI0GtE+uD1cuvc+c+ P5Jxv7F3zkNlXp/7HXuZnWYE4IzNzUYivHDtzwhkKv2TNU0u+ajTrPJyg1Pzwk05+N 0taAouVnsI6wIRaO502KXYuFbYlq8io1Z0TrHbtU= Received: from eusmges1new.samsung.com (unknown [203.254.199.242]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20201029134039eucas1p193ba2be91d3c7b44caf7d465bd5e68b8~CekG1Qot32525425254eucas1p1q; Thu, 29 Oct 2020 13:40:39 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges1new.samsung.com (EUCPMTA) with SMTP id 10.E1.06456.756CA9F5; Thu, 29 Oct 2020 13:40:39 +0000 (GMT) Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20201029134039eucas1p2270e5f4ecea05b17f4d9107300ce946d~CekGcqZWa0299902999eucas1p25; Thu, 29 Oct 2020 13:40:39 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20201029134039eusmtrp24e228e1d86a374111ad60785286af247~CekGboDBj0454004540eusmtrp2a; Thu, 29 Oct 2020 13:40:39 +0000 (GMT) X-AuditID: cbfec7f2-7efff70000001938-30-5f9ac6575361 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 2E.91.06017.756CA9F5; Thu, 29 Oct 2020 13:40:39 +0000 (GMT) Received: from AMDC2765.digital.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20201029134038eusmtip13903a4f585337a2a966793a800df6400~CekF1XkNG2299722997eusmtip1T; Thu, 29 Oct 2020 13:40:38 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH v3 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Date: Thu, 29 Oct 2020 14:40:15 +0100 Message-Id: <20201029134017.27400-5-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201029134017.27400-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjuO2c75zhcnKbNL4uMgUWCNwr5ohKLfhyEoPpTJKYzj5eaUzdn Wj+UeaGmRXZBXerMTId3h5qz0hJx4mUzDZpX3A9NrUGkIzXKnGfav+d53ud5n5ePj8JFL/ne VKI8jVXIpTIJIeB19K9b/K/2a6OCeoZDULU6Aen6zHxk3cjnI/1qKYlG5wsJZLG0kGi8q4xA IxUmApVYujH0/fciiRr7Zki0+a6TRMbpATxMyDRUNADGqJ0hmUqDijHUPSCYR211gDFZ32DM iuHwJfK64EwsK0tMZxWBodGChDntxZTl9IyFWQeZDXLjNcCNgvRJ+MdWzNcAASWi9QCalyoJ jqwCuLDxwkVWAPyVq8V2IvqcdZIb1AJoUX/j70YqLQ+B00XQwVBj12zFKcqTDoNrDuT04LQO h0WzU9ubPGgWzv9oJZyYR/tC/WQ3z4mF9Fn4drKd5Np8YH3LB9y5x40Ohf1qiXMPpGtIaCst AJznAmx9XoBz2AMum9pc2UNw06jDuEAOgDZzI8mRQgDH1SWu9Gk4bd7YvhSnj8PmrkBOPger C5qBU4b0Xmi173PK+BZ80lGMc7IQ3s8Xce6jUGtq2q39ODrmOoeBX8esrlcsArBe+xp7DHy0 /8sqAagDXqxKmRTPKoPl7J0ApTRJqZLHB9xMTjKArY8z9Nf0sxM4xmJ6AU0BibtwdKo0SsSX piszk3oBpHCJp/D8yNANkTBWmnmXVSRHKVQyVtkLDlI8iZfwRNVSpIiOl6axt1k2hVXsTDHK zTsbECjvHrbnGSnRlfv2N6U+nY5qMNgmGBsWk1r1mefpKB6ukrUZHSjrfVqmX8blrsjouMGK l+Hygf2Sqb6cOI+JGPSl/FjqoDgnz31t9IhdK8sX54VnTdrHxDWvToVHZOV69ZgP+Ccse1z5 5BshLiucCHVvv7UQFIJdS1ucqx2U8JQJ0mA/XKGU/gM24hoiNAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpkkeLIzCtJLcpLzFFi42I5/e/4Xd3wY7PiDebNlbRY0pRhMf/IOVaL G7/aWC1WfJnJbnHhaQ+bxfnzG9gtLu+aw2Zxdt5xNosZ5/cxWbz5/YLdYu2Ru+wW//fsYLfY eecEswOvx5p5axg9ds66y+6xYFOpx6ZVnWwefVtWMXocv7GdyePzJrkA9ig9m6L80pJUhYz8 4hJbpWhDCyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TUnMyy1CJ9uwS9jAezfAtelVU8u/eVvYGx Jb2LkZNDQsBEYkXzT/YuRi4OIYGljBKvZ51hgUjISJyc1sAKYQtL/LnWxQZR9IlRYlnbKTaQ BJuAoUTX2y4wW0TASeL95IvMIDazwEpmiYPb8kBsYYFkidlv1oENZRFQlVhxax+YzStgK7H7 1lZ2iAXyEqs3HADq5eDgFLCTONakBBIWAirZd+oV8wRGvgWMDKsYRVJLi3PTc4uN9IoTc4tL 89L1kvNzNzECg3/bsZ9bdjB2vQs+xCjAwajEw3vh9sx4IdbEsuLK3EOMEhzMSiK8TmdPxwnx piRWVqUW5ccXleakFh9iNAW6aSKzlGhyPjAy80riDU0NzS0sDc2NzY3NLJTEeTsEDsYICaQn lqRmp6YWpBbB9DFxcEo1MFqqvI5b/4ZlkejjAzMXrjUp4c1vsbNjaEjcpzpjxd0pL6KZP0R8 Xf/flGlb9UUXlpL8CY/YZba9mPvmronIVZ4KpbW/fl++aM1UvTeu5Ych9+u/D/9d+ChQvEP0 pMOqw3caZvyq7a+WaG3W7uDfk6ST8Y+5+EWBrZ0aZ3dLd5hA8HnPRYEOm5VYijMSDbWYi4oT AYMoIYOUAgAA X-CMS-MailID: 20201029134039eucas1p2270e5f4ecea05b17f4d9107300ce946d X-Msg-Generator: CA X-RootMTR: 20201029134039eucas1p2270e5f4ecea05b17f4d9107300ce946d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201029134039eucas1p2270e5f4ecea05b17f4d9107300ce946d References: <20201029134017.27400-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Jaehoon Chung Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM: dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY variant found in the Exynos5433 SoCs. Signed-off-by: Jaehoon Chung [mszyprow: reworked the driver to support only Exynos5433 variant, rebased onto current kernel code, rewrote commit message] Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski Reviewed-by: Jingoo Han --- drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++---------------- 1 file changed, 112 insertions(+), 192 deletions(-) -- 2.17.1 diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c index 7e28b1aea0d1..d91de323dd0e 100644 --- a/drivers/phy/samsung/phy-exynos-pcie.c +++ b/drivers/phy/samsung/phy-exynos-pcie.c @@ -4,70 +4,41 @@ * * Phy provider for PCIe controller on Exynos SoC series * - * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd. * Jaehoon Chung */ -#include #include -#include -#include #include -#include -#include #include #include #include #include -/* PCIe Purple registers */ -#define PCIE_PHY_GLOBAL_RESET 0x000 -#define PCIE_PHY_COMMON_RESET 0x004 -#define PCIE_PHY_CMN_REG 0x008 -#define PCIE_PHY_MAC_RESET 0x00c -#define PCIE_PHY_PLL_LOCKED 0x010 -#define PCIE_PHY_TRSVREG_RESET 0x020 -#define PCIE_PHY_TRSV_RESET 0x024 - -/* PCIe PHY registers */ -#define PCIE_PHY_IMPEDANCE 0x004 -#define PCIE_PHY_PLL_DIV_0 0x008 -#define PCIE_PHY_PLL_BIAS 0x00c -#define PCIE_PHY_DCC_FEEDBACK 0x014 -#define PCIE_PHY_PLL_DIV_1 0x05c -#define PCIE_PHY_COMMON_POWER 0x064 -#define PCIE_PHY_COMMON_PD_CMN BIT(3) -#define PCIE_PHY_TRSV0_EMP_LVL 0x084 -#define PCIE_PHY_TRSV0_DRV_LVL 0x088 -#define PCIE_PHY_TRSV0_RXCDR 0x0ac -#define PCIE_PHY_TRSV0_POWER 0x0c4 -#define PCIE_PHY_TRSV0_PD_TSV BIT(7) -#define PCIE_PHY_TRSV0_LVCC 0x0dc -#define PCIE_PHY_TRSV1_EMP_LVL 0x144 -#define PCIE_PHY_TRSV1_RXCDR 0x16c -#define PCIE_PHY_TRSV1_POWER 0x184 -#define PCIE_PHY_TRSV1_PD_TSV BIT(7) -#define PCIE_PHY_TRSV1_LVCC 0x19c -#define PCIE_PHY_TRSV2_EMP_LVL 0x204 -#define PCIE_PHY_TRSV2_RXCDR 0x22c -#define PCIE_PHY_TRSV2_POWER 0x244 -#define PCIE_PHY_TRSV2_PD_TSV BIT(7) -#define PCIE_PHY_TRSV2_LVCC 0x25c -#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4 -#define PCIE_PHY_TRSV3_RXCDR 0x2ec -#define PCIE_PHY_TRSV3_POWER 0x304 -#define PCIE_PHY_TRSV3_PD_TSV BIT(7) -#define PCIE_PHY_TRSV3_LVCC 0x31c - -struct exynos_pcie_phy_data { - const struct phy_ops *ops; -}; +#define PCIE_PHY_OFFSET(x) ((x) * 0x4) + +/* Sysreg FSYS register offsets and bits for Exynos5433 */ +#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208 +#define PCIE_MAC_RESET_MASK 0xFF +#define PCIE_MAC_RESET BIT(4) +#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010 +#define PCIE_REFCLK_GATING_EN BIT(0) +#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020 +#define PCIE_PHY_RESET BIT(0) +#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040 +#define PCIE_GLOBAL_RESET BIT(0) +#define PCIE_REFCLK BIT(1) +#define PCIE_REFCLK_MASK 0x16 +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5) + +/* PMU PCIE PHY isolation control */ +#define EXYNOS5433_PMU_PCIE_PHY_OFFSET 0x730 /* For Exynos pcie phy */ struct exynos_pcie_phy { - const struct exynos_pcie_phy_data *drv_data; - void __iomem *phy_base; - void __iomem *blk_base; /* For exynos5440 */ + void __iomem *base; + struct regmap *pmureg; + struct regmap *fsysreg; }; static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset) @@ -75,153 +46,103 @@ static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset) writel(val, base + offset); } -static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset) -{ - return readl(base + offset); -} - -/* For Exynos5440 specific functions */ -static int exynos5440_pcie_phy_init(struct phy *phy) +/* Exynos5433 specific functions */ +static int exynos5433_pcie_phy_init(struct phy *phy) { struct exynos_pcie_phy *ep = phy_get_drvdata(phy); - /* DCC feedback control off */ - exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK); - - /* set TX/RX impedance */ - exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE); - - /* set 50Mhz PHY clock */ - exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0); - exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1); - - /* set TX Differential output for lane 0 */ - exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL); - - /* set TX Pre-emphasis Level Control for lane 0 to minimum */ - exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL); - - /* set RX clock and data recovery bandwidth */ - exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS); - exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR); - exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR); - exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR); - exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR); - - /* change TX Pre-emphasis Level Control for lanes */ - exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL); - exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL); - exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL); - exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL); - - /* set LVCC */ - exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC); - exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC); - exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC); - exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC); - - /* pulse for common reset */ - exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET); - udelay(500); - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET); - + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET, + PCIE_PHY_RESET, 1); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET, + PCIE_MAC_RESET, 0); + + /* PHY refclk 24MHz */ + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, + PCIE_REFCLK_MASK, PCIE_REFCLK); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, + PCIE_GLOBAL_RESET, 0); + + + exynos_pcie_phy_writel(ep->base, 0x11, PCIE_PHY_OFFSET(0x3)); + + /* band gap reference on */ + exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x20)); + exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x4b)); + + /* jitter tunning */ + exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x4)); + exynos_pcie_phy_writel(ep->base, 0x02, PCIE_PHY_OFFSET(0x7)); + exynos_pcie_phy_writel(ep->base, 0x41, PCIE_PHY_OFFSET(0x21)); + exynos_pcie_phy_writel(ep->base, 0x7F, PCIE_PHY_OFFSET(0x14)); + exynos_pcie_phy_writel(ep->base, 0xC0, PCIE_PHY_OFFSET(0x15)); + exynos_pcie_phy_writel(ep->base, 0x61, PCIE_PHY_OFFSET(0x36)); + + /* D0 uninit.. */ + exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x3D)); + + /* 24MHz */ + exynos_pcie_phy_writel(ep->base, 0x94, PCIE_PHY_OFFSET(0x8)); + exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x9)); + exynos_pcie_phy_writel(ep->base, 0x93, PCIE_PHY_OFFSET(0xA)); + exynos_pcie_phy_writel(ep->base, 0x6B, PCIE_PHY_OFFSET(0xC)); + exynos_pcie_phy_writel(ep->base, 0xA5, PCIE_PHY_OFFSET(0xF)); + exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x16)); + exynos_pcie_phy_writel(ep->base, 0xA3, PCIE_PHY_OFFSET(0x17)); + exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x1A)); + exynos_pcie_phy_writel(ep->base, 0x71, PCIE_PHY_OFFSET(0x23)); + exynos_pcie_phy_writel(ep->base, 0x4C, PCIE_PHY_OFFSET(0x24)); + + exynos_pcie_phy_writel(ep->base, 0x0E, PCIE_PHY_OFFSET(0x26)); + exynos_pcie_phy_writel(ep->base, 0x14, PCIE_PHY_OFFSET(0x7)); + exynos_pcie_phy_writel(ep->base, 0x48, PCIE_PHY_OFFSET(0x43)); + exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x44)); + exynos_pcie_phy_writel(ep->base, 0x03, PCIE_PHY_OFFSET(0x45)); + exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x48)); + exynos_pcie_phy_writel(ep->base, 0x13, PCIE_PHY_OFFSET(0x54)); + exynos_pcie_phy_writel(ep->base, 0x04, PCIE_PHY_OFFSET(0x31)); + exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x32)); + + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET, + PCIE_PHY_RESET, 0); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET, + PCIE_MAC_RESET_MASK, PCIE_MAC_RESET); return 0; } -static int exynos5440_pcie_phy_power_on(struct phy *phy) +static int exynos5433_pcie_phy_power_on(struct phy *phy) { struct exynos_pcie_phy *ep = phy_get_drvdata(phy); - u32 val; - - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET); - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG); - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET); - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER); - val &= ~PCIE_PHY_COMMON_PD_CMN; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER); - val &= ~PCIE_PHY_TRSV0_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER); - val &= ~PCIE_PHY_TRSV1_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER); - val &= ~PCIE_PHY_TRSV2_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER); - val &= ~PCIE_PHY_TRSV3_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER); + regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET, + BIT(0), 1); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET, + PCIE_APP_REQ_EXIT_L1_MODE, 0); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON, + PCIE_REFCLK_GATING_EN, 0); return 0; } -static int exynos5440_pcie_phy_power_off(struct phy *phy) +static int exynos5433_pcie_phy_power_off(struct phy *phy) { struct exynos_pcie_phy *ep = phy_get_drvdata(phy); - u32 val; - - if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val, - (val != 0), 1, 500)) { - dev_err(&phy->dev, "PLL Locked: 0x%x\n", val); - return -ETIMEDOUT; - } - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER); - val |= PCIE_PHY_COMMON_PD_CMN; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER); - val |= PCIE_PHY_TRSV0_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER); - val |= PCIE_PHY_TRSV1_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER); - val |= PCIE_PHY_TRSV2_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER); - - val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER); - val |= PCIE_PHY_TRSV3_PD_TSV; - exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER); + regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON, + PCIE_REFCLK_GATING_EN, PCIE_REFCLK_GATING_EN); + regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET, + BIT(0), 0); return 0; } -static int exynos5440_pcie_phy_reset(struct phy *phy) -{ - struct exynos_pcie_phy *ep = phy_get_drvdata(phy); - - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET); - exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET); - exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET); - - return 0; -} - -static const struct phy_ops exynos5440_phy_ops = { - .init = exynos5440_pcie_phy_init, - .power_on = exynos5440_pcie_phy_power_on, - .power_off = exynos5440_pcie_phy_power_off, - .reset = exynos5440_pcie_phy_reset, +static const struct phy_ops exynos5433_phy_ops = { + .init = exynos5433_pcie_phy_init, + .power_on = exynos5433_pcie_phy_power_on, + .power_off = exynos5433_pcie_phy_power_off, .owner = THIS_MODULE, }; -static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = { - .ops = &exynos5440_phy_ops, -}; - static const struct of_device_id exynos_pcie_phy_match[] = { { - .compatible = "samsung,exynos5440-pcie-phy", - .data = &exynos5440_pcie_phy_data, + .compatible = "samsung,exynos5433-pcie-phy", }, {}, }; @@ -232,30 +153,30 @@ static int exynos_pcie_phy_probe(struct platform_device *pdev) struct exynos_pcie_phy *exynos_phy; struct phy *generic_phy; struct phy_provider *phy_provider; - struct resource *res; - const struct exynos_pcie_phy_data *drv_data; - - drv_data = of_device_get_match_data(dev); - if (!drv_data) - return -ENODEV; exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL); if (!exynos_phy) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - exynos_phy->phy_base = devm_ioremap_resource(dev, res); - if (IS_ERR(exynos_phy->phy_base)) - return PTR_ERR(exynos_phy->phy_base); + exynos_phy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(exynos_phy->base)) + return PTR_ERR(exynos_phy->base); - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - exynos_phy->blk_base = devm_ioremap_resource(dev, res); - if (IS_ERR(exynos_phy->blk_base)) - return PTR_ERR(exynos_phy->blk_base); + exynos_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,pmu-syscon"); + if (IS_ERR(exynos_phy->pmureg)) { + dev_err(&pdev->dev, "PMU regmap lookup failed.\n"); + return PTR_ERR(exynos_phy->pmureg); + } - exynos_phy->drv_data = drv_data; + exynos_phy->fsysreg = syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,fsys-sysreg"); + if (IS_ERR(exynos_phy->fsysreg)) { + dev_err(&pdev->dev, "FSYS sysreg regmap lookup failed.\n"); + return PTR_ERR(exynos_phy->fsysreg); + } - generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops); + generic_phy = devm_phy_create(dev, dev->of_node, &exynos5433_phy_ops); if (IS_ERR(generic_phy)) { dev_err(dev, "failed to create PHY\n"); return PTR_ERR(generic_phy); @@ -275,5 +196,4 @@ static struct platform_driver exynos_pcie_phy_driver = { .suppress_bind_attrs = true, } }; - builtin_platform_driver(exynos_pcie_phy_driver); From patchwork Thu Oct 29 13:40:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 311047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF7CBC4363A for ; Thu, 29 Oct 2020 13:50:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5D84B20809 for ; Thu, 29 Oct 2020 13:50:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="m4XN8no9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727454AbgJ2Nue (ORCPT ); Thu, 29 Oct 2020 09:50:34 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:42269 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725300AbgJ2Nud (ORCPT ); Thu, 29 Oct 2020 09:50:33 -0400 Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20201029134041euoutp01803fa400b045d01cb57f38bba31c0227~CekIqZjoC0672406724euoutp01e for ; Thu, 29 Oct 2020 13:40:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20201029134041euoutp01803fa400b045d01cb57f38bba31c0227~CekIqZjoC0672406724euoutp01e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1603978841; bh=G7+cs0Cey9mc1jUmzGnGpiHoQ8KNRi7EJkpJq7+FJtw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m4XN8no9xJ84HMBOlxCnje+FVbK/wC+nq+MmMQyIxtMQvFnTIbyrdTcdIUXYiTAN+ 8DGJnox3BExRiXOXop0zaZ9jAb6CQMPK8u+XmouZ0YscPityCYGr1pCtwol6M5J/4d uWjnz7a45qLvflrjzZ3bcIB3AsuPpdwvZarYSuVc= Received: from eusmges2new.samsung.com (unknown [203.254.199.244]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20201029134041eucas1p155b4949ffe67b6c3d13ec01ef0cc42eb~CekH-d4MP0596605966eucas1p1M; Thu, 29 Oct 2020 13:40:41 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges2new.samsung.com (EUCPMTA) with SMTP id 4C.99.05997.956CA9F5; Thu, 29 Oct 2020 13:40:41 +0000 (GMT) Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20201029134040eucas1p2a8958b44842a8a4647e3aa4521c75725~CekHj4xNl0841008410eucas1p2Z; Thu, 29 Oct 2020 13:40:40 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20201029134040eusmtrp24faa91cd5b16d567bd3e90e0fb74f44c~CekHjMRNb0455804558eusmtrp2Y; Thu, 29 Oct 2020 13:40:40 +0000 (GMT) X-AuditID: cbfec7f4-677ff7000000176d-42-5f9ac65995aa Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 6F.91.06017.856CA9F5; Thu, 29 Oct 2020 13:40:40 +0000 (GMT) Received: from AMDC2765.digital.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20201029134040eusmtip11497fb3783904a71700c403a00bb994d~CekG8YpxE2155521555eusmtip19; Thu, 29 Oct 2020 13:40:40 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH v3 6/6] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards Date: Thu, 29 Oct 2020 14:40:17 +0100 Message-Id: <20201029134017.27400-7-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201029134017.27400-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjm29nOOQ6Xx6Phh5WDdbPIWxYdSMVU6lR/qh+hgdp0J5V0yo6X TARboTZvswIvmIommbdsielQsyWboW4jKQw1LOhiZGbT8NryeLT+Pe9z+Z6Xlw9HyBqRO56g TGVUSnmiDBULO41LFq8IY2W0b3seSj1Qx1M1A2YRNbacK6Ia5yswyvqpEKUslnaMGtVXodRI tQmlyi19Aur7yleMah2YxCh7TxdGdU8MIsESuqW6BdDdlZMYXatLo3VNt1G6uKMJ0KaxZwLa pvM4h10SByiYxIR0RuUTdFkcX/axHElZlF4b6rWAHFDkrgEOOCSOQK2uB9MAMU4SjQBWlZgF nEAS8wBOLyG8YAOwqH4FbCWK74+LeOEhgCWfi1B+WE/k3f0t5Fwo4Qc1M5p1AcddiWC4uEBx HoSoQWDp+3EBx7sQ4bB3NZyzC4m90FqwhHG0hAiELWuRfJcUNrf3IxztQARBo1rGvQKJJgwa 7I829wmD6p9mIY9d4DdTB8bjndDeXSPgAzcB/GBuxfihEMBRdflm+jicMC9v7IkQB+BjvQ9P n4D2vsGNYkhsg2MzzhyNrMM7nWWbtATm55K8ex+sNLX9q31hfY3wmIYt/Q2bNywFMN/2FNUC aeX/sloAmoAbk8YmxTHsYSWT4c3Kk9g0ZZx3bHKSDqx/m6E/pvkuoF+NMQACBzJHiXW8IpoU ydPZzCQDgDgic5WEjAxFkRKFPPM6o0qOVqUlMqwB7MCFMjeJf910JEnEyVOZqwyTwqi2VAHu 4J4DSo8NGBOUrTH7pVNtmWeynodl/Mgazu73Ubz0ny34lX7F1GNhzTcaQrSv5h1tw6ke20/F ip3PT71LXvAkw0LfKCL2LOtHnOrp4ah7u+pIM7XkFnryYu8X3yinC7vTPcPXDEcnHfWnZXN7 7E7ZGq9Apb/ubMFsc8Bb7ZNbh+aMAgeZkI2X+x1EVKz8LxMU6tEyAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpkkeLIzCtJLcpLzFFi42I5/e/4Xd2IY7PiDVrPq1gsacqwmH/kHKvF jV9trBYrvsxkt7jwtIfN4vz5DewWl3fNYbM4O+84m8WM8/uYLN78fsFusfbIXXaL/3t2sFvs vHOC2YHXY828NYweO2fdZfdYsKnUY9OqTjaPvi2rGD2O39jO5PF5k1wAe5SeTVF+aUmqQkZ+ cYmtUrShhZGeoaWFnpGJpZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexvRHM5gLfshXnN57nrGB sVeqi5GTQ0LARKJv7m3WLkYuDiGBpYwSU1e0skMkZCROTmtghbCFJf5c62KDKPrEKPHy2Adm kASbgKFE11uQBCeHiICTxPvJF8HizAIrmSUObssDsYUFwiRuznsINpRFQFXiQvdPIJuDg1fA VmLN31iI+fISqzccYAYJcwrYSRxrUgIJCwFV7Dv1inkCI98CRoZVjCKppcW56bnFRnrFibnF pXnpesn5uZsYgcG/7djPLTsYu94FH2IU4GBU4uG9cHtmvBBrYllxZe4hRgkOZiURXqezp+OE eFMSK6tSi/Lji0pzUosPMZoCnTSRWUo0OR8YmXkl8YamhuYWlobmxubGZhZK4rwdAgdjhATS E0tSs1NTC1KLYPqYODilGhg91rzuSj06tS5xTr6vjm1dRJLnBRmzv7KtcyReT/JpeP5wkuqS D+dL9vikBN9O//h9zf7cc2tWlvPZW509fr1q0e3XT80MKjk6nzJr3rZpS5m2uu0d/6GFIkfO rDr4n/P1pYZUxhzGrJ8PPM/Ptp3z9umG2avu3U6uuJdUsGbj/F9z9/sV7Li8XYmlOCPRUIu5 qDgRADSB6GuUAgAA X-CMS-MailID: 20201029134040eucas1p2a8958b44842a8a4647e3aa4521c75725 X-Msg-Generator: CA X-RootMTR: 20201029134040eucas1p2a8958b44842a8a4647e3aa4521c75725 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201029134040eucas1p2a8958b44842a8a4647e3aa4521c75725 References: <20201029134017.27400-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Jaehoon Chung Add the nodes relevant to PCIe PHY and PCIe support. PCIe is used for the WiFi interface (Broadcom Limited BCM4358 802.11ac Wireless LAN SoC). Signed-off-by: Jaehoon Chung [mszyprow: rewrote commit message, reworked board/generic dts/dtsi split] Signed-off-by: Marek Szyprowski --- .../boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +- .../dts/exynos/exynos5433-tm2-common.dtsi | 24 ++++++++++++- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 36 +++++++++++++++++++ 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi index 9df7c65593a1..32a6518517e5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -329,7 +329,7 @@ }; pcie_bus: pcie_bus { - samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6"; samsung,pin-function = ; samsung,pin-pud = ; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 97a2f0c7c0cf..5ec447f0cf5d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -968,6 +968,25 @@ bus-width = <4>; }; +&pcie { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_bus &pcie_wlanen>; + vdd10-supply = <&ldo6_reg>; + vdd18-supply = <&ldo7_reg>; + assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>, + <&cmu_top CLK_MOUT_SCLK_PCIE_100>; + assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>, + <&cmu_top CLK_MOUT_BUS_PLL_USER>; + assigned-clock-rates = <0>, <100000000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; +}; + +&pcie_phy { + status = "okay"; +}; + &ppmu_d0_general { status = "okay"; events { @@ -1084,8 +1103,11 @@ pinctrl-names = "default"; pinctrl-0 = <&initial_ese>; + pcie_wlanen: pcie-wlanen { + PIN(INPUT, gpj2-0, UP, FAST_SR4); + }; + initial_ese: initial-state { - PIN(INPUT, gpj2-0, DOWN, FAST_SR1); PIN(INPUT, gpj2-1, DOWN, FAST_SR1); PIN(INPUT, gpj2-2, DOWN, FAST_SR1); }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0a886bb6c806..1d2442ac432c 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1029,6 +1029,11 @@ reg = <0x145f0000 0x1038>; }; + syscon_fsys: syscon@156f0000 { + compatible = "syscon"; + reg = <0x156f0000 0x1044>; + }; + gsc_0: video-scaler@13c00000 { compatible = "samsung,exynos5433-gsc"; reg = <0x13c00000 0x1000>; @@ -1830,6 +1835,37 @@ status = "disabled"; }; }; + + pcie_phy: pcie-phy@15680000 { + compatible = "samsung,exynos5433-pcie-phy"; + reg = <0x15680000 0x1000>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&syscon_fsys>; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie: pcie@15700000 { + compatible = "samsung,exynos5433-pcie"; + reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, + <0x0c000000 0x1000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = ; + clocks = <&cmu_fsys CLK_PCIE>, + <&cmu_fsys CLK_PCLK_PCIE_PHY>; + clock-names = "pcie", "pcie_bus"; + num-lanes = <1>; + num-viewport = <3>; + bus-range = <0x00 0xff>; + phys = <&pcie_phy>; + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + status = "disabled"; + }; }; timer: timer {