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vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:40:31 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:40:31 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv2 1/7] PCI: dwc: Fix a bug of the case dw_pci->ops is NULL Date: Tue, 27 Oct 2020 15:29:55 +0800 Message-Id: <20201027073001.41808-2-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: hcm7Ul3kfTUBEhXGfVzaVLi8l6i8ncnbD2Vt7ONS7uUPPQiQ7Snw7h3D9UZdWGPQUyXproUxjxhk94qc+wss0nuM3JzfPcmu16UlPDMoBPwYk4+r1UFdq/z4C8oxtBUTZeKUn1K5FJ28dk/QEvGOXQOWijEdmMRZ3cGG4ue9jrgMaSVsBNvvR1rIdoJzxGo8AeCLbSktCtGQpIpDefSjildnDQ3J6kSvgaDREy86l+9C0UDh++JLpfnylodpMUAm8uUSaF9nkWF3KhsSw6wrueVvVddxNkCZj1l+MgnVOtXVEDiWTd1K1azbq5xnHRKH9ptYma18XFbjPq9HkBDPIurVVhVgQqZwoQXQkf99uCCA89eP+n9NA9v1Nthmyxa52dxi7YCUCuv97FyTPbECuM+R3blreBYwMiUqeRbRXa/ADm8zFmR/Hk8BdrzKirVmFoGb4sHRf+rFpq7dXe6lfCiJ20NR+ipZlgQLk4YFg3t/AJYCKBMLJMKG1RT66zQUqPbhWwjGVPb+YlpOYboOyT8vBzs90/SDvUuLacA4GD6dQiWf1LHdWRyi+KiFHKghd5B0PpuD1z9q8H+QoRbn7pW9uH9thmYHRas0Qie7X/59HbGEwCkItVurbcILaIg9lXo23F4QspkmzOsAqr5Wxw== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6eaf557c-4359-4ed3-5895-08d87a4b7340 X-MS-Exchange-CrossTenant-AuthSource: HE1PR0402MB3371.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2020 07:39:35.1615 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AcmWZNwpZLAw2uXMSlnPGOh3RIzeEEp0K9BoJExg7cT92+/5qrWZhEwVWO3k3u72px87zm4SzSPQ+IIokCHNtQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3371 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Hou Zhiqiang The dw_pci->ops may be a NULL, and fix it by adding one more check. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring Acked-by: Gustavo Pimentel --- V2: - Rebased the patch against the latest code. drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index c2dea8fc97c8..7a5024450c4d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -141,7 +141,7 @@ u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) int ret; u32 val; - if (pci->ops->read_dbi) + if (pci->ops && pci->ops->read_dbi) return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); ret = dw_pcie_read(pci->dbi_base + reg, size, &val); @@ -156,7 +156,7 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) { int ret; - if (pci->ops->write_dbi) { + if (pci->ops && pci->ops->write_dbi) { pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); return; } @@ -171,7 +171,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) { int ret; - if (pci->ops->write_dbi2) { + if (pci->ops && pci->ops->write_dbi2) { pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); return; } @@ -186,7 +186,7 @@ static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg) int ret; u32 val; - if (pci->ops->read_dbi) + if (pci->ops && pci->ops->read_dbi) return pci->ops->read_dbi(pci, pci->atu_base, reg, 4); ret = dw_pcie_read(pci->atu_base + reg, 4, &val); @@ -200,7 +200,7 @@ static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) { int ret; - if (pci->ops->write_dbi) { + if (pci->ops && pci->ops->write_dbi) { pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val); return; } @@ -271,7 +271,7 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, { u32 retries, val; - if (pci->ops->cpu_addr_fixup) + if (pci->ops && pci->ops->cpu_addr_fixup) cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); if (pci->iatu_unroll_enabled) { @@ -479,7 +479,7 @@ int dw_pcie_link_up(struct dw_pcie *pci) { u32 val; - if (pci->ops->link_up) + if (pci->ops && pci->ops->link_up) return pci->ops->link_up(pci); val = readl(pci->dbi_base + PCIE_PORT_DEBUG1); From patchwork Tue Oct 27 07:29:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhiqiang Hou X-Patchwork-Id: 310870 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB4D9C4363A for ; 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dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:41:21 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:41:21 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv2 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Date: Tue, 27 Oct 2020 15:29:57 +0800 Message-Id: <20201027073001.41808-4-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; 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Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring --- V2: - No change. Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index daa99f7d4c3f..0033c898976e 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -39,6 +39,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { From patchwork Tue Oct 27 07:29:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhiqiang Hou X-Patchwork-Id: 310869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BA62C4363A for ; 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dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:43:14 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:43:14 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv2 5/7] dt-bindings: pci: layerscape-pci: Update the description of SCFG property Date: Tue, 27 Oct 2020 15:29:59 +0800 Message-Id: <20201027073001.41808-6-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; 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Signed-off-by: Hou Zhiqiang Acked-by: Rob Herring --- V2: - No change. Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 0033c898976e..4228562be505 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -33,7 +33,7 @@ Required properties: "intr": The interrupt that is asserted for controller interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software From patchwork Tue Oct 27 07:30:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhiqiang Hou X-Patchwork-Id: 310868 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A01F0C4363A for ; Tue, 27 Oct 2020 07:48:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 20BF220738 for ; Tue, 27 Oct 2020 07:48:16 +0000 (UTC) Authentication-Results: mail.kernel.org; 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vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) by HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Tue, 27 Oct 2020 07:45:51 +0000 Received: from HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e]) by HE1PR0402MB3371.eurprd04.prod.outlook.com ([fe80::f882:7106:de07:1e1e%4]) with mapi id 15.20.3477.028; Tue, 27 Oct 2020 07:45:51 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv2 7/7] PCI: layerscape: Add power management support Date: Tue, 27 Oct 2020 15:30:01 +0800 Message-Id: <20201027073001.41808-8-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> References: <20201027073001.41808-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by SGAP274CA0002.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; 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Signed-off-by: Hou Zhiqiang --- V2: - Change to use the common defines to access the RC configuration registers. drivers/pci/controller/dwc/pci-layerscape.c | 380 ++++++++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 379 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index be404c16bcbe..9886eaead593 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -3,13 +3,16 @@ * PCIe host controller driver for Freescale Layerscape SoCs * * Copyright (C) 2014 Freescale Semiconductor. + * Copyright 2020 NXP * * Author: Minghuan Lian */ +#include #include #include #include +#include #include #include #include @@ -27,17 +30,60 @@ #define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */ #define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */ +/* PF Message Command Register */ +#define LS_PCIE_PF_MCR 0x2c +#define PF_MCR_PTOMR BIT(0) +#define PF_MCR_EXL2S BIT(1) + +/* LS1021A PEXn PM Write Control Register */ +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) +#define PMXMTTURNOFF BIT(31) +#define SCFG_PEXSFTRSTCR 0x190 +#define PEXSR(idx) BIT(idx) + +/* LS1043A PEX PME control register */ +#define SCFG_PEXPMECR 0x144 +#define PEXPME(idx) BIT(31 - (idx) * 4) + +/* LS1043A PEX LUT debug register */ +#define LS_PCIE_LDBG 0x7fc +#define LDBG_SR BIT(30) +#define LDBG_WE BIT(31) + #define PCIE_IATU_NUM 6 +#define LS_PCIE_IS_L2(v) \ + (((v) & PORT_LOGIC_LTSSM_STATE_MASK) == PORT_LOGIC_LTSSM_STATE_L2) + +struct ls_pcie; + +struct ls_pcie_host_pm_ops { + int (*pm_init)(struct ls_pcie *pcie); + void (*send_turn_off_message)(struct ls_pcie *pcie); + void (*exit_from_l2)(struct ls_pcie *pcie); +}; + struct ls_pcie_drvdata { + const u32 pf_off; + const u32 lut_off; const struct dw_pcie_host_ops *ops; + const struct ls_pcie_host_pm_ops *pm_ops; }; struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; + void __iomem *pf_base; + void __iomem *lut_base; + bool big_endian; + bool ep_presence; + bool pm_support; + struct regmap *scfg; + int index; }; +#define ls_pcie_lut_readl_addr(addr) ls_pcie_lut_readl(pcie, addr) +#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr) #define to_ls_pcie(x) dev_get_drvdata((x)->dev) static bool ls_pcie_is_bridge(struct ls_pcie *pcie) @@ -86,6 +132,210 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); } +static u32 ls_pcie_lut_readl(struct ls_pcie *pcie, u32 off) +{ + if (pcie->big_endian) + return ioread32be(pcie->lut_base + off); + + return ioread32(pcie->lut_base + off); +} + +static void ls_pcie_lut_writel(struct ls_pcie *pcie, u32 off, u32 val) +{ + if (pcie->big_endian) + return iowrite32be(val, pcie->lut_base + off); + + return iowrite32(val, pcie->lut_base + off); + +} + +static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off) +{ + if (pcie->big_endian) + return ioread32be(pcie->pf_base + off); + + return ioread32(pcie->pf_base + off); +} + +static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) +{ + if (pcie->big_endian) + return iowrite32be(val, pcie->pf_base + off); + + return iowrite32(val, pcie->pf_base + off); + +} + +static void ls_pcie_send_turnoff_msg(struct ls_pcie *pcie) +{ + u32 val; + int ret; + + val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val |= PF_MCR_PTOMR; + ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + + ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + val, !(val & PF_MCR_PTOMR), 100, 10000); + if (ret) + dev_info(pcie->pci->dev, "poll turn off message timeout\n"); +} + +static void ls1021a_pcie_send_turnoff_msg(struct ls_pcie *pcie) +{ + u32 val; + + if (!pcie->scfg) { + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); + return; + } + + /* Send Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); + val |= PMXMTTURNOFF; + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); + + mdelay(10); + + /* Clear Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); + val &= ~PMXMTTURNOFF; + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); +} + +static void ls1043a_pcie_send_turnoff_msg(struct ls_pcie *pcie) +{ + u32 val; + + if (!pcie->scfg) { + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); + return; + } + + /* Send Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); + val |= PEXPME(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); + + mdelay(10); + + /* Clear Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); + val &= ~PEXPME(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); +} + +static void ls_pcie_exit_from_l2(struct ls_pcie *pcie) +{ + u32 val; + int ret; + + val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val |= PF_MCR_EXL2S; + ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + + ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + val, !(val & PF_MCR_EXL2S), 100, 10000); + if (ret) + dev_info(pcie->pci->dev, "poll exit L2 state timeout\n"); +} + +static void ls_pcie_retrain_link(struct ls_pcie *pcie) +{ + struct dw_pcie *pci = pcie->pci; + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; + + val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL); + val |= PCI_EXP_LNKCTL_RL; + dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCTL, val); +} + +static void ls1021a_pcie_exit_from_l2(struct ls_pcie *pcie) +{ + u32 val; + + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); + val |= PEXSR(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); + + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); + val &= ~PEXSR(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); + + mdelay(1); + + ls_pcie_retrain_link(pcie); +} +static void ls1043a_pcie_exit_from_l2(struct ls_pcie *pcie) +{ + u32 val; + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_WE; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_SR; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_SR; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_WE; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + mdelay(1); + + ls_pcie_retrain_link(pcie); +} + +static int ls1021a_pcie_pm_init(struct ls_pcie *pcie) +{ + struct device *dev = pcie->pci->dev; + u32 index[2]; + int ret; + + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, + "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + ret = PTR_ERR(pcie->scfg); + dev_err(dev, "No syscfg phandle specified\n"); + pcie->scfg = NULL; + return ret; + } + + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", + index, 2); + if (ret) { + pcie->scfg = NULL; + return ret; + } + + pcie->index = index[1]; + + return 0; +} + +static int ls_pcie_pm_init(struct ls_pcie *pcie) +{ + return 0; +} + +static void ls_pcie_set_dstate(struct ls_pcie *pcie, u32 dstate) +{ + struct dw_pcie *pci = pcie->pci; + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_PM); + u32 val; + + val = dw_pcie_readw_dbi(pci, offset + PCI_PM_CTRL); + val &= ~PCI_PM_CTRL_STATE_MASK; + val |= dstate; + dw_pcie_writew_dbi(pci, offset + PCI_PM_CTRL, val); +} + static int ls_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -133,20 +383,52 @@ static int ls_pcie_msi_host_init(struct pcie_port *pp) return 0; } +static struct ls_pcie_host_pm_ops ls1021a_pcie_host_pm_ops = { + .pm_init = &ls1021a_pcie_pm_init, + .send_turn_off_message = &ls1021a_pcie_send_turnoff_msg, + .exit_from_l2 = &ls1021a_pcie_exit_from_l2, +}; + +static struct ls_pcie_host_pm_ops ls1043a_pcie_host_pm_ops = { + .pm_init = &ls1021a_pcie_pm_init, + .send_turn_off_message = &ls1043a_pcie_send_turnoff_msg, + .exit_from_l2 = &ls1043a_pcie_exit_from_l2, +}; + +static struct ls_pcie_host_pm_ops ls_pcie_host_pm_ops = { + .pm_init = &ls_pcie_pm_init, + .send_turn_off_message = &ls_pcie_send_turnoff_msg, + .exit_from_l2 = &ls_pcie_exit_from_l2, +}; + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .msi_host_init = ls_pcie_msi_host_init, }; +static const struct ls_pcie_drvdata ls1021a_drvdata = { + .ops = &ls_pcie_host_ops, + .pm_ops = &ls1021a_pcie_host_pm_ops, +}; + +static const struct ls_pcie_drvdata ls1043a_drvdata = { + .ops = &ls_pcie_host_ops, + .lut_off = 0x10000, + .pm_ops = &ls1043a_pcie_host_pm_ops, +}; + static const struct ls_pcie_drvdata layerscape_drvdata = { .ops = &ls_pcie_host_ops, + .lut_off = 0x80000, + .pf_off = 0xc0000, + .pm_ops = &ls_pcie_host_pm_ops, }; static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, - { .compatible = "fsl,ls1021a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, @@ -170,6 +452,15 @@ static int __init ls_add_pcie_port(struct ls_pcie *pcie) return ret; } + if (dw_pcie_link_up(pci)) { + dev_dbg(pci->dev, "Endpoint is present\n"); + pcie->ep_presence = true; + } + + if (pcie->drvdata->pm_ops && pcie->drvdata->pm_ops->pm_init && + !pcie->drvdata->pm_ops->pm_init(pcie)) + pcie->pm_support = true; + return 0; } @@ -200,6 +491,14 @@ static int __init ls_pcie_probe(struct platform_device *pdev) if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); + pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); + + if (pcie->drvdata->lut_off) + pcie->lut_base = pci->dbi_base + pcie->drvdata->lut_off; + + if (pcie->drvdata->pf_off) + pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + if (!ls_pcie_is_bridge(pcie)) return -ENODEV; @@ -212,11 +511,88 @@ static int __init ls_pcie_probe(struct platform_device *pdev) return 0; } +static bool ls_pcie_pm_check(struct ls_pcie *pcie) +{ + if (!pcie->ep_presence) { + dev_dbg(pcie->pci->dev, "Endpoint isn't present\n"); + return false; + } + + if (!pcie->pm_support) + return false; + + return true; +} + +#ifdef CONFIG_PM_SLEEP +static int ls_pcie_suspend_noirq(struct device *dev) +{ + struct ls_pcie *pcie = dev_get_drvdata(dev); + struct dw_pcie *pci = pcie->pci; + u32 val; + int ret; + + if (!ls_pcie_pm_check(pcie)) + return 0; + + pcie->drvdata->pm_ops->send_turn_off_message(pcie); + + /* 10ms timeout to check L2 ready */ + ret = readl_poll_timeout(pci->dbi_base + PCIE_PORT_DEBUG0, + val, LS_PCIE_IS_L2(val), 100, 10000); + if (ret) { + dev_err(dev, "PCIe link enter L2 timeout! ltssm = 0x%x\n", val); + return ret; + } + + ls_pcie_set_dstate(pcie, 0x3); + + return 0; +} + +static int ls_pcie_resume_noirq(struct device *dev) +{ + struct ls_pcie *pcie = dev_get_drvdata(dev); + struct dw_pcie *pci = pcie->pci; + int ret; + + if (!ls_pcie_pm_check(pcie)) + return 0; + + ls_pcie_set_dstate(pcie, 0x0); + + pcie->drvdata->pm_ops->exit_from_l2(pcie); + + /* delay 10ms to access EP */ + mdelay(10); + + ret = ls_pcie_host_init(&pci->pp); + if (ret) { + dev_err(dev, "ls_pcie_host_init failed! ret = 0x%x\n", ret); + return ret; + } + + ret = dw_pcie_wait_for_link(pci); + if (ret) { + dev_err(dev, "wait link up timeout! ret = 0x%x\n", ret); + return ret; + } + + return 0; +} +#endif /* CONFIG_PM_SLEEP */ + +static const struct dev_pm_ops ls_pcie_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(ls_pcie_suspend_noirq, + ls_pcie_resume_noirq) +}; + static struct platform_driver ls_pcie_driver = { .driver = { .name = "layerscape-pcie", .of_match_table = ls_pcie_of_match, .suppress_bind_attrs = true, + .pm = &ls_pcie_pm_ops, }, }; builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9d2f511f13fa..0d863f525057 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -54,6 +54,7 @@ #define PCIE_PORT_DEBUG0 0x728 #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f #define PORT_LOGIC_LTSSM_STATE_L0 0x11 +#define PORT_LOGIC_LTSSM_STATE_L2 0x15 #define PCIE_PORT_DEBUG1 0x72C #define PCIE_PORT_DEBUG1_LINK_UP BIT(4) #define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)