From patchwork Wed Oct 28 23:27:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 314832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 832D2C55179 for ; Wed, 28 Oct 2020 23:28:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 30A552080D for ; Wed, 28 Oct 2020 23:28:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="TJMtRRrd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390598AbgJ1X2l (ORCPT ); Wed, 28 Oct 2020 19:28:41 -0400 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:20041 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390569AbgJ1X2H (ORCPT ); Wed, 28 Oct 2020 19:28:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1603927686; x=1635463686; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6n2d3Nw4+/BvSQCZVekBcYAwmYCImlxAQwh3nDgopHc=; b=TJMtRRrdbeT92L6GRmQff7c2Kl0lNwfaurtCdQfhX25SalFmFYrj3pGm bo5yR3KrzFBvdbdd5BB+I2ZNHgflnFDZhDaVRsk3Fu+OFLuctlPo0lrgp Mjn/6YDoyc9ernLzmnoUgq7VywFvl4+rSJ7qBVEf4g5lcjOD58dTloM+Y Cj+jmnBXKfUEvrZi1TMmdyQKXOk9MuWHTO9xHAdJysjJobPykJ1RHUOkX wfLPW/lD3EDQOyNfD8yeur3JFXVVn013MgPbBNezEoz2zjrz9c+DY0rGJ H5VGjU0EAeM+oWQntEpv4HRB2rKT1qnat5h5WjfWr42pM3OISXe4ovYNL g==; IronPort-SDR: ZuF6SaX8tEiW5f16jD7tWKEby97hSaifxwgWFCJ5Hl1DQeSYG4grbHNr0TjstNovClQdAa7dUF xhBRdftK9YCY2ZZGAZy880+dHk2Umm20DYoxlsGcVSjC3YXW2aEooXnZexv4jBJP9LzYDZfmZ4 wV8nsAKu/B5tMkm+UURY8AraQbbcTDucLbJSqxMAv/1hZ7i+9wkWpbsh1OSpyvwb2PLrNWMVic +IGa/72R8aFLzL2Dk9I98A7R5TCTLIEUogfeaG5FzSU9ghakGS9++F5ufOTwKeY/vqbIyuFYCU B3w= X-IronPort-AV: E=Sophos;i="5.77,428,1596470400"; d="scan'208";a="155611420" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 29 Oct 2020 07:28:06 +0800 IronPort-SDR: XrKxTqml/lbAFmiO0hYnR/rMWHty/+5vaCfy5/3mWqZu4eRzBOxfDEwiEztTeRn6AF9BrDH4Nz qoaZzm/2LFEQnKOyuTzLiPVnoutpec8cp2+k2jqhWNflIjSl+xZHGfpLlv/OCYFHQ7pfvzs+1t wS0qJ3FBrdQVnDFIEG93drDcQcHbnaXtDy9t+TvI0TqrWe+WI01FO4lVNXBwPnc0uQHraNZxbk FWaqVzEMN37i8oQCbQ9VSTOzAuwKVE+0Cuw3RmLN+f0VApQSmeNunDHjGnuq20KGCh3Mi73S4r PKtaHSVOmCClQ5bJZuUgRk/S Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2020 16:14:22 -0700 IronPort-SDR: dEjHin5uDaUncBBDKai1yiEDYvkh/5xbx9tbjqOIIhUNxWR9COUDwsaTbfD8OhLCHXAKBaH8sO JRl/JzxvEXUrLoKVtX0dihBQAcbnboJDogsemdy1o8lwaB7zYsw2Km4OpwbeHRFcpx7AeO83lt g3UI16nVWp3Ux4rzKEYXSD5NKtfbJD1AUT3Qh0a3pAs4kQggbMpqlb/nv42qU2VUGP+rmgyGjA 6eQj7oGORrPbysgCtZOcbPDzR0utnwrJpjKg6+DDH+Wlu1pzyltYsnMrkCMFCRqtKbZydeseKA PNg= WDCIronportException: Internal Received: from myd002180.ad.shared (HELO jedi-01.hgst.com) ([10.86.60.107]) by uls-op-cesaip01.wdc.com with ESMTP; 28 Oct 2020 16:28:07 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alistair Francis , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring , padmarao.begari@microchip.com, Daire McNamara , Cyril.Jean@microchip.com Subject: [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Date: Wed, 28 Oct 2020 16:27:57 -0700 Message-Id: <20201028232759.1928479-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028232759.1928479-1-atish.patra@wdc.com> References: <20201028232759.1928479-1-atish.patra@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Microchip PolarFire kconfig option which selects SoC specific and common drivers that is required for this SoC. Signed-off-by: Atish Patra Reviewed-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt --- arch/riscv/Kconfig.socs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 8a55f6156661..74d07250ecc5 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -22,6 +22,13 @@ config SOC_VIRT help This enables support for QEMU Virt Machine. +config SOC_MICROCHIP_POLARFIRE + bool "Microchip PolarFire SoCs" + select MCHP_CLK_PFSOC + select SIFIVE_PLIC + help + This enables support for Microchip PolarFire SoC platforms. + config SOC_KENDRYTE bool "Kendryte K210 SoC" depends on !MMU From patchwork Wed Oct 28 23:27:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 314833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 304A9C56201 for ; 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28 Oct 2020 16:14:23 -0700 IronPort-SDR: sdRoHQdPlyCEHZmgp8+a3JWtc/prLV6e8i85ZXglbSwulbo4SA+7TdtLwTiZ/xFLGk9GHzYAat 7ymi/80XcAZUkEwRsW3YcaCbzb7udiSB6YtB2QajVBilIxPeVcEJLJ6zeFHQ9pMlqb7i7StsZK m8byTaakphoH56tRhCTUF/+mgJ4XRz74nO8Q9rkf/jeCJpo/tsERC3RKNu2h062jABLSkQWFIP Kzy9M3CUAQnrZzEAxakgwl+uiheDdLvVUJWC7F4AeSTDd/DCdRqvyT7ZrWHzVp5gjcz7kebcQw Cbg= WDCIronportException: Internal Received: from myd002180.ad.shared (HELO jedi-01.hgst.com) ([10.86.60.107]) by uls-op-cesaip01.wdc.com with ESMTP; 28 Oct 2020 16:28:07 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alistair Francis , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring , padmarao.begari@microchip.com, Daire McNamara , Cyril.Jean@microchip.com Subject: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board Date: Wed, 28 Oct 2020 16:27:58 -0700 Message-Id: <20201028232759.1928479-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028232759.1928479-1-atish.patra@wdc.com> References: <20201028232759.1928479-1-atish.patra@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial DTS for Microchip ICICLE board having only essential devcies (clocks, sdhci, ethernet, serial, etc). Signed-off-by: Atish Patra --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/microchip/Makefile | 2 + .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++ 3 files changed, 316 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/Makefile create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ca1f8cbd78c0..3ea94ea0a18a 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += sifive subdir-y += kendryte +subdir-y += microchip obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile new file mode 100644 index 000000000000..55ad77521304 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts new file mode 100644 index 000000000000..5848920af55c --- /dev/null +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2020 Microchip Technology Inc */ + +/dts-v1/; + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PolarFire-SoC"; + compatible = "microchip,polarfire-soc"; + + chosen { + stdout-path = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = ; + + cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@1 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@2 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@3 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@4 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + clocks = <&clkcfg 26>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + + clint@2000000 { + compatible = "riscv,clint0"; + reg = <0x0 0x2000000 0x0 0xC000>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; + }; + + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11 + &cpu1_intc 11 &cpu1_intc 9 + &cpu2_intc 11 &cpu2_intc 9 + &cpu3_intc 11 &cpu3_intc 9 + &cpu4_intc 11 &cpu4_intc 9>; + }; + + dma@3000000 { + compatible = "sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = <23 24 25 26 27 28 29 30>; + #dma-cells = <1>; + }; + + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + clock-output-names = "msspllclk"; + }; + + clkcfg: clkcfg@20002000 { + compatible = "microchip,pfsoc-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>; + reg-names = "mss_sysreg"; + clocks = <&refclk>; + #clock-cells = <1>; + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk"; + }; + + serial0: serial@20000000 { + compatible = "ns16550a"; + reg = <0x0 0x20000000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <90>; + current-speed = <115200>; + clocks = <&clkcfg 8>; + status = "okay"; + }; + + serial1: serial@20100000 { + compatible = "ns16550a"; + reg = <0x0 0x20100000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <91>; + current-speed = <115200>; + clocks = <&clkcfg 9>; + status = "okay"; + }; + + serial2: serial@20102000 { + compatible = "ns16550a"; + reg = <0x0 0x20102000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <92>; + current-speed = <115200>; + clocks = <&clkcfg 10>; + status = "okay"; + }; + + serial3: serial@20104000 { + compatible = "ns16550a"; + reg = <0x0 0x20104000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <93>; + current-speed = <115200>; + clocks = <&clkcfg 11>; + status = "okay"; + }; + + sdcard: sdhc@20008000 { + compatible = "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88>; + pinctrl-names = "default"; + clocks = <&clkcfg 6>; + bus-width = <4>; + disable-wp; + no-1-8-v; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <200000000>; + status = "okay"; + }; + + emac1: ethernet@20112000 { + compatible = "cdns,macb"; + reg = <0x0 0x20112000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <70 71 72 73>; + mac-address = [56 34 12 00 FC 00]; + phy-mode = "sgmii"; + clocks = <&clkcfg 5>, <&clkcfg 2>; + clock-names = "pclk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@9 { + reg = <9>; + ti,fifo-depth = <0x01>; + }; + }; + + uio_axi_lsram@2030000000 { + compatible = "generic-uio"; + reg = <0x20 0x30000000 0 0x80000000 >; + status = "okay"; + }; + }; +}; From patchwork Wed Oct 28 23:27:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 314834 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93C36C4363A for ; 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IronPort-SDR: Wg3Bg+qcJWqdd6/QGCxM/eiz/grrWqx60mCd/y4nPVNmGfgkj2VpY5pyldjp7KMTrQkaRczOm5 U9jo+VPevekV2ORXS8cJ2THMbSwCHnAh2auSSifX846r/Dz+yAwHQzltD0g0iMKRdGcecGGtW8 Dbhve2oLceW2oT2zFjB2ZhqbWP9KxwOD0XhFRiwHdYWpLiR6oUz8owPenei5Mg7N8fUcQstqRn jV+v3zYn/BraNYQB8jY/s91ppPFPKiZiwsE1gu/oxCDLCzPDlPnWVqQraCdQi+9Ar2bRi5iU41 yEM= X-IronPort-AV: E=Sophos;i="5.77,428,1596470400"; d="scan'208";a="155611424" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 29 Oct 2020 07:28:07 +0800 IronPort-SDR: EJFOM87XrKCk+mpnGIEtnR4IAkDRlFXgMkXTOlKZmtMsfnQe4NUKew5ORz2ygYmmzJtjwSj6B/ 7LEZemOhOejeimuNMcMlR4fHKace1jL1azQrGxcyPdQeVQwxWEFqXUULqx4bLJB3GsQ5Ox1Clm jCwULkQwvfbTOfQoekUFEOiRSv97k+aW4w51Vr2NOX8iD+gKiVtW7sFI0cvSud/jxZxe4ctBfY 0eOaYBMdhc/t1Mv7erOSvv9vf+uZFfKhP4gwJHlTsiGfhHrNylyVbij6E/ETh83aXfAoXPR7Qe oqMT26FBQ9edprBfJlaQmYi7 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2020 16:14:23 -0700 IronPort-SDR: 94lWjA8ui21z5dRyHN8PFZLWc4UbJh3udYMvZwY9leNLlEB8hUj+d1Z/jiMQcWUW7nsSihk7lE De3GYYbvK3lkjiMk/0VstuQyyR07X7e7Nu4hoRn9agFLCYiKJt4QQ50Tdh80eMih/LGBigp8M0 YF4Oro9CD5i31jZTZiMSllyoN6XzPvseyy2jZQK0GjkEhFzFJ6aj0z5kIPRf8wtwUdctUo7UdD gKiq4jBVFuM6YFUEVh5FVbmmXhPISPJ9c5N8NAgSnNMt2dHBWCDeA5nRnyKMt6UNmLAA7y793f 8fc= WDCIronportException: Internal Received: from myd002180.ad.shared (HELO jedi-01.hgst.com) ([10.86.60.107]) by uls-op-cesaip01.wdc.com with ESMTP; 28 Oct 2020 16:28:08 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alistair Francis , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring , padmarao.begari@microchip.com, Daire McNamara , Cyril.Jean@microchip.com Subject: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC Date: Wed, 28 Oct 2020 16:27:59 -0700 Message-Id: <20201028232759.1928479-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028232759.1928479-1-atish.patra@wdc.com> References: <20201028232759.1928479-1-atish.patra@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable Microchip PolarFire ICICLE soc config in defconfig. It allows the default upstream kernel to boot on PolarFire ICICLE board. Signed-off-by: Atish Patra Reviewed-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt --- arch/riscv/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d222d353d86d..2660fa05451e 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -16,6 +16,7 @@ CONFIG_EXPERT=y CONFIG_BPF_SYSCALL=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y +CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_SMP=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y @@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_STORAGE=y CONFIG_USB_UAS=y +CONFIG_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC=y CONFIG_MMC_SPI=y CONFIG_RTC_CLASS=y