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[209.132.180.67]) by mx.google.com with ESMTP id j20si1518144pfh.75.2017.12.19.01.46.08; Tue, 19 Dec 2017 01:46:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LtJbS9/D; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966973AbdLSJqF (ORCPT + 28 others); Tue, 19 Dec 2017 04:46:05 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:18110 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030236AbdLSJp5 (ORCPT ); Tue, 19 Dec 2017 04:45:57 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ9jrbJ027611; Tue, 19 Dec 2017 03:45:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513676753; bh=ZEl50q124V+QV2kE9zTa+B6lIgJ8WYEmsu+H98q6rkw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LtJbS9/DUhv2PoVtN7v5d/FzUhpVmUgKiamf839HmzRtsr80fxKc6hF91Ry1LemzD siYsfDK7WoMJf6Djd67zpba+cGjvHuvwLEAAu/tSdXuRbqxUdK9ncwSm69Jpi+UZLj daLxCOFxqUbZ5AJknzLcMhC6sF+mfOGD9PGxCgc0= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9jrS0005243; Tue, 19 Dec 2017 03:45:53 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 03:45:52 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 03:45:53 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9jk2i028458; Tue, 19 Dec 2017 03:45:50 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Mark Rutland , CC: , , , Subject: [PATCH 1/2] dt-bindings: phy: ti-pipe3: Add dt binding to use USB3 PHY for PCIe Date: Tue, 19 Dec 2017 15:15:39 +0530 Message-ID: <20171219094540.18432-2-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219094540.18432-1-kishon@ti.com> References: <20171219094540.18432-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DRA72 uses USB3 PHY for the 2nd lane of PCIE. Add dt bindings property to indicate if the USB3 PHY should be used for 2nd lane of PCIe. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/ti-phy.txt | 2 ++ 1 file changed, 2 insertions(+) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt index cd13e6157088..907a046e794b 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt @@ -93,6 +93,8 @@ Optional properties: register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. - syscon-pcs : phandle/offset pair. Phandle to the system control module and the register offset to write the PCS delay value. + - "ti,configure-as-pcie" : property to indicate if the PHY should be + configured as PCIE PHY. Deprecated properties: - ctrl-module : phandle of the control module used by PHY driver to power on From patchwork Tue Dec 19 09:45:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 122358 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3925043qgn; Tue, 19 Dec 2017 01:46:33 -0800 (PST) X-Google-Smtp-Source: ACJfBouyVP2dSO7/SSmaSSFE2tcwyXWJeXQ+Mbfx+c/P9ZFB2CsC64NTNJWKt29vF2XIWP9b10Wa X-Received: by 10.101.69.203 with SMTP id m11mr2364647pgr.200.1513676793785; Tue, 19 Dec 2017 01:46:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513676793; cv=none; d=google.com; s=arc-20160816; b=l9ndUvXZP/+NB5CsD1Hcc1rqQwRTV7Va5VMwPhg3EYG4mgJwWr5kXLpP9zFL+M3ZT1 hEbBwcNAR3BsxQ0vR//tCsS6/jx1To0wbCA5v21LTiAB8/fITFso6fVzLOxiLwqZZ/F+ RjhZH/JkEePSw/K0SUkH+VDoxiWcL60fESVtpRSM8k4fEecPZ4tEhtN4YJ7Ra9s/Lnke ew+/JqRshrDRBdE46rZAi/oqs/1W2MBerSWBn95YSZG1akxGEYycO4Pm1WO5A+FFCnvC Ei3OspSVft1p2IETPCRhWOc62fKlo/hWjSEMdTpFUrdSFMSYWHEW4e52cIUVaLSlMTOY lwCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=yXEDskXEkYO+b/lClzk4fsML14juqGKKK9nTtB/SBB8=; b=rqCbTwyv2DhWoFlxU+zXV7CWu+MvVIa+LeRNw01YzqT1psrnWE0OXnWf+p+oLam+K+ OMHsSITG89Bu+j6ZRASaUmA1I1qAgV5OlnzAPsZE8zZuYbRnDU2beTJrROEuFC1guG40 uvjhF2eehADv9OW+8vkbw6qSGjLLgcVBqzILhi/uxzpQQwS3NOJpkaT48abJWrkk8XLy lSucyTgisxt1frHyDUf36FSUiiIAlTyaZ8qyEXwsoVXxUY6WexX0T3HgGFhC6f9WYVby 1e7bFkS7jnOFa2cCtdsKKcGBqEkCXL8i2KRoXuL+39VNMvOntoUoTntVDUiN4oLab/hG L4dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SMJzfkPM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The configuration required to make USB3 PHY used for the 2nd lane of PCIe is done here. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/phy-ti-pipe3.c | 47 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 41 insertions(+), 6 deletions(-) -- 2.11.0 diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index 68ce4a082b9b..d5a7cc435fb7 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -56,6 +56,12 @@ #define SATA_PLL_SOFT_RESET BIT(18) +#define PHY_RX_ANA_PRGRAMMABILITY_REG 0xC +#define MEM_EN_PLLBYP BIT(7) + +#define PHY_TX_TEST_CONFIG 0x2C +#define MEM_ENTESTCLK BIT(31) + #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14 @@ -110,6 +116,10 @@ #define PLL_IDLE_TIME 100 /* in milliseconds */ #define PLL_LOCK_TIME 100 /* in milliseconds */ +#define PIPE3_PHY_DISABLE_SYNC_POWER BIT(4) + +#define CONFIGURE_AS_PCIE BIT(0) + struct pipe3_dpll_params { u16 m; u8 n; @@ -141,6 +151,7 @@ struct ti_pipe3 { unsigned int power_reg; /* power reg. index within syscon */ unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */ bool sata_refclk_enabled; + u32 flags; }; static struct pipe3_dpll_map dpll_map_usb[] = { @@ -233,11 +244,22 @@ static int ti_pipe3_power_on(struct phy *x) rate = rate / 1000000; mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK; - val = PIPE3_PHY_TX_RX_POWERON << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + val = PIPE3_PHY_TX_RX_POWERON; + if (phy->flags & CONFIGURE_AS_PCIE) + val |= PIPE3_PHY_DISABLE_SYNC_POWER; + val <<= PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; val |= rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, mask, val); + + if (phy->flags & CONFIGURE_AS_PCIE) { + ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, + mask, val); + if (ret < 0) + return ret; + } + return ret; } @@ -335,6 +357,19 @@ static int ti_pipe3_init(struct phy *x) int ret = 0; ti_pipe3_enable_clocks(phy); + + if (phy->flags & CONFIGURE_AS_PCIE) { + val = ti_pipe3_readl(phy->phy_rx, + PHY_RX_ANA_PRGRAMMABILITY_REG); + val |= MEM_EN_PLLBYP; + ti_pipe3_writel(phy->phy_rx, PHY_RX_ANA_PRGRAMMABILITY_REG, + val); + val = ti_pipe3_readl(phy->phy_tx, PHY_TX_TEST_CONFIG); + val |= MEM_ENTESTCLK; + ti_pipe3_writel(phy->phy_tx, PHY_TX_TEST_CONFIG, val); + return 0; + } + /* * Set pcie_pcs register to 0x96 for proper functioning of phy * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table @@ -395,7 +430,8 @@ static int ti_pipe3_exit(struct phy *x) return 0; /* PCIe doesn't have internal DPLL */ - if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) { + if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie") && + !(phy->flags & CONFIGURE_AS_PCIE)) { /* Put DPLL in IDLE mode */ val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); val |= PLL_IDLE; @@ -589,12 +625,8 @@ static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy) { struct resource *res; struct device *dev = phy->dev; - struct device_node *node = dev->of_node; struct platform_device *pdev = to_platform_device(dev); - if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) - return 0; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_rx"); phy->phy_rx = devm_ioremap_resource(dev, res); @@ -666,6 +698,9 @@ static int ti_pipe3_probe(struct platform_device *pdev) if (ret) return ret; + if (of_property_read_bool(node, "ti,configure-as-pcie")) + phy->flags |= CONFIGURE_AS_PCIE; + platform_set_drvdata(pdev, phy); pm_runtime_enable(dev);