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[209.132.180.67]) by mx.google.com with ESMTP id n16si1118583pll.476.2017.12.14.05.12.02; Thu, 14 Dec 2017 05:12:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vu98626e; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752634AbdLNNL3 (ORCPT + 20 others); Thu, 14 Dec 2017 08:11:29 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:33521 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752511AbdLNNLV (ORCPT ); Thu, 14 Dec 2017 08:11:21 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBEDAQrc013234; Thu, 14 Dec 2017 07:10:26 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513257026; bh=cj6lMiXPDUPKj/e59Q1NhmrkCtOZjbkPYLMi1H53Lc8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vu98626ebx5uKGUsncOGTKpt6NRQAKC9wGeeGyr1tKXany2ZFbfJ4zoCGbTLjIvsN ntGcfKmekKHyCmx1wJmi5ti+3XAGaSKv/IGF+uoouYJCgC9Jsm5wJHzVGFa2cD3w8v PnDOQW7LV29xSe2tF4MoydQN6AA4Q59Kzp5ZH6uY= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBEDAQ8W014014; Thu, 14 Dec 2017 07:10:26 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 14 Dec 2017 07:10:25 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 14 Dec 2017 07:10:25 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBED9wdS032017; Thu, 14 Dec 2017 07:10:22 -0600 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren , Adrian Hunter CC: Mark Rutland , Russell King , , , , , , , Subject: [PATCH 06/12] mmc: sdhci_omap: Add support to set IODELAY values Date: Thu, 14 Dec 2017 18:39:35 +0530 Message-ID: <20171214130941.26666-7-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171214130941.26666-1-kishon@ti.com> References: <20171214130941.26666-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. Add support to set the IODELAY values depending on the various MMC modes using the pinctrl APIs. Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci-omap.c | 174 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 174 insertions(+) -- 2.11.0 diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index b20f4c79ccc6..594e41200d8a 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -93,8 +93,12 @@ #define MAX_PHASE_DELAY 0x7C +/* sdhci-omap controller flags */ +#define SDHCI_OMAP_REQUIRE_IODELAY BIT(0) + struct sdhci_omap_data { u32 offset; + u8 flags; }; struct sdhci_omap_host { @@ -105,6 +109,20 @@ struct sdhci_omap_host { struct sdhci_host *host; u8 bus_mode; u8 power_mode; + u8 timing; + u8 flags; + + struct pinctrl *pinctrl; + struct pinctrl_state *pinctrl_state; + struct pinctrl_state *default_pinctrl_state; + struct pinctrl_state *sdr104_pinctrl_state; + struct pinctrl_state *hs200_1_8v_pinctrl_state; + struct pinctrl_state *ddr50_pinctrl_state; + struct pinctrl_state *sdr50_pinctrl_state; + struct pinctrl_state *sdr25_pinctrl_state; + struct pinctrl_state *sdr12_pinctrl_state; + struct pinctrl_state *hs_pinctrl_state; + struct pinctrl_state *ddr_1_8v_pinctrl_state; }; static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host); @@ -449,6 +467,62 @@ static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc, return 0; } +static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing) +{ + int ret; + struct pinctrl_state *pinctrl_state; + struct device *dev = omap_host->dev; + + if (omap_host->timing == timing) + return; + + sdhci_omap_stop_clock(omap_host); + + switch (timing) { + case MMC_TIMING_UHS_SDR104: + pinctrl_state = omap_host->sdr104_pinctrl_state; + break; + case MMC_TIMING_MMC_HS200: + pinctrl_state = omap_host->hs200_1_8v_pinctrl_state; + break; + case MMC_TIMING_UHS_DDR50: + pinctrl_state = omap_host->ddr50_pinctrl_state; + break; + case MMC_TIMING_UHS_SDR50: + pinctrl_state = omap_host->sdr50_pinctrl_state; + break; + case MMC_TIMING_UHS_SDR25: + pinctrl_state = omap_host->sdr25_pinctrl_state; + break; + case MMC_TIMING_UHS_SDR12: + pinctrl_state = omap_host->sdr12_pinctrl_state; + break; + case MMC_TIMING_SD_HS: + case MMC_TIMING_MMC_HS: + pinctrl_state = omap_host->hs_pinctrl_state; + break; + case MMC_TIMING_MMC_DDR52: + pinctrl_state = omap_host->ddr_1_8v_pinctrl_state; + break; + default: + pinctrl_state = omap_host->default_pinctrl_state; + break; + } + + if (omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY) { + ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state); + if (ret) { + dev_err(dev, "failed to select pinctrl state\n"); + goto ret; + } + omap_host->pinctrl_state = pinctrl_state; + } + +ret: + sdhci_omap_start_clock(omap_host); + omap_host->timing = timing; +} + static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host, u8 power_mode) { @@ -485,6 +559,7 @@ static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) omap_host = sdhci_pltfm_priv(pltfm_host); sdhci_omap_set_bus_mode(omap_host, ios->bus_mode); + sdhci_omap_set_timing(omap_host, ios->timing); sdhci_set_ios(mmc, ios); sdhci_omap_set_power_mode(omap_host, ios->power_mode); } @@ -693,6 +768,7 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = { static const struct sdhci_omap_data dra7_data = { .offset = 0x200, + .flags = SDHCI_OMAP_REQUIRE_IODELAY, }; static const struct of_device_id omap_sdhci_match[] = { @@ -701,6 +777,98 @@ static const struct of_device_id omap_sdhci_match[] = { }; MODULE_DEVICE_TABLE(of, omap_sdhci_match); +static struct pinctrl_state +*sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode, + u32 *caps, u32 capmask) +{ + struct device *dev = omap_host->dev; + struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV); + + if (!(*caps & capmask)) + goto ret; + + pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode); + if (IS_ERR(pinctrl_state)) { + dev_err(dev, "no pinctrl state for %s mode", mode); + *caps &= ~capmask; + } + +ret: + return pinctrl_state; +} + +static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host + *omap_host) +{ + struct device *dev = omap_host->dev; + struct sdhci_host *host = omap_host->host; + struct mmc_host *mmc = host->mmc; + u32 *caps = &mmc->caps; + u32 *caps2 = &mmc->caps2; + struct pinctrl_state *state; + + if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY)) + return 0; + + omap_host->pinctrl = devm_pinctrl_get(omap_host->dev); + if (IS_ERR(omap_host->pinctrl)) { + dev_err(dev, "Cannot get pinctrl\n"); + return PTR_ERR(omap_host->pinctrl); + } + + state = pinctrl_lookup_state(omap_host->pinctrl, "default"); + if (IS_ERR(state)) { + dev_err(dev, "no pinctrl state for default mode\n"); + return PTR_ERR(state); + } + omap_host->default_pinctrl_state = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps, + MMC_CAP_UHS_SDR104); + if (!IS_ERR(state)) + omap_host->sdr104_pinctrl_state = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps, + MMC_CAP_UHS_DDR50); + if (!IS_ERR(state)) + omap_host->ddr50_pinctrl_state = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps, + MMC_CAP_UHS_SDR50); + if (!IS_ERR(state)) + omap_host->sdr50_pinctrl_state = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps, + MMC_CAP_UHS_SDR25); + if (!IS_ERR(state)) + omap_host->sdr25_pinctrl_state = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps, + MMC_CAP_UHS_SDR12); + if (!IS_ERR(state)) + omap_host->sdr12_pinctrl_state = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps, + MMC_CAP_1_8V_DDR); + if (!IS_ERR(state)) + omap_host->ddr_1_8v_pinctrl_state = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps, + MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_SD_HIGHSPEED); + if (!IS_ERR(state)) + omap_host->hs_pinctrl_state = state; + + state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2, + MMC_CAP2_HS200_1_8V_SDR); + if (!IS_ERR(state)) + omap_host->hs200_1_8v_pinctrl_state = state; + + omap_host->pinctrl_state = omap_host->default_pinctrl_state; + + return 0; +} + static int sdhci_omap_probe(struct platform_device *pdev) { int ret; @@ -737,6 +905,8 @@ static int sdhci_omap_probe(struct platform_device *pdev) omap_host->base = host->ioaddr; omap_host->dev = dev; omap_host->power_mode = MMC_POWER_UNDEFINED; + omap_host->timing = MMC_TIMING_LEGACY; + omap_host->flags = data->flags; host->ioaddr += offset; mmc = host->mmc; @@ -785,6 +955,10 @@ static int sdhci_omap_probe(struct platform_device *pdev) goto err_put_sync; } + ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host); + if (ret) + goto err_put_sync; + host->mmc_host_ops.get_ro = mmc_gpio_get_ro; host->mmc_host_ops.start_signal_voltage_switch = sdhci_omap_start_signal_voltage_switch; From patchwork Thu Dec 14 13:09:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 121929 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6787117qgn; Thu, 14 Dec 2017 05:12:44 -0800 (PST) X-Google-Smtp-Source: ACJfBouyngJnvRr4T4okE5McNZKETKExQCViWYjuO3oAiOCccColhe6pFNycPMGtMJkQEeESZv4I X-Received: by 10.99.127.91 with SMTP id p27mr8448394pgn.1.1513257164828; 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[209.132.180.67]) by mx.google.com with ESMTP id p5si2892253pgq.124.2017.12.14.05.12.44; Thu, 14 Dec 2017 05:12:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=u4s4qEyx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752716AbdLNNMl (ORCPT + 20 others); Thu, 14 Dec 2017 08:12:41 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:22200 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752303AbdLNNMi (ORCPT ); Thu, 14 Dec 2017 08:12:38 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBEDAZGi022233; Thu, 14 Dec 2017 07:10:35 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513257035; bh=9CcIPRF0g+hQeJ/4wuKkOyylM9yS6KnlnNI1GZJ/8GE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=u4s4qEyxNTQECeG+Zqs12x8t76KtJ8ZsyHrp2/q5pVTUfs7XdWfjVNLAN14CAYDwH 8IP61Ye4xfSXkHnKpf0scZMUpatMWP7QJC5G3WqiPIERUZDiVOAL9Yxea9GZiYbJLi vRGhw0V8gij1NYpmLPnzMsA9myPcoePD5Y9LooiA= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBEDAU4j020428; Thu, 14 Dec 2017 07:10:30 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 14 Dec 2017 07:10:29 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 14 Dec 2017 07:10:29 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBED9wdT032017; Thu, 14 Dec 2017 07:10:26 -0600 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren , Adrian Hunter CC: Mark Rutland , Russell King , , , , , , , Subject: [PATCH 07/12] mmc: sdhci_omap: Fix sdhci-omap quirks Date: Thu, 14 Dec 2017 18:39:36 +0530 Message-ID: <20171214130941.26666-8-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171214130941.26666-1-kishon@ti.com> References: <20171214130941.26666-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove SDHCI_QUIRK_BROKEN_CARD_DETECTION quirk as gpio card detection is supported in sdhci-omap. Add SDHCI_QUIRK2_PRESET_VALUE_BROKEN quirk as setting preset values loads incorrect CLKD values (for UHS modes). Remove SDHCI_QUIRK2_NO_1_8_V quirk as sdhci-omap now supports UHS modes. Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci-omap.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) -- 2.11.0 diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index 594e41200d8a..6dee275b2e57 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -755,13 +755,12 @@ static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host) } static const struct sdhci_pltfm_data sdhci_omap_pdata = { - .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | - SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | + .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, - .quirks2 = SDHCI_QUIRK2_NO_1_8_V | - SDHCI_QUIRK2_ACMD23_BROKEN | + .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | + SDHCI_QUIRK2_PRESET_VALUE_BROKEN | SDHCI_QUIRK2_RSP_136_HAS_CRC, .ops = &sdhci_omap_ops, }; From patchwork Thu Dec 14 13:09:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 121928 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6786539qgn; Thu, 14 Dec 2017 05:12:15 -0800 (PST) X-Google-Smtp-Source: ACJfBosOnzpiXU/56vwvmtc3sba+Mja7X7aoord5wS520lSwlyORyXoesNmlOdZA6k85cZ5q2lig X-Received: by 10.159.218.150 with SMTP id w22mr9122055plp.91.1513257135729; Thu, 14 Dec 2017 05:12:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513257135; cv=none; d=google.com; s=arc-20160816; b=Jeiuxk/m29pLuxWexx2VHZYoMgiwCIti/rap4LUcWRnlyKKn7CSeXhHBOEa8vpKuVO 3v2VebvkF0cSRI9npT45vdP+KAQEINNVS0v7z5+CWv8zTeiy+tfywdf8cCqBDJWBruaQ VJk4P8Nai8e7PxCg2TNLqzggDzjjsTsI3ZbB2Qt6Ux9mT9O9+VdY1UEZgI+iN9OJiWPO 2l0SJiZxLF6Lp6r7ydtKkhvEL1DBC3TjFhEqXIqmJlFMa0TZtLPYrp2fxobZa0Y9IndS BZN/Kj99o6hXNRWQFjRj3Fnr7Gr9LiedddqO3lqaHilRb5Hn3r9cMmGTvkZFaB0srFcS /IrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=DowXcglzdJz1tDJNO+t8twOLAJ8IwrhmquS4cLCMbtE=; b=OFhksk6gF6zZnkHIz/mZzzoyl9BvYuFRbjHMvgfSGIK7Sxnczv4J+XfBBBL9lQ8/2o na7d2TOqXEzU1Zg82jBVmttbqzKYc5K4Q0aL7QYm7fFDXTc4GYcKAY0FZTOOLc8xzQEU CPsMwoGTVhGs9iPM23dMDWO43h9XWDr5CmoHzJvJKyRQvYYcv8IAPGv3mdyn2GiIrRGt W/WmGOpRO45M9395Rq3XUNWldh6f1AuGBQxI6OtMzA0POkzSksB5TQQkN8j5fg7owkvl 1rAAQ26OZwPllkKAnE1jVNYRLkE5Ytr3rj4ADaG5J6JBH46qYbxSOHC+F7fmEaTZ4ugP JxXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vD3SlnB+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o72si3218249pfa.375.2017.12.14.05.12.15; Thu, 14 Dec 2017 05:12:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vD3SlnB+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752613AbdLNNL0 (ORCPT + 20 others); Thu, 14 Dec 2017 08:11:26 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:33517 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752572AbdLNNLU (ORCPT ); Thu, 14 Dec 2017 08:11:20 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBEDAbZs013249; Thu, 14 Dec 2017 07:10:37 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513257037; bh=AUBy2BztH9lbp4BL82Nll0utHCryvAAFs2E29KQXzuk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vD3SlnB+4VzCV+XcqObJBqn+4XI4e8JDmiDLbKv5P1cfjTgIkr604Qioz+lzcOfnt NWiZNldvx6XqngN4C4nrXTAAe/1FrMQ8V7e9/JvWAEfSrKnw/pjRp0hzEEt552lAs7 mhMeLF4IxHeJV3V6fjbFtmZ/Vl8FX9/5/IufB7Cc= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBEDAbmS014315; Thu, 14 Dec 2017 07:10:37 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 14 Dec 2017 07:10:37 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 14 Dec 2017 07:10:37 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBED9wdV032017; Thu, 14 Dec 2017 07:10:33 -0600 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren , Adrian Hunter CC: Mark Rutland , Russell King , , , , , , , Subject: [RFC PATCH 09/12] mmc: sdhci: Use software timer when timeout greater than hardware capablility Date: Thu, 14 Dec 2017 18:39:38 +0530 Message-ID: <20171214130941.26666-10-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171214130941.26666-1-kishon@ti.com> References: <20171214130941.26666-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Errata i834 in AM572x Sitara Processors Silicon Revision 2.0, 1.1 (SPRZ429K July 2014–Revised March 2017 [1]) mentions Under high speed HS200 and SDR104 modes, the functional clock for MMC modules will reach up to 192 MHz. At this frequency, the maximum obtainable timeout (DTO = 0xE) through MMC host controller is (1/192MHz)*2^27 = 700ms. Commands taking longer than 700ms may be affected by this small window frame. Workaround for this errata is use a software timer instead of hardware timer to provide the delay requested by the upper layer. While this errata is specific to AM572x, it is applicable to all sdhci based controllers when a particular request require timeout greater than hardware capability. Re-use the software timer already implemented in sdhci to program the correct timeout value and also disable the hardware timeout when the required timeout is greater than hardware capabiltiy in order to avoid spurious timeout interrupts. This patch is based on the earlier patch implemented for omap_hsmmc [2] [1] -> http://www.ti.com/lit/er/sprz429k/sprz429k.pdf [2] -> https://patchwork.kernel.org/patch/9791449/ Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci.c | 41 +++++++++++++++++++++++++++++++++++++++-- drivers/mmc/host/sdhci.h | 11 +++++++++++ 2 files changed, 50 insertions(+), 2 deletions(-) -- 2.11.0 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index e9290a3439d5..d0655e1d2cc7 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -673,6 +673,27 @@ static void sdhci_adma_table_post(struct sdhci_host *host, } } +static void sdhci_calc_sw_timeout(struct sdhci_host *host, + struct mmc_command *cmd, + unsigned int target_timeout) +{ + struct mmc_host *mmc = host->mmc; + struct mmc_ios *ios = &mmc->ios; + struct mmc_data *data = cmd->data; + unsigned long long transfer_time; + + if (data) { + transfer_time = MMC_BLOCK_TRANSFER_TIME_MS(data->blksz, + ios->bus_width, + ios->clock); + /* calculate timeout for the entire data */ + host->data_timeout = (data->blocks * (target_timeout + + transfer_time)); + } else if (cmd->flags & MMC_RSP_BUSY) { + host->data_timeout = cmd->busy_timeout * MSEC_PER_SEC; + } +} + static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) { u8 count; @@ -732,8 +753,12 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) } if (count >= 0xF) { - DBG("Too large timeout 0x%x requested for CMD%d!\n", - count, cmd->opcode); + DBG("Too large timeout.. using SW timeout for CMD%d!\n", + cmd->opcode); + sdhci_calc_sw_timeout(host, cmd, target_timeout); + host->ier &= ~SDHCI_INT_DATA_TIMEOUT; + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); count = 0xE; } @@ -1198,6 +1223,14 @@ static void sdhci_finish_command(struct sdhci_host *host) { struct mmc_command *cmd = host->cmd; + if (host->data_timeout) { + unsigned long timeout; + + timeout = jiffies + + msecs_to_jiffies(host->data_timeout); + sdhci_mod_timer(host, host->cmd->mrq, timeout); + } + host->cmd = NULL; if (cmd->flags & MMC_RSP_PRESENT) { @@ -2341,6 +2374,10 @@ static bool sdhci_request_done(struct sdhci_host *host) return true; } + host->data_timeout = 0; + host->ier |= SDHCI_INT_DATA_TIMEOUT; + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); sdhci_del_timer(host, mrq); /* diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 54bc444c317f..e6e0278bea1a 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -332,6 +332,15 @@ struct sdhci_adma2_64_desc { /* Allow for a a command request and a data request at the same time */ #define SDHCI_MAX_MRQS 2 +/* + * Time taken for transferring one block. It is multiplied by a constant + * factor '2' to account for any errors + */ +#define MMC_BLOCK_TRANSFER_TIME_MS(blksz, bus_width, freq) \ + ((unsigned long long) \ + (2 * (((blksz) * MSEC_PER_SEC * \ + (8 / (bus_width))) / (freq)))) + enum sdhci_cookie { COOKIE_UNMAPPED, COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ @@ -546,6 +555,8 @@ struct sdhci_host { /* Host SDMA buffer boundary. */ u32 sdma_boundary; + unsigned long long data_timeout; + unsigned long private[0] ____cacheline_aligned; }; From patchwork Thu Dec 14 13:09:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 121930 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6787581qgn; Thu, 14 Dec 2017 05:13:09 -0800 (PST) X-Google-Smtp-Source: ACJfBov/s2t85PlqWW3X80KVcjmQ4HVA0RUU3u28mQzKiTuHcOVTIhD4Om2a94nOUTIeZRZhi4J4 X-Received: by 10.84.217.86 with SMTP id e22mr9444065plj.283.1513257189838; Thu, 14 Dec 2017 05:13:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513257189; cv=none; d=google.com; s=arc-20160816; b=vWK941fDcVTEh5eflOt4b3dV5MCyBGfrgXZ6Cp9QGjgza4PmAutFyJdrl69gnjzBTJ ee/qgb376GCWY4k6E74aZDOmR8LkYaPGt3CwKj7qYLkKLTvogRPP5axa0mo0FgB89a0o PUhx2Yp58MMRC2vQg+FMWSwVomzVmeKf361P0ai/oEXBhOVfj45G+IxR4Ia9PIxW6ovx eb9SkbmiIzLDL8eYZI/ZsHcchPcShTM6vYQJOgdnJtTDc/go5v7OgfqRBXPENRtgtoOw DXDcwouPVZfrOxdB2Ohe++F6jvpZquJDTY5MCdPWzdKGXiXS1nWGDkim1JEv499vU3+f OWQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=yOIqGviWZhO01z6f4Sv8o5kl3X22AISn9xEuLWbs3M4=; b=BN4HyhgY3xg6N1esmHiHeB5fH4NMlAWLGwlgMdEnagIDT54osVZbZBVHkUGGkjbCbq miEFZOUPfhq+RxtpphwhlAHMlz97KHUd2nUUNa77OnYnHCY2DwZaSG1cdvXE9x2AhlF4 QejycVj/JSkvS6D7UEk/2lnxOufn2IPLH1pQ5J8/MlOq2FujebiGbgtV4jJ33T4OZbha 38Hk/d/4ZS/6RBkwF4octg6ThW96z7To44uPL8NvgLan5OJKirezPcVUttOV+Jr1YMPZ x+uwHluOtYiNsEu0TX3IKZwdT7pJm0KJ/ZGqqOUmUa+tL7K71zdsJrSbrX8cY1zJk/F+ v/JA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Y1YUn0Rt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci-omap.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.11.0 diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index cddc3ad1331f..5e81e29383d9 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -767,6 +767,10 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = { .ops = &sdhci_omap_ops, }; +static const struct sdhci_omap_data k2g_data = { + .offset = 0x200, +}; + static const struct sdhci_omap_data dra7_data = { .offset = 0x200, .flags = SDHCI_OMAP_REQUIRE_IODELAY, @@ -774,6 +778,7 @@ static const struct sdhci_omap_data dra7_data = { static const struct of_device_id omap_sdhci_match[] = { { .compatible = "ti,dra7-sdhci", .data = &dra7_data }, + { .compatible = "ti,k2g-sdhci", .data = &k2g_data }, {}, }; MODULE_DEVICE_TABLE(of, omap_sdhci_match); @@ -882,6 +887,7 @@ static int sdhci_omap_probe(struct platform_device *pdev) int ret; u32 offset; struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; struct sdhci_host *host; struct sdhci_pltfm_host *pltfm_host; struct sdhci_omap_host *omap_host; @@ -908,6 +914,9 @@ static int sdhci_omap_probe(struct platform_device *pdev) return PTR_ERR(host); } + if (of_device_is_compatible(node, "ti,k2g-sdhci")) + host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; + pltfm_host = sdhci_priv(host); omap_host = sdhci_pltfm_priv(pltfm_host); omap_host->host = host; From patchwork Thu Dec 14 13:09:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 121926 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6785817qgn; Thu, 14 Dec 2017 05:11:42 -0800 (PST) X-Google-Smtp-Source: ACJfBotHNvzOhfuZ3fM3QY7NA22CBBiq4COKbKyOQef/aUtgGsUC/RiDpYG6KiMdGANaK/TFhZYA X-Received: by 10.98.113.196 with SMTP id m187mr9538231pfc.136.1513257102542; Thu, 14 Dec 2017 05:11:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513257102; cv=none; d=google.com; s=arc-20160816; b=Bre8rthf+0qu6KOSyDHRgyL7VRYDyNUx26x314q1NiQsnF+HAhRvFIrYlfCJqwZBpy o1+WJXRYvSfYmJ/qGsSuYsNqNe83SOYwbM+sfeRqZ8chHVF70a41lTAfOr+fBUuj6zjM 6h/e8IKDEwTuhqblTtJ7u9HZd0swzheGqC2WsXjXdesP359miEOnALNby2RXspJkSRO3 A2Lr+oOTnj23bMsy++6QvcCDd3YYzL+w0a7JrheGzRZ3MFsuO1XemeUQRYj/+Xk091x6 dWKZq3jew6o2zbfGSCNZZe/KjKWvOg0kLPhEI92iWnl7cPh47lfgDzmEM20POLEcSAEA 106Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=BfNcDUOqKnPkcktJdO/wTg1t42caxE0v/YoiAqiTzPc=; b=tVIhr9PaEhi1WTomdnB72LEpSn6OWeRzRcwy/14KzSKwVKKL07R2MYi8aabPDaLg0K mKMXzs9qS91hyfAtwiZRsBf0yg0TxkiWDlvi320tna+5g+W/kpYycUkPbUYx9GJMEtZ3 5bumFWd1ve+dWZPVEk88H4CYH8qxtVLFQA4CPUHOZ6LKs3Tn1JcoVD14WSrLYAq4I9xj wSkj2zEJuLl3xE+rqrN1CWCuFnhMjyqFXibj4o4h9CC71HVi5hlBZGRmaYHhVGPbEXmS 1qLi4cCgqzT74Zi8Keq7/ZCS5UZ7yYYrYsatLaJy4Luwd24prjxmHOZZv1kAHyWoIeQO zwxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qXVwLjYS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- arch/arm/mach-omap2/pdata-quirks.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) -- 2.11.0 diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 6b433fce65a5..92fb8828d57f 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -21,7 +21,7 @@ #include #include -#include +#include #include #include #include @@ -38,7 +38,7 @@ #include "soc.h" #include "hsmmc.h" -static struct omap_hsmmc_platform_data __maybe_unused mmc_pdata[2]; +static struct sdhci_omap_platform_data __maybe_unused mmc_pdata[2]; struct pdata_init { const char *compatible; @@ -435,21 +435,21 @@ static void __init omap5_uevm_legacy_init(void) #endif #ifdef CONFIG_SOC_DRA7XX -static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1; -static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2; -static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3; +static struct sdhci_omap_platform_data dra7_sdhci_data_mmc1; +static struct sdhci_omap_platform_data dra7_sdhci_data_mmc2; +static struct sdhci_omap_platform_data dra7_sdhci_data_mmc3; static void __init dra7x_evm_mmc_quirk(void) { if (omap_rev() == DRA752_REV_ES1_1 || omap_rev() == DRA752_REV_ES1_0) { - dra7_hsmmc_data_mmc1.version = "rev11"; - dra7_hsmmc_data_mmc1.max_freq = 96000000; + dra7_sdhci_data_mmc1.version = "rev11"; + dra7_sdhci_data_mmc1.max_freq = 96000000; - dra7_hsmmc_data_mmc2.version = "rev11"; - dra7_hsmmc_data_mmc2.max_freq = 48000000; + dra7_sdhci_data_mmc2.version = "rev11"; + dra7_sdhci_data_mmc2.max_freq = 48000000; - dra7_hsmmc_data_mmc3.version = "rev11"; - dra7_hsmmc_data_mmc3.max_freq = 48000000; + dra7_sdhci_data_mmc3.version = "rev11"; + dra7_sdhci_data_mmc3.max_freq = 48000000; } } #endif @@ -582,12 +582,12 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { &omap4_iommu_pdata), #endif #ifdef CONFIG_SOC_DRA7XX - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x4809c000, "4809c000.mmc", - &dra7_hsmmc_data_mmc1), - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480b4000, "480b4000.mmc", - &dra7_hsmmc_data_mmc2), - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", - &dra7_hsmmc_data_mmc3), + OF_DEV_AUXDATA("ti,dra7-sdhci", 0x4809c000, "4809c000.mmc", + &dra7_sdhci_data_mmc1), + OF_DEV_AUXDATA("ti,dra7-sdhci", 0x480b4000, "480b4000.mmc", + &dra7_sdhci_data_mmc2), + OF_DEV_AUXDATA("ti,dra7-sdhci", 0x480ad000, "480ad000.mmc", + &dra7_sdhci_data_mmc3), #endif /* Common auxdata */ OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata),