From patchwork Mon Mar 13 13:43:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95232 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1178153qgd; Mon, 13 Mar 2017 06:45:22 -0700 (PDT) X-Received: by 10.98.112.134 with SMTP id l128mr37436369pfc.81.1489412722195; Mon, 13 Mar 2017 06:45:22 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b14si11468561pge.221.2017.03.13.06.45.21; Mon, 13 Mar 2017 06:45:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752183AbdCMNpF (ORCPT + 25 others); Mon, 13 Mar 2017 09:45:05 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:35787 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752748AbdCMNo2 (ORCPT ); Mon, 13 Mar 2017 09:44:28 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DDhgQl025489; Mon, 13 Mar 2017 08:43:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489412622; bh=Nmg0DqhHaYoPPmmZsy4VXol2d3v8ZUeWJftsvQrVWv0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dESMdUsgeIbINBwtf/lpKYemh+3kAadJVSR8m20+hjKQZ/rthiibB09AAe9NTeYDG W9Ahr9Z4Veawphd/gxfm2WVfX2Y/m8rjRnvpfc+/NfaK7yxDLGnnGuDRODHW6NvgPb Yz0pPPtlQ4f+CVsOWXyP+dT7U56yWS5lVLtAArjc= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DDhg3k019297; Mon, 13 Mar 2017 08:43:42 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:43:41 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DDhZvj017427; Mon, 13 Mar 2017 08:43:39 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , Niklas Cassel , , , , CC: , Subject: [PATCH v4 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup Date: Mon, 13 Mar 2017 19:13:22 +0530 Message-ID: <20170313134328.1588-2-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170313134328.1588-1-kishon@ti.com> References: <20170313134328.1588-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some platforms (like dra7xx) require only the least 28 bits of the corresponding 32 bit CPU address to be programmed in the address translation unit. This modified address is stored in io_base/mem_base/ cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for host mode where the address range is fixed, device mode requires different addresses to be programmed based on the host buffer address. Add a new ops to get the least 28 bits of the corresponding 32 bit CPU address and invoke it before programming the address translation unit. Acked-by: Joao Pinto Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-designware.c | 3 +++ drivers/pci/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+) -- 2.11.0 diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 7e1fb7d6643c..3eaf3ccdc118 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, { u32 retries, val; + if (pci->ops->cpu_addr_fixup) + cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr); + if (pci->iatu_unroll_enabled) { dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(cpu_addr)); diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index cd3b8713fe50..8f3dcb2b099b 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -143,6 +143,7 @@ struct pcie_port { }; struct dw_pcie_ops { + u64 (*cpu_addr_fixup)(u64 cpu_addr); u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg); void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val); int (*link_up)(struct dw_pcie *pcie); From patchwork Mon Mar 13 13:43:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95228 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1177805qgd; Mon, 13 Mar 2017 06:44:24 -0700 (PDT) X-Received: by 10.99.63.71 with SMTP id m68mr36739781pga.115.1489412664350; Mon, 13 Mar 2017 06:44:24 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 2si11508861pfd.116.2017.03.13.06.44.24; Mon, 13 Mar 2017 06:44:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753321AbdCMNoX (ORCPT + 25 others); Mon, 13 Mar 2017 09:44:23 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:35788 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752496AbdCMNoM (ORCPT ); Mon, 13 Mar 2017 09:44:12 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DDhmxU025501; Mon, 13 Mar 2017 08:43:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489412628; bh=yRy0CFeX0e+JV6QGIHAw9vXC4/n1jFF+CcnVrnsu9LE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=G5S4KbF5zye+lbD0JyqYo8BYz3fyPxpaOWVgIg7EA8N+BhP17kKnM51L4J6ZGwfDT 9OLkl19jD3RFzp/JLAwvOtZAZL4e8i7S25cgeMcCZFp8Ar5BNea2K7eOF6Nvs02/Nq dO28zGK/8ka+BRHyZKNKjsDZ7Ndt99XvsIr49Muw= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DDhmo4021661; Mon, 13 Mar 2017 08:43:48 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:43:47 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DDhZvl017427; Mon, 13 Mar 2017 08:43:45 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , Niklas Cassel , , , , CC: , Subject: [PATCH v4 3/7] PCI: dwc: artpec6: Populate cpu_addr_fixup ops Date: Mon, 13 Mar 2017 19:13:24 +0530 Message-ID: <20170313134328.1588-4-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170313134328.1588-1-kishon@ti.com> References: <20170313134328.1588-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding cpu address. Cc: Niklas Cassel Acked-by: Niklas Cassel Acked-by: Joao Pinto Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-artpec6.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) -- 2.11.0 diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c index fcd3ef845883..5b3b3afc0edb 100644 --- a/drivers/pci/dwc/pcie-artpec6.c +++ b/drivers/pci/dwc/pcie-artpec6.c @@ -78,6 +78,11 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u regmap_write(artpec6_pcie->regmap, offset, val); } +static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr) +{ + return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR; +} + static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) { struct dw_pcie *pci = artpec6_pcie->pci; @@ -142,11 +147,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) */ dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN); - pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR; - pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR; - pp->cfg0_base &= ARTPEC6_CPU_TO_BUS_ADDR; - pp->cfg1_base &= ARTPEC6_CPU_TO_BUS_ADDR; - /* setup root complex */ dw_pcie_setup_rc(pp); @@ -234,6 +234,10 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie, return 0; } +static const struct dw_pcie_ops dw_pcie_ops = { + .cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup, +}; + static int artpec6_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -252,6 +256,7 @@ static int artpec6_pcie_probe(struct platform_device *pdev) return -ENOMEM; pci->dev = dev; + pci->ops = &dw_pcie_ops; artpec6_pcie->pci = pci; From patchwork Mon Mar 13 13:43:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95233 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1178245qgd; Mon, 13 Mar 2017 06:45:38 -0700 (PDT) X-Received: by 10.84.168.69 with SMTP id e63mr47465641plb.124.1489412738682; Mon, 13 Mar 2017 06:45:38 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 38si510067pld.335.2017.03.13.06.45.38; Mon, 13 Mar 2017 06:45:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753407AbdCMNpc (ORCPT + 25 others); Mon, 13 Mar 2017 09:45:32 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:64705 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752982AbdCMNpY (ORCPT ); Mon, 13 Mar 2017 09:45:24 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DDi6Lo012135; Mon, 13 Mar 2017 08:44:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489412646; bh=EMSTZF6u5XJVUorXa5duBKPuseetyrEcTnW9wJwRfpo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mXeHFqbFnvr+mNZcBgjkNeozyAVab7hZz2wfBeIQmdutcUrqxo7KC/QWGTb7UcLXU 6FeGq1d9TF+U6p2hSdODjtnj9wUrBv7e3Pcv9kpUUiJBy2Us9FbfiiXsnyVw4J3L7k d8Ln95Mq4dpGBXPBz7fWjPjFhlIDsSexowoh6tDA= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DDi1SB021824; Mon, 13 Mar 2017 08:44:01 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:44:00 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DDhZvp017427; Mon, 13 Mar 2017 08:43:57 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , Niklas Cassel , , , , CC: , , Keerthy Subject: [PATCH v4 7/7] PCI: dwc: dra7xx: Push request_irq call to the bottom of probe Date: Mon, 13 Mar 2017 19:13:28 +0530 Message-ID: <20170313134328.1588-8-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170313134328.1588-1-kishon@ti.com> References: <20170313134328.1588-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Keerthy Currently devm_request_irq is being called before base, pci fields of dra7xx_pcie structure are populated. It is called even before pm_runtime_enable and pm_runtime_get_sync are called. This will lead to exceptions if in case an interrupt is triggered before the all of the above are done. Hence push the devm_request_irq call to the end of the probe. Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.11.0 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 07c45ec07662..7c9ed6a6675c 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -410,13 +410,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) return -EINVAL; } - ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler, - IRQF_SHARED, "dra7xx-pcie-main", dra7xx); - if (ret) { - dev_err(dev, "failed to request irq\n"); - return ret; - } - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf"); base = devm_ioremap_nocache(dev, res->start, resource_size(res)); if (!base) @@ -478,6 +471,13 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) if (ret < 0) goto err_gpio; + ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler, + IRQF_SHARED, "dra7xx-pcie-main", dra7xx); + if (ret) { + dev_err(dev, "failed to request irq\n"); + goto err_gpio; + } + return 0; err_gpio: