From patchwork Wed Dec 13 11:58:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 121733 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5373478qgn; Wed, 13 Dec 2017 04:00:55 -0800 (PST) X-Google-Smtp-Source: ACJfBovaI6ol5/D4js92dWr8jszGl1hJrJibrT2Sh1GIIZJv0Nz/bv/SZN2rhg720oquzZI7zDiD X-Received: by 10.99.179.12 with SMTP id i12mr4893144pgf.199.1513166455795; Wed, 13 Dec 2017 04:00:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513166455; cv=none; d=google.com; s=arc-20160816; b=M1yBwZ5yjxVOXEHjuSs9X6bgISdRLECGbFCoRZOOr/pvAQTda7Q8AQkZq0dRYY7L4Y 26lyr9I1dmgE/80wOLa1EyZjcjWoMDX8M45eBL1BzOH/xv2JB+t45mXy5WnHsLCrcDqu 5vd33brngI56Jb5FhzdaZEpAqEHvUT/Ch9uVJvdJUQO3KoJ19BQat7zJkSNfXdnQbd6y 1AITNNds07cMi3EW+UhK0w83Eppw7odWgTba/Vymni1AqGYLD9f4678TrARp7owz+4w4 Jxs0++MSXZRaLa4gJSX0Z18KLwBhc/LMbpV4+PyH4mlXH6wpi22yXQ3JGZk7Z9oobqMr 0QTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=oO1mG/sSKOfoqtZeLJRtSDuVzRi74oU1thRKN1ifAFM=; b=YPQ2xXvkZSw+ybX/zDjC9kcLtVRGUZRmrfF/WMln1LDzjYu76q89q2ghMxIurHp88t IsvQIvO5xp1pQrCZJ5HJYR2EDinnnYUio1Fz4CEI/waHDUUGnGGofKDuMbTdo2KmezBb WMIJGKf68oa4ycRZm90NPflV7LX/prlzu3HTcoeBHqphS1APeLOTzw+qspBPTCK/HSfN 5QElLw4Npha5K3Xz4JhhBEQuLmtCx+INuY7pg6lKPG6H1Uw6Z4DsxexETqb9Eb8k+Jay oK0jMGO/xeDzH9Ifck2Q3Wj7A90xl+eetQnYTDXgRIDNbJtipL7lwCeCouIXMF58Gnvy 2JVg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t8si1285240pfh.310.2017.12.13.04.00.55; Wed, 13 Dec 2017 04:00:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752379AbdLMMAy (ORCPT + 7 others); Wed, 13 Dec 2017 07:00:54 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2676 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751853AbdLMMAy (ORCPT ); Wed, 13 Dec 2017 07:00:54 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 283DD23980B3F; Wed, 13 Dec 2017 20:00:38 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.361.1; Wed, 13 Dec 2017 20:00:31 +0800 From: Shameer Kolothum To: , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v11 1/3] ACPI/IORT: Add msi address regions reservation helper Date: Wed, 13 Dec 2017 11:58:28 +0000 Message-ID: <20171213115830.61872-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20171213115830.61872-1-shameerali.kolothum.thodi@huawei.com> References: <20171213115830.61872-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On some platforms msi parent address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add a helper function that retrieves ITS address regions - the msi parent - through IORT device <-> ITS mappings and reserves it so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. The function checks for the smmu model number and only applies the msi reservation if the platform requires it. Signed-off-by: Shameer Kolothum --- drivers/acpi/arm64/iort.c | 112 +++++++++++++++++++++++++++++++++++++-- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 ++- 3 files changed, 117 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 95255ec..3e0ce65 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -39,6 +39,7 @@ struct iort_its_msi_chip { struct list_head list; struct fwnode_handle *fw_node; + phys_addr_t base_addr; u32 translation_id; }; @@ -161,14 +162,16 @@ typedef acpi_status (*iort_find_node_callback) static DEFINE_SPINLOCK(iort_msi_chip_lock); /** - * iort_register_domain_token() - register domain token and related ITS ID - * to the list from where we can get it back later on. + * iort_register_domain_token() - register domain token along with related + * ITS ID and base address to the list from where we can get it back later on. * @trans_id: ITS ID. + * @base: ITS base address. * @fw_node: Domain token. * * Returns: 0 on success, -ENOMEM if no memory when allocating list element */ -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node) { struct iort_its_msi_chip *its_msi_chip; @@ -178,6 +181,7 @@ int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) its_msi_chip->fw_node = fw_node; its_msi_chip->translation_id = trans_id; + its_msi_chip->base_addr = base; spin_lock(&iort_msi_chip_lock); list_add(&its_msi_chip->list, &iort_msi_chip_list); @@ -581,6 +585,24 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) return -ENODEV; } +static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base) +{ + struct iort_its_msi_chip *its_msi_chip; + int ret = -ENODEV; + + spin_lock(&iort_msi_chip_lock); + list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) { + if (its_msi_chip->translation_id == its_id) { + *base = its_msi_chip->base_addr; + ret = 0; + break; + } + } + spin_unlock(&iort_msi_chip_lock); + + return ret; +} + /** * iort_dev_find_its_id() - Find the ITS identifier for a device * @dev: The device. @@ -740,6 +762,25 @@ static int __maybe_unused __get_pci_rid(struct pci_dev *pdev, u16 alias, return 0; } +static __maybe_unused struct acpi_iort_node *iort_get_msi_resv_iommu( + struct device *dev) +{ + struct acpi_iort_node *iommu; + struct iommu_fwspec *fwspec = dev->iommu_fwspec; + + iommu = iort_get_iort_node(fwspec->iommu_fwnode); + + if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) { + struct acpi_iort_smmu_v3 *smmu; + + smmu = (struct acpi_iort_smmu_v3 *)iommu->node_data; + if (smmu->model == ACPI_IORT_SMMU_V3_HISILICON_HI161X) + return iommu; + } + + return NULL; +} + static int arm_smmu_iort_xlate(struct device *dev, u32 streamid, struct fwnode_handle *fwnode, const struct iommu_ops *ops) @@ -782,6 +823,69 @@ static inline int iort_add_device_replay(const struct iommu_ops *ops, return err; } + +/** + * iort_iommu_msi_get_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @head: Reserved region list from iommu_get_resv_regions() + * + * Returns: Number of msi reserved regions on success (0 if platform + * doesn't require the reservation or no associated msi regions), + * appropriate error value otherwise. The ITS interrupt translation + * spaces (ITS_base + SZ_64K, SZ_64K) associated with the device + * are the msi reserved regions. + */ +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ + struct acpi_iort_its_group *its; + struct acpi_iort_node *iommu_node, *its_node = NULL; + int i, resv = 0; + + iommu_node = iort_get_msi_resv_iommu(dev); + if (!iommu_node) + return 0; + + /* + * Current logic to reserve ITS regions relies on HW topologies + * where a given PCI or named component maps its IDs to only one + * ITS group; if a PCI or named component can map its IDs to + * different ITS groups through IORT mappings this function has + * to be reworked to ensure we reserve regions for all ITS groups + * a given PCI or named component may map IDs to. + */ + + for (i = 0; i < dev->iommu_fwspec->num_ids; i++) { + its_node = iort_node_map_id(iommu_node, + dev->iommu_fwspec->ids[i], + NULL, IORT_MSI_TYPE); + if (its_node) + break; + } + + if (!its_node) + return 0; + + /* Move to ITS specific data */ + its = (struct acpi_iort_its_group *)its_node->node_data; + + for (i = 0; i < its->its_count; i++) { + phys_addr_t base; + + if (!iort_find_its_base(its->identifiers[i], &base)) { + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct iommu_resv_region *region; + + region = iommu_alloc_resv_region(base + SZ_64K, SZ_64K, + prot, IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv++; + } + } + } + + return (resv == its->its_count) ? resv : -ENODEV; +} #else static inline const struct iommu_ops *iort_fwspec_iommu_ops( struct iommu_fwspec *fwspec) @@ -789,6 +893,8 @@ static inline const struct iommu_ops *iort_fwspec_iommu_ops( static inline int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) { return 0; } +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ return 0; } #endif static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node, diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 4039e64..d4cff12 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -3450,7 +3450,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, return -ENOMEM; } - err = iort_register_domain_token(its_entry->translation_id, dom_handle); + err = iort_register_domain_token(its_entry->translation_id, res.start, + dom_handle); if (err) { pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", &res.start, its_entry->translation_id); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 2f7a292..38cd77b 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -26,7 +26,8 @@ #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL) #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node); +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node); void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); #ifdef CONFIG_ACPI_IORT @@ -38,6 +39,7 @@ /* IOMMU interface */ void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *size); const struct iommu_ops *iort_iommu_configure(struct device *dev); +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head); #else static inline void acpi_iort_init(void) { } static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id) @@ -52,6 +54,9 @@ static inline void iort_dma_setup(struct device *dev, u64 *dma_addr, static inline const struct iommu_ops *iort_iommu_configure( struct device *dev) { return NULL; } +static inline +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ return 0; } #endif #endif /* __ACPI_IORT_H__ */ From patchwork Wed Dec 13 11:58:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 121734 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5373736qgn; Wed, 13 Dec 2017 04:01:06 -0800 (PST) X-Google-Smtp-Source: ACJfBotaSu+9VAW1+ppfbB6pzMKTmd1hbCWgKQLTFF+YWtJjrxx2Vy3YT10JoXQbvaSZMlRyOKHm X-Received: by 10.84.235.2 with SMTP id o2mr5628942plk.64.1513166465925; Wed, 13 Dec 2017 04:01:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513166465; cv=none; d=google.com; s=arc-20160816; b=hhrAXjsj0Hs2gBUDnmXUq/e1zNdpNA44550IArEJ+DgM+AQ9JiymhAgNe6u1JcQCVa txP5lGxuIiI4rGlXrAsfs7OXzJZwiIKB9RwB6L4zCFfnOw04hTC9+sKCILnFa4lTVrhW dR0Rcj4PfRYjkVqUyAObD2Yp+JExw8mW+4BQRkOTdeBX2iAMJFR0LhAQj5P5wrVmulCP 2nyUzf3kvr5oftmrCCtXFsaCAGeF+cpXI5BdV586VXkNTL+GKNe+7QfwUStvsYjoc/jN +Q1rg9W3AYlJq3BSUioVTYr8fpWqooL72/lsHZiNY/A0IVLhfBVIysVqaQkSnjVG5iul Cqxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=o19kW1wLU8MDIujGimkwGPqEQv4H208yUdU1wSK/zyc=; b=xVLmgfFgrqjqQyyDYJuU/8CR/RcentPP+E73QA9IzolKN1u4pUN9qqluDFXKSwgjMb Xs4bizvl+oAChRrl02t71Vb8jiLrk/dlUuQBbNYVdDw3JszYtaQlvRQ9hQKYqRjD2uIl zMvZZG3ru+JO1hld2kzJxdrm8G80R5ecMPdoxtz8lmA3JU1kYceynJJRjQtBAVCRrSRK TB2RnggZAHilMYdftTXRULuy0GVLiCjuIESCZNFcPacE/56ut57ya85Nnc838NySibGY h+p4yLo3665b1V1CC4E4/973Hq8kCM6TfSQoTrP0AF+YtXHgZjQ8mjkqJWYxbzt+DCPl dT5g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t8si1285240pfh.310.2017.12.13.04.01.05; Wed, 13 Dec 2017 04:01:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752623AbdLMMBE (ORCPT + 7 others); Wed, 13 Dec 2017 07:01:04 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2283 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752603AbdLMMBE (ORCPT ); Wed, 13 Dec 2017 07:01:04 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 70049B80BB334; Wed, 13 Dec 2017 20:00:47 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.361.1; Wed, 13 Dec 2017 20:00:39 +0800 From: Shameer Kolothum To: , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v11 3/3] arm64:dts:hisilicon Disable hisilicon smmu node on hip06/hip07 Date: Wed, 13 Dec 2017 11:58:30 +0000 Message-ID: <20171213115830.61872-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20171213115830.61872-1-shameerali.kolothum.thodi@huawei.com> References: <20171213115830.61872-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMUv3 mappings for MSI transactions. PCIe controller on these platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This makes it difficult for these platforms to have SMMU translation for MSI. In order to workaround this, ARM SMMUv3 driver requires a quirk to treat the MSI regions separately. Such a quirk is currently missing for DT based systems and therefore we need to explicitly disable the hip06/hip07 smmu entries in dts. Signed-off-by: Shameer Kolothum Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 55 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 24 ++++++++++++++ 2 files changed, 79 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index a049b64..d0d5933 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -291,6 +291,13 @@ #interrupt-cells = <2>; num-pins = <128>; }; + + mbigen_pcie0: intc_pcie0 { + msi-parent = <&its_dsa 0x40085>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <10>; + }; }; mbigen_dsa@c0080000 { @@ -312,6 +319,30 @@ }; }; + /** HiSilicon erratum 161010801: This describes the limitation + * of HiSilicon platforms hip06/hip07 to support the SMMUv3 + * mappings for PCIe MSI transactions. + * PCIe controller on these platforms has to differentiate the + * MSI payload against other DMA payload and has to modify the + * MSI payload. This makes it difficult for these platforms to + * have a SMMU translation for MSI. In order to workaround this, + * ARM SMMUv3 driver requires a quirk to treat the MSI regions + * separately. Such a quirk is currently missing for DT based + * systems. Hence please make sure that the smmu pcie node on + * hip06 is disabled as this will break the PCIe functionality + * when iommu-map entry is used along with the PCIe node. + * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html + */ + smmu0: smmu_pcie { + compatible = "arm,smmu-v3"; + reg = <0x0 0xa0040000 0x0 0x20000>; + #iommu-cells = <1>; + dma-coherent; + smmu-cb-memtype = <0x0 0x1>; + hisilicon,broken-prefetch-cmd; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -676,6 +707,30 @@ <637 1>,<638 1>,<639 1>; status = "disabled"; }; + + pcie0: pcie@a0090000 { + compatible = "hisilicon,hip06-pcie-ecam"; + reg = <0 0xb0000000 0 0x2000000>, + <0 0xa0090000 0 0x10000>; + bus-range = <0 31>; + msi-map = <0x0000 &its_dsa 0x0000 0x2000>; + msi-map-mask = <0xffff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 + 0x5ff0000 0x01000000 0 0 0 0xb7ff0000 + 0 0x10000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 + 0x0 0 0 2 &mbigen_pcie0 650 4 + 0x0 0 0 3 &mbigen_pcie0 650 4 + 0x0 0 0 4 &mbigen_pcie0 650 4>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 2c01a21..58fe013 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1083,6 +1083,30 @@ }; }; + /** HiSilicon erratum 161010801: This describes the limitation + * of HiSilicon platforms hip06/hip07 to support the SMMUv3 + * mappings for PCIe MSI transactions. + * PCIe controller on these platforms has to differentiate the + * MSI payload against other DMA payload and has to modify the + * MSI payload. This makes it difficult for these platforms to + * have a SMMU translation for MSI. In order to workaround this, + * ARM SMMUv3 driver requires a quirk to treat the MSI regions + * separately. Such a quirk is currently missing for DT based + * systems. Hence please make sure that the smmu pcie node on + * hip06 is disabled as this will break the PCIe functionality + * when iommu-map entry is used along with the PCIe node. + * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html + */ + smmu0: smmu_pcie { + compatible = "arm,smmu-v3"; + reg = <0x0 0xa0040000 0x0 0x20000>; + #iommu-cells = <1>; + dma-coherent; + smmu-cb-memtype = <0x0 0x1>; + hisilicon,broken-prefetch-cmd; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>;